[ceph.git] / ceph / src / isa-l / include / reg_sizes.asm

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  Copyright(c) 2011-2015 Intel Corporation All rights reserved.
;
;  Redistribution and use in source and binary forms, with or without
;  modification, are permitted provided that the following conditions
;  are met:
;    * Redistributions of source code must retain the above copyright
;      notice, this list of conditions and the following disclaimer.
;    * Redistributions in binary form must reproduce the above copyright
;      notice, this list of conditions and the following disclaimer in
;      the documentation and/or other materials provided with the
;      distribution.
;    * Neither the name of Intel Corporation nor the names of its
;      contributors may be used to endorse or promote products derived
;      from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

%ifndef _REG_SIZES_ASM_
%define _REG_SIZES_ASM_

%ifndef AS_FEATURE_LEVEL
%define AS_FEATURE_LEVEL 4
%endif

%define EFLAGS_HAS_CPUID        (1<<21)
%define FLAG_CPUID1_ECX_CLMUL   (1<<1)
%define FLAG_CPUID1_EDX_SSE2    (1<<26)
%define FLAG_CPUID1_ECX_SSE3	(1)
%define FLAG_CPUID1_ECX_SSE4_1  (1<<19)
%define FLAG_CPUID1_ECX_SSE4_2  (1<<20)
%define FLAG_CPUID1_ECX_POPCNT  (1<<23)
%define FLAG_CPUID1_ECX_AESNI   (1<<25)
%define FLAG_CPUID1_ECX_OSXSAVE (1<<27)
%define FLAG_CPUID1_ECX_AVX     (1<<28)
%define FLAG_CPUID1_EBX_AVX2    (1<<5)

%define FLAG_CPUID7_EBX_AVX2           (1<<5)
%define FLAG_CPUID7_EBX_AVX512F        (1<<16)
%define FLAG_CPUID7_EBX_AVX512DQ       (1<<17)
%define FLAG_CPUID7_EBX_AVX512IFMA     (1<<21)
%define FLAG_CPUID7_EBX_AVX512PF       (1<<26)
%define FLAG_CPUID7_EBX_AVX512ER       (1<<27)
%define FLAG_CPUID7_EBX_AVX512CD       (1<<28)
%define FLAG_CPUID7_EBX_AVX512BW       (1<<30)
%define FLAG_CPUID7_EBX_AVX512VL       (1<<31)

%define FLAG_CPUID7_ECX_AVX512VBMI     (1<<1)
%define FLAG_CPUID7_ECX_AVX512VBMI2    (1 << 6)
%define FLAG_CPUID7_ECX_GFNI           (1 << 8)
%define FLAG_CPUID7_ECX_VAES           (1 << 9)
%define FLAG_CPUID7_ECX_VPCLMULQDQ     (1 << 10)
%define FLAG_CPUID7_ECX_VNNI           (1 << 11)
%define FLAG_CPUID7_ECX_BITALG         (1 << 12)
%define FLAG_CPUID7_ECX_VPOPCNTDQ      (1 << 14)

%define FLAGS_CPUID7_EBX_AVX512_G1 (FLAG_CPUID7_EBX_AVX512F | FLAG_CPUID7_EBX_AVX512VL | FLAG_CPUID7_EBX_AVX512BW | FLAG_CPUID7_EBX_AVX512CD | FLAG_CPUID7_EBX_AVX512DQ)
%define FLAGS_CPUID7_ECX_AVX512_G2 (FLAG_CPUID7_ECX_AVX512VBMI2 | FLAG_CPUID7_ECX_GFNI | FLAG_CPUID7_ECX_VAES | FLAG_CPUID7_ECX_VPCLMULQDQ | FLAG_CPUID7_ECX_VNNI | FLAG_CPUID7_ECX_BITALG | FLAG_CPUID7_ECX_VPOPCNTDQ)

%define FLAG_XGETBV_EAX_XMM            (1<<1)
%define FLAG_XGETBV_EAX_YMM            (1<<2)
%define FLAG_XGETBV_EAX_XMM_YMM        0x6
%define FLAG_XGETBV_EAX_ZMM_OPM        0xe0

%define FLAG_CPUID1_EAX_AVOTON     0x000406d0
%define FLAG_CPUID1_EAX_STEP_MASK  0xfffffff0

; define d and w variants for registers

%define	raxd	eax
%define raxw	ax
%define raxb	al

%define	rbxd	ebx
%define rbxw	bx
%define rbxb	bl

%define	rcxd	ecx
%define rcxw	cx
%define rcxb	cl

%define	rdxd	edx
%define rdxw	dx
%define rdxb	dl

%define	rsid	esi
%define rsiw	si
%define rsib	sil

%define	rdid	edi
%define rdiw	di
%define rdib	dil

%define	rbpd	ebp
%define rbpw	bp
%define rbpb	bpl

%define ymm0x xmm0
%define ymm1x xmm1
%define ymm2x xmm2
%define ymm3x xmm3
%define ymm4x xmm4
%define ymm5x xmm5
%define ymm6x xmm6
%define ymm7x xmm7
%define ymm8x xmm8
%define ymm9x xmm9
%define ymm10x xmm10
%define ymm11x xmm11
%define ymm12x xmm12
%define ymm13x xmm13
%define ymm14x xmm14
%define ymm15x xmm15

%define zmm0x xmm0
%define zmm1x xmm1
%define zmm2x xmm2
%define zmm3x xmm3
%define zmm4x xmm4
%define zmm5x xmm5
%define zmm6x xmm6
%define zmm7x xmm7
%define zmm8x xmm8
%define zmm9x xmm9
%define zmm10x xmm10
%define zmm11x xmm11
%define zmm12x xmm12
%define zmm13x xmm13
%define zmm14x xmm14
%define zmm15x xmm15
%define zmm16x xmm16
%define zmm17x xmm17
%define zmm18x xmm18
%define zmm19x xmm19
%define zmm20x xmm20
%define zmm21x xmm21
%define zmm22x xmm22
%define zmm23x xmm23
%define zmm24x xmm24
%define zmm25x xmm25
%define zmm26x xmm26
%define zmm27x xmm27
%define zmm28x xmm28
%define zmm29x xmm29
%define zmm30x xmm30
%define zmm31x xmm31

%define zmm0y ymm0
%define zmm1y ymm1
%define zmm2y ymm2
%define zmm3y ymm3
%define zmm4y ymm4
%define zmm5y ymm5
%define zmm6y ymm6
%define zmm7y ymm7
%define zmm8y ymm8
%define zmm9y ymm9
%define zmm10y ymm10
%define zmm11y ymm11
%define zmm12y ymm12
%define zmm13y ymm13
%define zmm14y ymm14
%define zmm15y ymm15
%define zmm16y ymm16
%define zmm17y ymm17
%define zmm18y ymm18
%define zmm19y ymm19
%define zmm20y ymm20
%define zmm21y ymm21
%define zmm22y ymm22
%define zmm23y ymm23
%define zmm24y ymm24
%define zmm25y ymm25
%define zmm26y ymm26
%define zmm27y ymm27
%define zmm28y ymm28
%define zmm29y ymm29
%define zmm30y ymm30
%define zmm31y ymm31

%define DWORD(reg) reg %+ d
%define WORD(reg)  reg %+ w
%define BYTE(reg)  reg %+ b

%define XWORD(reg) reg %+ x

%ifidn __OUTPUT_FORMAT__,elf32
section .note.GNU-stack noalloc noexec nowrite progbits
section .text
%endif
%ifidn __OUTPUT_FORMAT__,elf64
 %define __x86_64__
section .note.GNU-stack noalloc noexec nowrite progbits
section .text
%endif
%ifidn __OUTPUT_FORMAT__,win64
 %define __x86_64__
%endif
%ifidn __OUTPUT_FORMAT__,macho64
 %define __x86_64__
%endif

%ifdef __x86_64__
 %define endbranch db 0xf3, 0x0f, 0x1e, 0xfa
%else
 %define endbranch db 0xf3, 0x0f, 0x1e, 0xfb
%endif

%ifdef REL_TEXT
 %define WRT_OPT
%elifidn __OUTPUT_FORMAT__, elf64
 %define WRT_OPT        wrt ..plt
%else
 %define WRT_OPT
%endif

%macro mk_global 1-3
  %ifdef __NASM_VER__
    %ifidn __OUTPUT_FORMAT__, macho64
	global %1
    %elifidn __OUTPUT_FORMAT__, win64
	global %1
    %else
	global %1:%2 %3
    %endif
  %else
	global %1:%2 %3
  %endif
%endmacro


; Fixes for nasm lack of MS proc helpers
%ifdef __NASM_VER__
  %ifidn __OUTPUT_FORMAT__, win64
    %macro alloc_stack 1
	sub	rsp, %1
    %endmacro

    %macro proc_frame 1
	%1:
    %endmacro

    %macro save_xmm128 2
	movdqa	[rsp + %2], %1
    %endmacro

    %macro save_reg 2
	mov	[rsp + %2], %1
    %endmacro

    %macro rex_push_reg	1
	push	%1
    %endmacro

    %macro push_reg 1
	push	%1
    %endmacro

    %define end_prolog
  %endif

  %define endproc_frame
%endif

%ifidn __OUTPUT_FORMAT__, macho64
 %define elf64 macho64
 mac_equ equ 1
%endif

%macro slversion 4
	section .text
	global %1_slver_%2%3%4
	global %1_slver
	%1_slver:
	%1_slver_%2%3%4:
		dw 0x%4
		db 0x%3, 0x%2
%endmacro

%endif ; ifndef _REG_SIZES_ASM_
Commit	Line	Data
7c673cae FG	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	2	; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
	3	;
	4	; Redistribution and use in source and binary forms, with or without
f91f0fd5	5	; modification, are permitted provided that the following conditions
7c673cae FG	6	; are met:
	7	; * Redistributions of source code must retain the above copyright
	8	; notice, this list of conditions and the following disclaimer.
	9	; * Redistributions in binary form must reproduce the above copyright
	10	; notice, this list of conditions and the following disclaimer in
	11	; the documentation and/or other materials provided with the
	12	; distribution.
	13	; * Neither the name of Intel Corporation nor the names of its
	14	; contributors may be used to endorse or promote products derived
	15	; from this software without specific prior written permission.
	16	;
	17	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	18	; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	19	; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	20	; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	21	; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	22	; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	23	; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	27	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	29
	30	%ifndef _REG_SIZES_ASM_
	31	%define _REG_SIZES_ASM_
	32
f91f0fd5 TL	33	%ifndef AS_FEATURE_LEVEL
	34	%define AS_FEATURE_LEVEL 4
	35	%endif
	36
7c673cae FG	37	%define EFLAGS_HAS_CPUID (1<<21)
	38	%define FLAG_CPUID1_ECX_CLMUL (1<<1)
	39	%define FLAG_CPUID1_EDX_SSE2 (1<<26)
	40	%define FLAG_CPUID1_ECX_SSE3 (1)
	41	%define FLAG_CPUID1_ECX_SSE4_1 (1<<19)
	42	%define FLAG_CPUID1_ECX_SSE4_2 (1<<20)
	43	%define FLAG_CPUID1_ECX_POPCNT (1<<23)
	44	%define FLAG_CPUID1_ECX_AESNI (1<<25)
	45	%define FLAG_CPUID1_ECX_OSXSAVE (1<<27)
	46	%define FLAG_CPUID1_ECX_AVX (1<<28)
	47	%define FLAG_CPUID1_EBX_AVX2 (1<<5)
	48
	49	%define FLAG_CPUID7_EBX_AVX2 (1<<5)
	50	%define FLAG_CPUID7_EBX_AVX512F (1<<16)
	51	%define FLAG_CPUID7_EBX_AVX512DQ (1<<17)
	52	%define FLAG_CPUID7_EBX_AVX512IFMA (1<<21)
	53	%define FLAG_CPUID7_EBX_AVX512PF (1<<26)
	54	%define FLAG_CPUID7_EBX_AVX512ER (1<<27)
	55	%define FLAG_CPUID7_EBX_AVX512CD (1<<28)
	56	%define FLAG_CPUID7_EBX_AVX512BW (1<<30)
	57	%define FLAG_CPUID7_EBX_AVX512VL (1<<31)
f91f0fd5	58
7c673cae	59	%define FLAG_CPUID7_ECX_AVX512VBMI (1<<1)
f91f0fd5 TL	60	%define FLAG_CPUID7_ECX_AVX512VBMI2 (1 << 6)
	61	%define FLAG_CPUID7_ECX_GFNI (1 << 8)
	62	%define FLAG_CPUID7_ECX_VAES (1 << 9)
	63	%define FLAG_CPUID7_ECX_VPCLMULQDQ (1 << 10)
	64	%define FLAG_CPUID7_ECX_VNNI (1 << 11)
	65	%define FLAG_CPUID7_ECX_BITALG (1 << 12)
	66	%define FLAG_CPUID7_ECX_VPOPCNTDQ (1 << 14)
7c673cae	67
f91f0fd5 TL	68	%define FLAGS_CPUID7_EBX_AVX512_G1 (FLAG_CPUID7_EBX_AVX512F \| FLAG_CPUID7_EBX_AVX512VL \| FLAG_CPUID7_EBX_AVX512BW \| FLAG_CPUID7_EBX_AVX512CD \| FLAG_CPUID7_EBX_AVX512DQ)
f91f0fd5 TL	69	%define FLAGS_CPUID7_ECX_AVX512_G2 (FLAG_CPUID7_ECX_AVX512VBMI2 \| FLAG_CPUID7_ECX_GFNI \| FLAG_CPUID7_ECX_VAES \| FLAG_CPUID7_ECX_VPCLMULQDQ \| FLAG_CPUID7_ECX_VNNI \| FLAG_CPUID7_ECX_BITALG \| FLAG_CPUID7_ECX_VPOPCNTDQ)
7c673cae FG	70
	71	%define FLAG_XGETBV_EAX_XMM (1<<1)
	72	%define FLAG_XGETBV_EAX_YMM (1<<2)
	73	%define FLAG_XGETBV_EAX_XMM_YMM 0x6
	74	%define FLAG_XGETBV_EAX_ZMM_OPM 0xe0
	75
	76	%define FLAG_CPUID1_EAX_AVOTON 0x000406d0
	77	%define FLAG_CPUID1_EAX_STEP_MASK 0xfffffff0
	78
	79	; define d and w variants for registers
	80
	81	%define raxd eax
	82	%define raxw ax
	83	%define raxb al
	84
	85	%define rbxd ebx
	86	%define rbxw bx
	87	%define rbxb bl
	88
	89	%define rcxd ecx
	90	%define rcxw cx
	91	%define rcxb cl
	92
	93	%define rdxd edx
	94	%define rdxw dx
	95	%define rdxb dl
	96
	97	%define rsid esi
	98	%define rsiw si
	99	%define rsib sil
	100
	101	%define rdid edi
	102	%define rdiw di
	103	%define rdib dil
	104
	105	%define rbpd ebp
	106	%define rbpw bp
	107	%define rbpb bpl
	108
	109	%define ymm0x xmm0
	110	%define ymm1x xmm1
	111	%define ymm2x xmm2
	112	%define ymm3x xmm3
	113	%define ymm4x xmm4
	114	%define ymm5x xmm5
	115	%define ymm6x xmm6
	116	%define ymm7x xmm7
	117	%define ymm8x xmm8
	118	%define ymm9x xmm9
	119	%define ymm10x xmm10
	120	%define ymm11x xmm11
	121	%define ymm12x xmm12
	122	%define ymm13x xmm13
	123	%define ymm14x xmm14
	124	%define ymm15x xmm15
	125
f91f0fd5 TL	126	%define zmm0x xmm0
	127	%define zmm1x xmm1
	128	%define zmm2x xmm2
	129	%define zmm3x xmm3
	130	%define zmm4x xmm4
	131	%define zmm5x xmm5
	132	%define zmm6x xmm6
	133	%define zmm7x xmm7
	134	%define zmm8x xmm8
	135	%define zmm9x xmm9
	136	%define zmm10x xmm10
	137	%define zmm11x xmm11
	138	%define zmm12x xmm12
	139	%define zmm13x xmm13
	140	%define zmm14x xmm14
	141	%define zmm15x xmm15
	142	%define zmm16x xmm16
	143	%define zmm17x xmm17
	144	%define zmm18x xmm18
	145	%define zmm19x xmm19
	146	%define zmm20x xmm20
	147	%define zmm21x xmm21
	148	%define zmm22x xmm22
	149	%define zmm23x xmm23
	150	%define zmm24x xmm24
	151	%define zmm25x xmm25
	152	%define zmm26x xmm26
	153	%define zmm27x xmm27
	154	%define zmm28x xmm28
	155	%define zmm29x xmm29
	156	%define zmm30x xmm30
	157	%define zmm31x xmm31
	158
	159	%define zmm0y ymm0
	160	%define zmm1y ymm1
	161	%define zmm2y ymm2
	162	%define zmm3y ymm3
	163	%define zmm4y ymm4
	164	%define zmm5y ymm5
	165	%define zmm6y ymm6
	166	%define zmm7y ymm7
	167	%define zmm8y ymm8
	168	%define zmm9y ymm9
	169	%define zmm10y ymm10
	170	%define zmm11y ymm11
	171	%define zmm12y ymm12
	172	%define zmm13y ymm13
	173	%define zmm14y ymm14
	174	%define zmm15y ymm15
	175	%define zmm16y ymm16
	176	%define zmm17y ymm17
	177	%define zmm18y ymm18
	178	%define zmm19y ymm19
	179	%define zmm20y ymm20
	180	%define zmm21y ymm21
	181	%define zmm22y ymm22
	182	%define zmm23y ymm23
	183	%define zmm24y ymm24
	184	%define zmm25y ymm25
	185	%define zmm26y ymm26
	186	%define zmm27y ymm27
	187	%define zmm28y ymm28
	188	%define zmm29y ymm29
	189	%define zmm30y ymm30
190	%define zmm31y ymm31
191
7c673cae FG	192	%define DWORD(reg) reg %+ d
	193	%define WORD(reg) reg %+ w
	194	%define BYTE(reg) reg %+ b
	195
	196	%define XWORD(reg) reg %+ x
	197
	198	%ifidn __OUTPUT_FORMAT__,elf32
	199	section .note.GNU-stack noalloc noexec nowrite progbits
	200	section .text
	201	%endif
	202	%ifidn __OUTPUT_FORMAT__,elf64
20effc67	203	%define __x86_64__
7c673cae FG	204	section .note.GNU-stack noalloc noexec nowrite progbits
	205	section .text
	206	%endif
20effc67 TL	207	%ifidn __OUTPUT_FORMAT__,win64
	208	%define __x86_64__
	209	%endif
	210	%ifidn __OUTPUT_FORMAT__,macho64
	211	%define __x86_64__
	212	%endif
	213
	214	%ifdef __x86_64__
	215	%define endbranch db 0xf3, 0x0f, 0x1e, 0xfa
	216	%else
	217	%define endbranch db 0xf3, 0x0f, 0x1e, 0xfb
	218	%endif
f91f0fd5 TL	219
	220	%ifdef REL_TEXT
	221	%define WRT_OPT
	222	%elifidn __OUTPUT_FORMAT__, elf64
	223	%define WRT_OPT wrt ..plt
	224	%else
	225	%define WRT_OPT
	226	%endif
	227
20effc67 TL	228	%macro mk_global 1-3
	229	%ifdef __NASM_VER__
	230	%ifidn __OUTPUT_FORMAT__, macho64
	231	global %1
	232	%elifidn __OUTPUT_FORMAT__, win64
	233	global %1
	234	%else
	235	global %1:%2 %3
	236	%endif
	237	%else
	238	global %1:%2 %3
	239	%endif
	240	%endmacro
	241
	242
	243	; Fixes for nasm lack of MS proc helpers
	244	%ifdef __NASM_VER__
	245	%ifidn __OUTPUT_FORMAT__, win64
	246	%macro alloc_stack 1
	247	sub rsp, %1
	248	%endmacro
	249
	250	%macro proc_frame 1
	251	%1:
	252	%endmacro
	253
	254	%macro save_xmm128 2
	255	movdqa [rsp + %2], %1
	256	%endmacro
	257
	258	%macro save_reg 2
	259	mov [rsp + %2], %1
	260	%endmacro
	261
	262	%macro rex_push_reg 1
	263	push %1
	264	%endmacro
	265
	266	%macro push_reg 1
	267	push %1
	268	%endmacro
	269
	270	%define end_prolog
	271	%endif
	272
	273	%define endproc_frame
	274	%endif
	275
7c673cae	276	%ifidn __OUTPUT_FORMAT__, macho64
f91f0fd5 TL	277	%define elf64 macho64
f91f0fd5 TL	278	mac_equ equ 1
7c673cae FG	279	%endif
	280
	281	%macro slversion 4
	282	section .text
	283	global %1_slver_%2%3%4
	284	global %1_slver
	285	%1_slver:
	286	%1_slver_%2%3%4:
	287	dw 0x%4
	288	db 0x%3, 0x%2
	289	%endmacro
	290
	291	%endif ; ifndef _REG_SIZES_ASM_