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1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ; Copyright(c) 2011-2015 Intel Corporation All rights reserved. | |
3 | ; | |
4 | ; Redistribution and use in source and binary forms, with or without | |
5 | ; modification, are permitted provided that the following conditions | |
6 | ; are met: | |
7 | ; * Redistributions of source code must retain the above copyright | |
8 | ; notice, this list of conditions and the following disclaimer. | |
9 | ; * Redistributions in binary form must reproduce the above copyright | |
10 | ; notice, this list of conditions and the following disclaimer in | |
11 | ; the documentation and/or other materials provided with the | |
12 | ; distribution. | |
13 | ; * Neither the name of Intel Corporation nor the names of its | |
14 | ; contributors may be used to endorse or promote products derived | |
15 | ; from this software without specific prior written permission. | |
16 | ; | |
17 | ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
18 | ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
19 | ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
20 | ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
21 | ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
22 | ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
23 | ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
24 | ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
25 | ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
26 | ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
27 | ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
28 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
29 | ||
30 | %ifidn __OUTPUT_FORMAT__, elf64 | |
31 | %define WRT_OPT wrt ..plt | |
32 | %else | |
33 | %define WRT_OPT | |
34 | %endif | |
35 | ||
36 | %include "reg_sizes.asm" | |
37 | %include "multibinary.asm" | |
38 | ||
39 | default rel | |
40 | [bits 64] | |
41 | ||
42 | extern pq_gen_base | |
43 | extern pq_gen_sse | |
44 | extern pq_gen_avx | |
45 | extern pq_gen_avx2 | |
46 | ||
47 | extern xor_gen_base | |
48 | extern xor_gen_sse | |
49 | extern xor_gen_avx | |
50 | ||
51 | extern pq_check_base | |
52 | extern pq_check_sse | |
53 | ||
54 | extern xor_check_base | |
55 | extern xor_check_sse | |
56 | ||
57 | mbin_interface xor_gen | |
58 | mbin_interface pq_gen | |
59 | ||
60 | mbin_dispatch_init5 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx | |
61 | mbin_dispatch_init5 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2 | |
62 | ||
63 | ||
64 | section .data | |
65 | ||
66 | xor_check_dispatched: | |
67 | dq xor_check_mbinit | |
68 | pq_check_dispatched: | |
69 | dq pq_check_mbinit | |
70 | ||
71 | section .text | |
72 | ||
73 | ;;;; | |
74 | ; pq_check multibinary function | |
75 | ;;;; | |
76 | global pq_check:function | |
77 | pq_check_mbinit: | |
78 | call pq_check_dispatch_init | |
79 | pq_check: | |
80 | jmp qword [pq_check_dispatched] | |
81 | ||
82 | pq_check_dispatch_init: | |
83 | push rax | |
84 | push rbx | |
85 | push rcx | |
86 | push rdx | |
87 | push rsi | |
88 | lea rsi, [pq_check_base WRT_OPT] ; Default | |
89 | ||
90 | mov eax, 1 | |
91 | cpuid | |
92 | test ecx, FLAG_CPUID1_ECX_SSE4_1 | |
93 | lea rbx, [pq_check_sse WRT_OPT] | |
94 | cmovne rsi, rbx | |
95 | ||
96 | mov [pq_check_dispatched], rsi | |
97 | pop rsi | |
98 | pop rdx | |
99 | pop rcx | |
100 | pop rbx | |
101 | pop rax | |
102 | ret | |
103 | ||
104 | ||
105 | ;;;; | |
106 | ; xor_check multibinary function | |
107 | ;;;; | |
108 | global xor_check:function | |
109 | xor_check_mbinit: | |
110 | call xor_check_dispatch_init | |
111 | xor_check: | |
112 | jmp qword [xor_check_dispatched] | |
113 | ||
114 | xor_check_dispatch_init: | |
115 | push rax | |
116 | push rbx | |
117 | push rcx | |
118 | push rdx | |
119 | push rsi | |
120 | lea rsi, [xor_check_base WRT_OPT] ; Default | |
121 | ||
122 | mov eax, 1 | |
123 | cpuid | |
124 | test ecx, FLAG_CPUID1_ECX_SSE4_1 | |
125 | lea rbx, [xor_check_sse WRT_OPT] | |
126 | cmovne rsi, rbx | |
127 | ||
128 | mov [xor_check_dispatched], rsi | |
129 | pop rsi | |
130 | pop rdx | |
131 | pop rcx | |
132 | pop rbx | |
133 | pop rax | |
134 | ret | |
135 | ||
136 | ;;; func core, ver, snum | |
137 | slversion xor_gen, 00, 03, 0126 | |
138 | slversion xor_check, 00, 03, 0127 | |
139 | slversion pq_gen, 00, 03, 0128 | |
140 | slversion pq_check, 00, 03, 0129 |