]>
Commit | Line | Data |
---|---|---|
1e59de90 TL |
1 | set(VCPKG_TARGET_ARCHITECTURE arm) |
2 | set(VCPKG_CRT_LINKAGE dynamic) | |
3 | set(VCPKG_LIBRARY_LINKAGE dynamic) | |
4 | set(VCPKG_ENV_PASSTHROUGH PATH) | |
5 | ||
6 | set(VCPKG_CMAKE_SYSTEM_NAME MinGW) | |
7 | set(VCPKG_POLICY_DLLS_WITHOUT_LIBS enabled)\r | |
8 | if(PORT STREQUAL "szip") | |
9 | set(VCPKG_POLICY_SKIP_ARCHITECTURE_CHECK enabled) | |
10 | endif() |