projects / ceph.git / blame
| Commit | Line | Data |
|---|---|---|
| 9f95a23c TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
| 2 | * Copyright (c) 2015-2018 Atomic Rules LLC | |
| 11fdf7f2 TL |
3 | */ |
| 4 | ||
| 5 | #ifndef _ARK_DDM_H_ | |
| 6 | #define _ARK_DDM_H_ | |
| 7 | ||
| 8 | #include <stdint.h> | |
| 9 | ||
| 10 | #include <rte_memory.h> | |
| 11 | ||
| 12 | ||
| 13 | /* The DDM or Downstream Data Mover is an internal Arkville hardware | |
| 14 | * module for moving packet from host memory to the TX packet streams. | |
| 15 | * This module is *not* intended for end-user manipulation, hence | |
| 16 | * there is minimal documentation. | |
| 17 | */ | |
| 18 | ||
| 19 | /* struct defining Tx meta data -- fixed in FPGA -- 16 bytes */ | |
| 20 | struct ark_tx_meta { | |
| 21 | uint64_t physaddr; | |
| 9f95a23c | 22 | uint32_t user1; |
| 11fdf7f2 TL |
23 | uint16_t data_len; /* of this MBUF */ |
| 24 | #define ARK_DDM_EOP 0x01 | |
| 25 | #define ARK_DDM_SOP 0x02 | |
| 26 | uint8_t flags; /* bit 0 indicates last mbuf in chain. */ | |
| 27 | uint8_t reserved[1]; | |
| 28 | }; | |
| 29 | ||
| 30 | ||
| 31 | /* | |
| 32 | * DDM core hardware structures | |
| 33 | * These are overlay structures to a memory mapped FPGA device. These | |
| 34 | * structs will never be instantiated in ram memory | |
| 35 | */ | |
| 36 | #define ARK_DDM_CFG 0x0000 | |
| 9f95a23c TL |
37 | /* Set unique HW ID for hardware version */ |
| 38 | #define ARK_DDM_CONST2 (0x324d4444) | |
| 39 | #define ARK_DDM_CONST1 (0xfacecafe) | |
| 40 | ||
| 11fdf7f2 TL |
41 | struct ark_ddm_cfg_t { |
| 42 | uint32_t r0; | |
| 43 | volatile uint32_t tlp_stats_clear; | |
| 44 | uint32_t const0; | |
| 45 | volatile uint32_t tag_max; | |
| 46 | volatile uint32_t command; | |
| 47 | volatile uint32_t stop_flushed; | |
| 48 | }; | |
| 49 | ||
| 50 | #define ARK_DDM_STATS 0x0020 | |
| 51 | struct ark_ddm_stats_t { | |
| 52 | volatile uint64_t tx_byte_count; | |
| 53 | volatile uint64_t tx_pkt_count; | |
| 54 | volatile uint64_t tx_mbuf_count; | |
| 55 | }; | |
| 56 | ||
| 57 | #define ARK_DDM_MRDQ 0x0040 | |
| 58 | struct ark_ddm_mrdq_t { | |
| 59 | volatile uint32_t mrd_q1; | |
| 60 | volatile uint32_t mrd_q2; | |
| 61 | volatile uint32_t mrd_q3; | |
| 62 | volatile uint32_t mrd_q4; | |
| 63 | volatile uint32_t mrd_full; | |
| 64 | }; | |
| 65 | ||
| 66 | #define ARK_DDM_CPLDQ 0x0068 | |
| 67 | struct ark_ddm_cpldq_t { | |
| 68 | volatile uint32_t cpld_q1; | |
| 69 | volatile uint32_t cpld_q2; | |
| 70 | volatile uint32_t cpld_q3; | |
| 71 | volatile uint32_t cpld_q4; | |
| 72 | volatile uint32_t cpld_full; | |
| 73 | }; | |
| 74 | ||
| 75 | #define ARK_DDM_MRD_PS 0x0090 | |
| 76 | struct ark_ddm_mrd_ps_t { | |
| 77 | volatile uint32_t mrd_ps_min; | |
| 78 | volatile uint32_t mrd_ps_max; | |
| 79 | volatile uint32_t mrd_full_ps_min; | |
| 80 | volatile uint32_t mrd_full_ps_max; | |
| 81 | volatile uint32_t mrd_dw_ps_min; | |
| 82 | volatile uint32_t mrd_dw_ps_max; | |
| 83 | }; | |
| 84 | ||
| 85 | #define ARK_DDM_QUEUE_STATS 0x00a8 | |
| 86 | struct ark_ddm_qstats_t { | |
| 87 | volatile uint64_t byte_count; | |
| 88 | volatile uint64_t pkt_count; | |
| 89 | volatile uint64_t mbuf_count; | |
| 90 | }; | |
| 91 | ||
| 92 | #define ARK_DDM_CPLD_PS 0x00c0 | |
| 93 | struct ark_ddm_cpld_ps_t { | |
| 94 | volatile uint32_t cpld_ps_min; | |
| 95 | volatile uint32_t cpld_ps_max; | |
| 96 | volatile uint32_t cpld_full_ps_min; | |
| 97 | volatile uint32_t cpld_full_ps_max; | |
| 98 | volatile uint32_t cpld_dw_ps_min; | |
| 99 | volatile uint32_t cpld_dw_ps_max; | |
| 100 | }; | |
| 101 | ||
| 102 | #define ARK_DDM_SETUP 0x00e0 | |
| 103 | struct ark_ddm_setup_t { | |
| 9f95a23c | 104 | rte_iova_t cons_write_index_addr; |
| 11fdf7f2 TL |
105 | uint32_t write_index_interval; /* 4ns each */ |
| 106 | volatile uint32_t cons_index; | |
| 107 | }; | |
| 108 | ||
| 109 | #define ARK_DDM_EXPECTED_SIZE 256 | |
| 110 | #define ARK_DDM_QOFFSET ARK_DDM_EXPECTED_SIZE | |
| 111 | /* Consolidated structure */ | |
| 112 | struct ark_ddm_t { | |
| 113 | struct ark_ddm_cfg_t cfg; | |
| 114 | uint8_t reserved0[(ARK_DDM_STATS - ARK_DDM_CFG) - | |
| 115 | sizeof(struct ark_ddm_cfg_t)]; | |
| 116 | struct ark_ddm_stats_t stats; | |
| 117 | uint8_t reserved1[(ARK_DDM_MRDQ - ARK_DDM_STATS) - | |
| 118 | sizeof(struct ark_ddm_stats_t)]; | |
| 119 | struct ark_ddm_mrdq_t mrdq; | |
| 120 | uint8_t reserved2[(ARK_DDM_CPLDQ - ARK_DDM_MRDQ) - | |
| 121 | sizeof(struct ark_ddm_mrdq_t)]; | |
| 122 | struct ark_ddm_cpldq_t cpldq; | |
| 123 | uint8_t reserved3[(ARK_DDM_MRD_PS - ARK_DDM_CPLDQ) - | |
| 124 | sizeof(struct ark_ddm_cpldq_t)]; | |
| 125 | struct ark_ddm_mrd_ps_t mrd_ps; | |
| 126 | struct ark_ddm_qstats_t queue_stats; | |
| 127 | struct ark_ddm_cpld_ps_t cpld_ps; | |
| 128 | uint8_t reserved5[(ARK_DDM_SETUP - ARK_DDM_CPLD_PS) - | |
| 129 | sizeof(struct ark_ddm_cpld_ps_t)]; | |
| 130 | struct ark_ddm_setup_t setup; | |
| 131 | uint8_t reserved_p[(ARK_DDM_EXPECTED_SIZE - ARK_DDM_SETUP) - | |
| 132 | sizeof(struct ark_ddm_setup_t)]; | |
| 133 | }; | |
| 134 | ||
| 135 | ||
| 136 | /* DDM function prototype */ | |
| 137 | int ark_ddm_verify(struct ark_ddm_t *ddm); | |
| 138 | void ark_ddm_start(struct ark_ddm_t *ddm); | |
| 139 | int ark_ddm_stop(struct ark_ddm_t *ddm, const int wait); | |
| 140 | void ark_ddm_reset(struct ark_ddm_t *ddm); | |
| 141 | void ark_ddm_stats_reset(struct ark_ddm_t *ddm); | |
| 9f95a23c | 142 | void ark_ddm_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr, |
| 11fdf7f2 TL |
143 | uint32_t interval); |
| 144 | void ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg); | |
| 145 | void ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg); | |
| 146 | int ark_ddm_is_stopped(struct ark_ddm_t *ddm); | |
| 147 | uint64_t ark_ddm_queue_byte_count(struct ark_ddm_t *ddm); | |
| 148 | uint64_t ark_ddm_queue_pkt_count(struct ark_ddm_t *ddm); | |
| 149 | void ark_ddm_queue_reset_stats(struct ark_ddm_t *ddm); | |
| 150 | ||
| 151 | #endif |