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[ceph.git] / ceph / src / seastar / dpdk / drivers / net / ark / ark_udm.c
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1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2018 Atomic Rules LLC
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3 */
4
5#include <unistd.h>
6
7#include "ark_logs.h"
8#include "ark_udm.h"
9
10int
11ark_udm_verify(struct ark_udm_t *udm)
12{
13 if (sizeof(struct ark_udm_t) != ARK_UDM_EXPECT_SIZE) {
14 PMD_DRV_LOG(ERR,
15 "ARK: UDM structure looks incorrect %d vs %zd\n",
16 ARK_UDM_EXPECT_SIZE, sizeof(struct ark_udm_t));
17 return -1;
18 }
19
20 if (udm->setup.const0 != ARK_UDM_CONST) {
21 PMD_DRV_LOG(ERR,
22 "ARK: UDM module not found as expected 0x%08x\n",
23 udm->setup.const0);
24 return -1;
25 }
26 return 0;
27}
28
29int
30ark_udm_stop(struct ark_udm_t *udm, const int wait)
31{
32 int cnt = 0;
33
34 udm->cfg.command = 2;
35
36 while (wait && (udm->cfg.stop_flushed & 0x01) == 0) {
37 if (cnt++ > 1000)
38 return 1;
39
40 usleep(10);
41 }
42 return 0;
43}
44
45int
46ark_udm_reset(struct ark_udm_t *udm)
47{
48 int status;
49
50 status = ark_udm_stop(udm, 1);
51 if (status != 0) {
52 PMD_DEBUG_LOG(INFO, "%s stop failed doing forced reset\n",
53 __func__);
54 udm->cfg.command = 4;
55 usleep(10);
56 udm->cfg.command = 3;
57 status = ark_udm_stop(udm, 0);
58 PMD_DEBUG_LOG(INFO, "%s stop status %d post failure"
59 " and forced reset\n",
60 __func__, status);
61 } else {
62 udm->cfg.command = 3;
63 }
64
65 return status;
66}
67
68void
69ark_udm_start(struct ark_udm_t *udm)
70{
71 udm->cfg.command = 1;
72}
73
74void
75ark_udm_stats_reset(struct ark_udm_t *udm)
76{
77 udm->pcibp.pci_clear = 1;
78 udm->tlp_ps.tlp_clear = 1;
79}
80
81void
82ark_udm_configure(struct ark_udm_t *udm,
83 uint32_t headroom,
84 uint32_t dataroom,
85 uint32_t write_interval_ns)
86{
87 /* headroom and data room are in DWords in the UDM */
88 udm->cfg.dataroom = dataroom / 4;
89 udm->cfg.headroom = headroom / 4;
90
91 /* 4 NS period ns */
92 udm->rt_cfg.write_interval = write_interval_ns / 4;
93}
94
95void
9f95a23c 96ark_udm_write_addr(struct ark_udm_t *udm, rte_iova_t addr)
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97{
98 udm->rt_cfg.hw_prod_addr = addr;
99}
100
101int
102ark_udm_is_flushed(struct ark_udm_t *udm)
103{
104 return (udm->cfg.stop_flushed & 0x01) != 0;
105}
106
107uint64_t
108ark_udm_dropped(struct ark_udm_t *udm)
109{
110 return udm->qstats.q_pkt_drop;
111}
112
113uint64_t
114ark_udm_bytes(struct ark_udm_t *udm)
115{
116 return udm->qstats.q_byte_count;
117}
118
119uint64_t
120ark_udm_packets(struct ark_udm_t *udm)
121{
122 return udm->qstats.q_ff_packet_count;
123}
124
125void
126ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg)
127{
128 PMD_STATS_LOG(INFO, "UDM Stats: %s"
129 ARK_SU64 ARK_SU64 ARK_SU64 ARK_SU64 ARK_SU64 "\n",
130 msg,
131 "Pkts Received", udm->stats.rx_packet_count,
132 "Pkts Finalized", udm->stats.rx_sent_packets,
133 "Pkts Dropped", udm->tlp.pkt_drop,
134 "Bytes Count", udm->stats.rx_byte_count,
135 "MBuf Count", udm->stats.rx_mbuf_count);
136}
137
138void
139ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg, uint16_t qid)
140{
141 PMD_STATS_LOG(INFO, "UDM Queue %3u Stats: %s"
142 ARK_SU64 ARK_SU64
143 ARK_SU64 ARK_SU64
144 ARK_SU64 "\n",
145 qid, msg,
146 "Pkts Received", udm->qstats.q_packet_count,
147 "Pkts Finalized", udm->qstats.q_ff_packet_count,
148 "Pkts Dropped", udm->qstats.q_pkt_drop,
149 "Bytes Count", udm->qstats.q_byte_count,
150 "MBuf Count", udm->qstats.q_mbuf_count);
151}
152
153void
154ark_udm_dump(struct ark_udm_t *udm, const char *msg)
155{
156 PMD_DEBUG_LOG(DEBUG, "UDM Dump: %s Stopped: %d\n", msg,
157 udm->cfg.stop_flushed);
158}
159
160void
161ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id)
162{
163 PMD_DEBUG_LOG(DEBUG, "UDM Setup Q: %u"
164 ARK_SU64X ARK_SU32 "\n",
165 q_id,
166 "hw_prod_addr", udm->rt_cfg.hw_prod_addr,
167 "prod_idx", udm->rt_cfg.prod_idx);
168}
169
170void
171ark_udm_dump_perf(struct ark_udm_t *udm, const char *msg)
172{
173 struct ark_udm_pcibp_t *bp = &udm->pcibp;
174
175 PMD_STATS_LOG(INFO, "UDM Performance %s"
176 ARK_SU32 ARK_SU32 ARK_SU32 ARK_SU32 ARK_SU32 ARK_SU32
177 "\n",
178 msg,
179 "PCI Empty", bp->pci_empty,
180 "PCI Q1", bp->pci_q1,
181 "PCI Q2", bp->pci_q2,
182 "PCI Q3", bp->pci_q3,
183 "PCI Q4", bp->pci_q4,
184 "PCI Full", bp->pci_full);
185}
186
187void
188ark_udm_queue_stats_reset(struct ark_udm_t *udm)
189{
190 udm->qstats.q_byte_count = 1;
191}
192
193void
194ark_udm_queue_enable(struct ark_udm_t *udm, int enable)
195{
196 udm->qstats.q_enable = enable ? 1 : 0;
197}