[ceph.git] / ceph / src / seastar / dpdk / drivers / net / ark / ark_udm.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright (c) 2015-2018 Atomic Rules LLC
 */

#ifndef _ARK_UDM_H_
#define _ARK_UDM_H_

#include <stdint.h>

#include <rte_memory.h>

/* The UDM or Upstream Data Mover is an internal Arkville hardware
 * module for moving packet from the RX packet streams to host memory.
 * This module is *not* intended for end-user manipulation, hence
 * there is minimal documentation.
 */

/* Meta data structure apssed from FPGA, must match layout in FPGA */
struct ark_rx_meta {
	uint64_t timestamp;
	uint64_t user_data;
	uint8_t port;
	uint8_t dst_queue;
	uint16_t pkt_len;
};

/*
 * UDM hardware structures
 * These are overlay structures to a memory mapped FPGA device.  These
 * structs will never be instantiated in ram memory
 */

#define ARK_RX_WRITE_TIME_NS 2500
#define ARK_UDM_SETUP 0
#define ARK_UDM_CONST 0xbACECACE
struct ark_udm_setup_t {
	uint32_t r0;
	uint32_t r4;
	volatile uint32_t cycle_count;
	uint32_t const0;
};

#define ARK_UDM_CFG 0x010
struct ark_udm_cfg_t {
	volatile uint32_t stop_flushed;	/* RO */
	volatile uint32_t command;
	uint32_t dataroom;
	uint32_t headroom;
};

typedef enum {
	ARK_UDM_START = 0x1,
	ARK_UDM_STOP = 0x2,
	ARK_UDM_RESET = 0x3
} ark_udm_commands;

#define ARK_UDM_STATS 0x020
struct ark_udm_stats_t {
	volatile uint64_t rx_byte_count;
	volatile uint64_t rx_packet_count;
	volatile uint64_t rx_mbuf_count;
	volatile uint64_t rx_sent_packets;
};

#define ARK_UDM_PQ 0x040
struct ark_udm_queue_stats_t {
	volatile uint64_t q_byte_count;
	volatile uint64_t q_packet_count;	/* includes drops */
	volatile uint64_t q_mbuf_count;
	volatile uint64_t q_ff_packet_count;
	volatile uint64_t q_pkt_drop;
	uint32_t q_enable;
};

#define ARK_UDM_TLP 0x0070
struct ark_udm_tlp_t {
	volatile uint64_t pkt_drop;	/* global */
	volatile uint32_t tlp_q1;
	volatile uint32_t tlp_q2;
	volatile uint32_t tlp_q3;
	volatile uint32_t tlp_q4;
	volatile uint32_t tlp_full;
};

#define ARK_UDM_PCIBP 0x00a0
struct ark_udm_pcibp_t {
	volatile uint32_t pci_clear;
	volatile uint32_t pci_empty;
	volatile uint32_t pci_q1;
	volatile uint32_t pci_q2;
	volatile uint32_t pci_q3;
	volatile uint32_t pci_q4;
	volatile uint32_t pci_full;
};

#define ARK_UDM_TLP_PS 0x00bc
struct ark_udm_tlp_ps_t {
	volatile uint32_t tlp_clear;
	volatile uint32_t tlp_ps_min;
	volatile uint32_t tlp_ps_max;
	volatile uint32_t tlp_full_ps_min;
	volatile uint32_t tlp_full_ps_max;
	volatile uint32_t tlp_dw_ps_min;
	volatile uint32_t tlp_dw_ps_max;
	volatile uint32_t tlp_pldw_ps_min;
	volatile uint32_t tlp_pldw_ps_max;
};

#define ARK_UDM_RT_CFG 0x00e0
struct ark_udm_rt_cfg_t {
	rte_iova_t hw_prod_addr;
	uint32_t write_interval;	/* 4ns cycles */
	volatile uint32_t prod_idx;	/* RO */
};

/*  Consolidated structure */
#define ARK_UDM_EXPECT_SIZE (0x00fc + 4)
#define ARK_UDM_QOFFSET ARK_UDM_EXPECT_SIZE
struct ark_udm_t {
	struct ark_udm_setup_t setup;
	struct ark_udm_cfg_t cfg;
	struct ark_udm_stats_t stats;
	struct ark_udm_queue_stats_t qstats;
	uint8_t reserved1[(ARK_UDM_TLP - ARK_UDM_PQ) -
			  sizeof(struct ark_udm_queue_stats_t)];
	struct ark_udm_tlp_t tlp;
	uint8_t reserved2[(ARK_UDM_PCIBP - ARK_UDM_TLP) -
			  sizeof(struct ark_udm_tlp_t)];
	struct ark_udm_pcibp_t pcibp;
	struct ark_udm_tlp_ps_t tlp_ps;
	struct ark_udm_rt_cfg_t rt_cfg;
	int8_t reserved3[(ARK_UDM_EXPECT_SIZE - ARK_UDM_RT_CFG) -
			 sizeof(struct ark_udm_rt_cfg_t)];
};


int ark_udm_verify(struct ark_udm_t *udm);
int ark_udm_stop(struct ark_udm_t *udm, int wait);
void ark_udm_start(struct ark_udm_t *udm);
int ark_udm_reset(struct ark_udm_t *udm);
void ark_udm_configure(struct ark_udm_t *udm,
		       uint32_t headroom,
		       uint32_t dataroom,
		       uint32_t write_interval_ns);
void ark_udm_write_addr(struct ark_udm_t *udm, rte_iova_t addr);
void ark_udm_stats_reset(struct ark_udm_t *udm);
void ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg);
void ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg,
			      uint16_t qid);
void ark_udm_dump(struct ark_udm_t *udm, const char *msg);
void ark_udm_dump_perf(struct ark_udm_t *udm, const char *msg);
void ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id);
int ark_udm_is_flushed(struct ark_udm_t *udm);

/* Per queue data */
uint64_t ark_udm_dropped(struct ark_udm_t *udm);
uint64_t ark_udm_bytes(struct ark_udm_t *udm);
uint64_t ark_udm_packets(struct ark_udm_t *udm);

void ark_udm_queue_stats_reset(struct ark_udm_t *udm);
void ark_udm_queue_enable(struct ark_udm_t *udm, int enable);

#endif
Commit	Line	Data
9f95a23c TL	1	/* SPDX-License-Identifier: BSD-3-Clause
9f95a23c TL	2	* Copyright (c) 2015-2018 Atomic Rules LLC
11fdf7f2 TL	3	*/
	4
	5	#ifndef _ARK_UDM_H_
	6	#define _ARK_UDM_H_
	7
	8	#include <stdint.h>
	9
	10	#include <rte_memory.h>
	11
	12	/* The UDM or Upstream Data Mover is an internal Arkville hardware
	13	* module for moving packet from the RX packet streams to host memory.
	14	* This module is not intended for end-user manipulation, hence
	15	* there is minimal documentation.
	16	*/
	17
	18	/* Meta data structure apssed from FPGA, must match layout in FPGA */
	19	struct ark_rx_meta {
	20	uint64_t timestamp;
	21	uint64_t user_data;
	22	uint8_t port;
	23	uint8_t dst_queue;
	24	uint16_t pkt_len;
	25	};
	26
	27	/*
	28	* UDM hardware structures
	29	* These are overlay structures to a memory mapped FPGA device. These
	30	* structs will never be instantiated in ram memory
	31	*/
	32
	33	#define ARK_RX_WRITE_TIME_NS 2500
	34	#define ARK_UDM_SETUP 0
	35	#define ARK_UDM_CONST 0xbACECACE
	36	struct ark_udm_setup_t {
	37	uint32_t r0;
	38	uint32_t r4;
	39	volatile uint32_t cycle_count;
	40	uint32_t const0;
	41	};
	42
	43	#define ARK_UDM_CFG 0x010
	44	struct ark_udm_cfg_t {
	45	volatile uint32_t stop_flushed; /* RO */
	46	volatile uint32_t command;
	47	uint32_t dataroom;
	48	uint32_t headroom;
	49	};
	50
	51	typedef enum {
	52	ARK_UDM_START = 0x1,
	53	ARK_UDM_STOP = 0x2,
	54	ARK_UDM_RESET = 0x3
	55	} ark_udm_commands;
	56
	57	#define ARK_UDM_STATS 0x020
	58	struct ark_udm_stats_t {
	59	volatile uint64_t rx_byte_count;
	60	volatile uint64_t rx_packet_count;
	61	volatile uint64_t rx_mbuf_count;
	62	volatile uint64_t rx_sent_packets;
	63	};
	64
	65	#define ARK_UDM_PQ 0x040
	66	struct ark_udm_queue_stats_t {
67	volatile uint64_t q_byte_count;
68	volatile uint64_t q_packet_count; /* includes drops */
69	volatile uint64_t q_mbuf_count;
70	volatile uint64_t q_ff_packet_count;
71	volatile uint64_t q_pkt_drop;
72	uint32_t q_enable;
73	};
74
75	#define ARK_UDM_TLP 0x0070
76	struct ark_udm_tlp_t {
77	volatile uint64_t pkt_drop; /* global */
78	volatile uint32_t tlp_q1;
79	volatile uint32_t tlp_q2;
80	volatile uint32_t tlp_q3;
81	volatile uint32_t tlp_q4;
82	volatile uint32_t tlp_full;
83	};
84
85	#define ARK_UDM_PCIBP 0x00a0
86	struct ark_udm_pcibp_t {
87	volatile uint32_t pci_clear;
88	volatile uint32_t pci_empty;
89	volatile uint32_t pci_q1;
90	volatile uint32_t pci_q2;
91	volatile uint32_t pci_q3;
92	volatile uint32_t pci_q4;
93	volatile uint32_t pci_full;
94	};
95
96	#define ARK_UDM_TLP_PS 0x00bc
97	struct ark_udm_tlp_ps_t {
98	volatile uint32_t tlp_clear;
99	volatile uint32_t tlp_ps_min;
100	volatile uint32_t tlp_ps_max;
101	volatile uint32_t tlp_full_ps_min;
102	volatile uint32_t tlp_full_ps_max;
103	volatile uint32_t tlp_dw_ps_min;
104	volatile uint32_t tlp_dw_ps_max;
105	volatile uint32_t tlp_pldw_ps_min;
106	volatile uint32_t tlp_pldw_ps_max;
107	};
108
109	#define ARK_UDM_RT_CFG 0x00e0
110	struct ark_udm_rt_cfg_t {
9f95a23c	111	rte_iova_t hw_prod_addr;
11fdf7f2 TL	112	uint32_t write_interval; /* 4ns cycles */
	113	volatile uint32_t prod_idx; /* RO */
	114	};
	115
	116	/* Consolidated structure */
	117	#define ARK_UDM_EXPECT_SIZE (0x00fc + 4)
	118	#define ARK_UDM_QOFFSET ARK_UDM_EXPECT_SIZE
	119	struct ark_udm_t {
	120	struct ark_udm_setup_t setup;
	121	struct ark_udm_cfg_t cfg;
	122	struct ark_udm_stats_t stats;
	123	struct ark_udm_queue_stats_t qstats;
	124	uint8_t reserved1[(ARK_UDM_TLP - ARK_UDM_PQ) -
	125	sizeof(struct ark_udm_queue_stats_t)];
	126	struct ark_udm_tlp_t tlp;
	127	uint8_t reserved2[(ARK_UDM_PCIBP - ARK_UDM_TLP) -
	128	sizeof(struct ark_udm_tlp_t)];
	129	struct ark_udm_pcibp_t pcibp;
	130	struct ark_udm_tlp_ps_t tlp_ps;
	131	struct ark_udm_rt_cfg_t rt_cfg;
	132	int8_t reserved3[(ARK_UDM_EXPECT_SIZE - ARK_UDM_RT_CFG) -
	133	sizeof(struct ark_udm_rt_cfg_t)];
	134	};
	135
	136
	137	int ark_udm_verify(struct ark_udm_t *udm);
	138	int ark_udm_stop(struct ark_udm_t *udm, int wait);
	139	void ark_udm_start(struct ark_udm_t *udm);
	140	int ark_udm_reset(struct ark_udm_t *udm);
	141	void ark_udm_configure(struct ark_udm_t *udm,
	142	uint32_t headroom,
	143	uint32_t dataroom,
	144	uint32_t write_interval_ns);
9f95a23c	145	void ark_udm_write_addr(struct ark_udm_t *udm, rte_iova_t addr);
11fdf7f2 TL	146	void ark_udm_stats_reset(struct ark_udm_t *udm);
	147	void ark_udm_dump_stats(struct ark_udm_t udm, const char msg);
	148	void ark_udm_dump_queue_stats(struct ark_udm_t udm, const char msg,
	149	uint16_t qid);
	150	void ark_udm_dump(struct ark_udm_t udm, const char msg);
	151	void ark_udm_dump_perf(struct ark_udm_t udm, const char msg);
	152	void ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id);
	153	int ark_udm_is_flushed(struct ark_udm_t *udm);
	154
	155	/* Per queue data */
	156	uint64_t ark_udm_dropped(struct ark_udm_t *udm);
	157	uint64_t ark_udm_bytes(struct ark_udm_t *udm);
	158	uint64_t ark_udm_packets(struct ark_udm_t *udm);
	159
	160	void ark_udm_queue_stats_reset(struct ark_udm_t *udm);
	161	void ark_udm_queue_enable(struct ark_udm_t *udm, int enable);
	162
	163	#endif