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[ceph.git] / ceph / src / seastar / dpdk / drivers / net / bnxt / bnxt_ethdev.c
CommitLineData
9f95a23c
TL		 1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
3 * All rights reserved.
7c673cae
FG		 4 */
5
6#include <inttypes.h>
7#include <stdbool.h>
8
9#include <rte_dev.h>
9f95a23c 10#include <rte_ethdev_driver.h>
11fdf7f2 11#include <rte_ethdev_pci.h>
7c673cae
FG		 12#include <rte_malloc.h>
13#include <rte_cycles.h>
14
15#include "bnxt.h"
16#include "bnxt_cpr.h"
17#include "bnxt_filter.h"
18#include "bnxt_hwrm.h"
19#include "bnxt_irq.h"
20#include "bnxt_ring.h"
21#include "bnxt_rxq.h"
22#include "bnxt_rxr.h"
23#include "bnxt_stats.h"
24#include "bnxt_txq.h"
25#include "bnxt_txr.h"
26#include "bnxt_vnic.h"
27#include "hsi_struct_def_dpdk.h"
9f95a23c
TL		 28#include "bnxt_nvm_defs.h"
29#include "bnxt_util.h"
7c673cae
FG		 30
31#define DRV_MODULE_NAME "bnxt"
32static const char bnxt_version[] =
9f95a23c
TL		 33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34int bnxt_logtype_driver;
7c673cae
FG		 35
36#define PCI_VENDOR_ID_BROADCOM 0x14E4
37
9f95a23c
TL		 38#define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39#define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
11fdf7f2
TL		 40#define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41#define BROADCOM_DEV_ID_57414_VF 0x16c1
7c673cae
FG		 42#define BROADCOM_DEV_ID_57301 0x16c8
43#define BROADCOM_DEV_ID_57302 0x16c9
44#define BROADCOM_DEV_ID_57304_PF 0x16ca
45#define BROADCOM_DEV_ID_57304_VF 0x16cb
11fdf7f2 46#define BROADCOM_DEV_ID_57417_MF 0x16cc
7c673cae 47#define BROADCOM_DEV_ID_NS2 0x16cd
11fdf7f2
TL		 48#define BROADCOM_DEV_ID_57311 0x16ce
49#define BROADCOM_DEV_ID_57312 0x16cf
7c673cae
FG		 50#define BROADCOM_DEV_ID_57402 0x16d0
51#define BROADCOM_DEV_ID_57404 0x16d1
52#define BROADCOM_DEV_ID_57406_PF 0x16d2
53#define BROADCOM_DEV_ID_57406_VF 0x16d3
54#define BROADCOM_DEV_ID_57402_MF 0x16d4
55#define BROADCOM_DEV_ID_57407_RJ45 0x16d5
11fdf7f2
TL		 56#define BROADCOM_DEV_ID_57412 0x16d6
57#define BROADCOM_DEV_ID_57414 0x16d7
58#define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59#define BROADCOM_DEV_ID_57417_RJ45 0x16d9
7c673cae 60#define BROADCOM_DEV_ID_5741X_VF 0x16dc
11fdf7f2
TL		 61#define BROADCOM_DEV_ID_57412_MF 0x16de
62#define BROADCOM_DEV_ID_57314 0x16df
63#define BROADCOM_DEV_ID_57317_RJ45 0x16e0
7c673cae 64#define BROADCOM_DEV_ID_5731X_VF 0x16e1
11fdf7f2
TL		 65#define BROADCOM_DEV_ID_57417_SFP 0x16e2
66#define BROADCOM_DEV_ID_57416_SFP 0x16e3
67#define BROADCOM_DEV_ID_57317_SFP 0x16e4
7c673cae
FG		 68#define BROADCOM_DEV_ID_57404_MF 0x16e7
69#define BROADCOM_DEV_ID_57406_MF 0x16e8
70#define BROADCOM_DEV_ID_57407_SFP 0x16e9
71#define BROADCOM_DEV_ID_57407_MF 0x16ea
11fdf7f2
TL		 72#define BROADCOM_DEV_ID_57414_MF 0x16ec
73#define BROADCOM_DEV_ID_57416_MF 0x16ee
9f95a23c
TL		 74#define BROADCOM_DEV_ID_58802 0xd802
75#define BROADCOM_DEV_ID_58804 0xd804
76#define BROADCOM_DEV_ID_58808 0x16f0
77#define BROADCOM_DEV_ID_58802_VF 0xd800
7c673cae 78
11fdf7f2 79static const struct rte_pci_id bnxt_pci_id_map[] = {
9f95a23c
TL		 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
11fdf7f2
TL		 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
7c673cae
FG		 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
11fdf7f2
TL		 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
9f95a23c
TL		 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
7c673cae
FG		 122 { .vendor_id = 0, /* sentinel */ },
123};
124
125#define BNXT_ETH_RSS_SUPPORT ( \
126 ETH_RSS_IPV4 | \
127 ETH_RSS_NONFRAG_IPV4_TCP | \
128 ETH_RSS_NONFRAG_IPV4_UDP | \
129 ETH_RSS_IPV6 | \
130 ETH_RSS_NONFRAG_IPV6_TCP | \
131 ETH_RSS_NONFRAG_IPV6_UDP)
132
9f95a23c
TL		 133#define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
134 DEV_TX_OFFLOAD_IPV4_CKSUM | \
135 DEV_TX_OFFLOAD_TCP_CKSUM | \
136 DEV_TX_OFFLOAD_UDP_CKSUM | \
137 DEV_TX_OFFLOAD_TCP_TSO | \
138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
143 DEV_TX_OFFLOAD_MULTI_SEGS)
144
145#define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
146 DEV_RX_OFFLOAD_VLAN_STRIP | \
147 DEV_RX_OFFLOAD_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_UDP_CKSUM | \
149 DEV_RX_OFFLOAD_TCP_CKSUM | \
150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
151 DEV_RX_OFFLOAD_JUMBO_FRAME | \
152 DEV_RX_OFFLOAD_KEEP_CRC | \
153 DEV_RX_OFFLOAD_TCP_LRO)
154
155static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
156static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
157static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
158static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
159
7c673cae
FG		 160/***********************/
161
162/*
163 * High level utility functions
164 */
165
166static void bnxt_free_mem(struct bnxt *bp)
167{
168 bnxt_free_filter_mem(bp);
169 bnxt_free_vnic_attributes(bp);
170 bnxt_free_vnic_mem(bp);
171
172 bnxt_free_stats(bp);
173 bnxt_free_tx_rings(bp);
174 bnxt_free_rx_rings(bp);
7c673cae
FG		 175}
176
177static int bnxt_alloc_mem(struct bnxt *bp)
178{
179 int rc;
180
7c673cae
FG		 181 rc = bnxt_alloc_vnic_mem(bp);
182 if (rc)
183 goto alloc_mem_err;
184
185 rc = bnxt_alloc_vnic_attributes(bp);
186 if (rc)
187 goto alloc_mem_err;
188
189 rc = bnxt_alloc_filter_mem(bp);
190 if (rc)
191 goto alloc_mem_err;
192
193 return 0;
194
195alloc_mem_err:
196 bnxt_free_mem(bp);
197 return rc;
198}
199
200static int bnxt_init_chip(struct bnxt *bp)
201{
9f95a23c 202 struct bnxt_rx_queue *rxq;
7c673cae 203 struct rte_eth_link new;
9f95a23c
TL		 204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
205 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
207 uint64_t rx_offloads = dev_conf->rxmode.offloads;
208 uint32_t intr_vector = 0;
209 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
210 uint32_t vec = BNXT_MISC_VEC_ID;
211 unsigned int i, j;
7c673cae
FG		 212 int rc;
213
9f95a23c
TL		 214 /* disable uio/vfio intr/eventfd mapping */
215 rte_intr_disable(intr_handle);
216
217 if (bp->eth_dev->data->mtu > ETHER_MTU) {
218 bp->eth_dev->data->dev_conf.rxmode.offloads |=
219 DEV_RX_OFFLOAD_JUMBO_FRAME;
220 bp->flags |= BNXT_FLAG_JUMBO;
221 } else {
222 bp->eth_dev->data->dev_conf.rxmode.offloads &=
223 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
224 bp->flags &= ~BNXT_FLAG_JUMBO;
225 }
226
7c673cae
FG		 227 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
228 if (rc) {
9f95a23c 229 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
7c673cae
FG		 230 goto err_out;
231 }
232
233 rc = bnxt_alloc_hwrm_rings(bp);
234 if (rc) {
9f95a23c 235 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
7c673cae
FG		 236 goto err_out;
237 }
238
239 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
240 if (rc) {
9f95a23c 241 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
7c673cae
FG		 242 goto err_out;
243 }
244
245 rc = bnxt_mq_rx_configure(bp);
246 if (rc) {
9f95a23c 247 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
7c673cae
FG		 248 goto err_out;
249 }
250
251 /* VNIC configuration */
252 for (i = 0; i < bp->nr_vnics; i++) {
9f95a23c 253 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
7c673cae 254 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
9f95a23c
TL		 255 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
256
257 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
258 if (!vnic->fw_grp_ids) {
259 PMD_DRV_LOG(ERR,
260 "Failed to alloc %d bytes for group ids\n",
261 size);
262 rc = -ENOMEM;
263 goto err_out;
264 }
265 memset(vnic->fw_grp_ids, -1, size);
266
267 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
268 i, vnic, vnic->fw_grp_ids);
7c673cae
FG		 269
270 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
271 if (rc) {
9f95a23c
TL		 272 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
273 i, rc);
7c673cae
FG		 274 goto err_out;
275 }
276
9f95a23c
TL		 277 /* Alloc RSS context only if RSS mode is enabled */
278 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
279 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
280 if (rc) {
281 PMD_DRV_LOG(ERR,
282 "HWRM vnic %d ctx alloc failure rc: %x\n",
283 i, rc);
284 goto err_out;
285 }
7c673cae
FG		 286 }
287
9f95a23c
TL		 288 /*
289 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
290 * setting is not available at this time, it will not be
291 * configured correctly in the CFA.
292 */
293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
294 vnic->vlan_strip = true;
295 else
296 vnic->vlan_strip = false;
297
7c673cae
FG		 298 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
299 if (rc) {
9f95a23c
TL		 300 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
301 i, rc);
7c673cae
FG		 302 goto err_out;
303 }
304
305 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
306 if (rc) {
9f95a23c
TL		 307 PMD_DRV_LOG(ERR,
308 "HWRM vnic %d filter failure rc: %x\n",
309 i, rc);
7c673cae
FG		 310 goto err_out;
311 }
9f95a23c
TL		 312
313 for (j = 0; j < bp->rx_nr_rings; j++) {
314 rxq = bp->eth_dev->data->rx_queues[j];
315
316 PMD_DRV_LOG(DEBUG,
317 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
318 j, rxq->vnic, rxq->vnic->fw_grp_ids);
319
320 if (rxq->rx_deferred_start)
321 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
322 }
323
324 rc = bnxt_vnic_rss_configure(bp, vnic);
325 if (rc) {
326 PMD_DRV_LOG(ERR,
327 "HWRM vnic set RSS failure rc: %x\n", rc);
328 goto err_out;
7c673cae 329 }
9f95a23c
TL		 330
331 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
332
333 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
334 DEV_RX_OFFLOAD_TCP_LRO)
335 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
336 else
337 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
7c673cae 338 }
9f95a23c 339 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
7c673cae 340 if (rc) {
9f95a23c 341 PMD_DRV_LOG(ERR,
7c673cae
FG		 342 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
343 goto err_out;
344 }
345
9f95a23c
TL		 346 /* check and configure queue intr-vector mapping */
347 if ((rte_intr_cap_multiple(intr_handle) ||
348 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
349 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
350 intr_vector = bp->eth_dev->data->nb_rx_queues;
351 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
352 if (intr_vector > bp->rx_cp_nr_rings) {
353 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
354 bp->rx_cp_nr_rings);
355 return -ENOTSUP;
356 }
357 if (rte_intr_efd_enable(intr_handle, intr_vector))
358 return -1;
359 }
360
361 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
362 intr_handle->intr_vec =
363 rte_zmalloc("intr_vec",
364 bp->eth_dev->data->nb_rx_queues *
365 sizeof(int), 0);
366 if (intr_handle->intr_vec == NULL) {
367 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
368 " intr_vec", bp->eth_dev->data->nb_rx_queues);
369 return -ENOMEM;
370 }
371 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
372 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
373 intr_handle->intr_vec, intr_handle->nb_efd,
374 intr_handle->max_intr);
375 }
376
377 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
378 queue_id++) {
379 intr_handle->intr_vec[queue_id] = vec;
380 if (vec < base + intr_handle->nb_efd - 1)
381 vec++;
382 }
383
384 /* enable uio/vfio intr/eventfd mapping */
385 rte_intr_enable(intr_handle);
386
7c673cae
FG		 387 rc = bnxt_get_hwrm_link_config(bp, &new);
388 if (rc) {
9f95a23c 389 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
7c673cae
FG		 390 goto err_out;
391 }
392
393 if (!bp->link_info.link_up) {
394 rc = bnxt_set_hwrm_link_config(bp, true);
395 if (rc) {
9f95a23c 396 PMD_DRV_LOG(ERR,
7c673cae
FG		 397 "HWRM link config failure rc: %x\n", rc);
398 goto err_out;
399 }
400 }
9f95a23c 401 bnxt_print_link_info(bp->eth_dev);
7c673cae
FG		 402
403 return 0;
404
405err_out:
406 bnxt_free_all_hwrm_resources(bp);
407
9f95a23c
TL		 408 /* Some of the error status returned by FW may not be from errno.h */
409 if (rc > 0)
410 rc = -EIO;
411
7c673cae
FG		 412 return rc;
413}
414
415static int bnxt_shutdown_nic(struct bnxt *bp)
416{
417 bnxt_free_all_hwrm_resources(bp);
418 bnxt_free_all_filters(bp);
419 bnxt_free_all_vnics(bp);
420 return 0;
421}
422
423static int bnxt_init_nic(struct bnxt *bp)
424{
425 int rc;
426
9f95a23c 427 rc = bnxt_init_ring_grps(bp);
7c673cae
FG		 428 if (rc)
429 return rc;
430
9f95a23c
TL		 431 bnxt_init_vnics(bp);
432 bnxt_init_filters(bp);
433
7c673cae
FG		 434 return 0;
435}
436
437/*
438 * Device configuration and status function
439 */
440
441static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
442 struct rte_eth_dev_info *dev_info)
443{
444 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
445 uint16_t max_vnics, i, j, vpool, vrxq;
9f95a23c 446 unsigned int max_rx_rings;
11fdf7f2 447
7c673cae 448 /* MAC Specifics */
9f95a23c 449 dev_info->max_mac_addrs = bp->max_l2_ctx;
7c673cae
FG		 450 dev_info->max_hash_mac_addrs = 0;
451
452 /* PF/VF specifics */
9f95a23c
TL		 453 if (BNXT_PF(bp))
454 dev_info->max_vfs = bp->pdev->max_vfs;
455 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
456 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
457 dev_info->max_rx_queues = max_rx_rings;
458 dev_info->max_tx_queues = max_rx_rings;
459 dev_info->reta_size = HW_HASH_INDEX_SIZE;
460 dev_info->hash_key_size = 40;
461 max_vnics = bp->max_vnics;
7c673cae
FG		 462
463 /* Fast path specifics */
464 dev_info->min_rx_bufsize = 1;
465 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
9f95a23c
TL		 466 + VLAN_TAG_SIZE * 2;
467
468 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
469 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
470 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
471 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
472 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
7c673cae
FG		 473
474 /* *INDENT-OFF* */
475 dev_info->default_rxconf = (struct rte_eth_rxconf) {
476 .rx_thresh = {
477 .pthresh = 8,
478 .hthresh = 8,
479 .wthresh = 0,
480 },
481 .rx_free_thresh = 32,
9f95a23c
TL		 482 /* If no descriptors available, pkts are dropped by default */
483 .rx_drop_en = 1,
7c673cae
FG		 484 };
485
486 dev_info->default_txconf = (struct rte_eth_txconf) {
487 .tx_thresh = {
488 .pthresh = 32,
489 .hthresh = 0,
490 .wthresh = 0,
491 },
492 .tx_free_thresh = 32,
493 .tx_rs_thresh = 32,
7c673cae
FG		 494 };
495 eth_dev->data->dev_conf.intr_conf.lsc = 1;
496
9f95a23c
TL		 497 eth_dev->data->dev_conf.intr_conf.rxq = 1;
498 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
499 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
500 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
501 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
502
7c673cae
FG		 503 /* *INDENT-ON* */
504
505 /*
506 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
507 * need further investigation.
508 */
509
510 /* VMDq resources */
511 vpool = 64; /* ETH_64_POOLS */
512 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
513 for (i = 0; i < 4; vpool >>= 1, i++) {
514 if (max_vnics > vpool) {
515 for (j = 0; j < 5; vrxq >>= 1, j++) {
516 if (dev_info->max_rx_queues > vrxq) {
517 if (vpool > vrxq)
518 vpool = vrxq;
519 goto found;
520 }
521 }
522 /* Not enough resources to support VMDq */
523 break;
524 }
525 }
526 /* Not enough resources to support VMDq */
527 vpool = 0;
528 vrxq = 0;
529found:
530 dev_info->max_vmdq_pools = vpool;
531 dev_info->vmdq_queue_num = vrxq;
532
533 dev_info->vmdq_pool_base = 0;
534 dev_info->vmdq_queue_base = 0;
535}
536
537/* Configure the device based on the configuration provided */
538static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
539{
540 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
9f95a23c
TL		 541 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
542 int rc;
7c673cae
FG		 543
544 bp->rx_queues = (void *)eth_dev->data->rx_queues;
545 bp->tx_queues = (void *)eth_dev->data->tx_queues;
9f95a23c
TL		 546 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
547 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
548
549 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
550 rc = bnxt_hwrm_check_vf_rings(bp);
551 if (rc) {
552 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
553 return -ENOSPC;
554 }
555
556 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
557 if (rc) {
558 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
559 return -ENOSPC;
560 }
561 } else {
562 /* legacy driver needs to get updated values */
563 rc = bnxt_hwrm_func_qcaps(bp);
564 if (rc) {
565 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
566 return rc;
567 }
568 }
7c673cae
FG		 569
570 /* Inherit new configurations */
9f95a23c
TL		 571 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
572 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
573 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
574 bp->max_cp_rings ||
575 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
576 bp->max_stat_ctx ||
577 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps ||
578 (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
579 bp->max_vnics < eth_dev->data->nb_rx_queues)) {
580 PMD_DRV_LOG(ERR,
581 "Insufficient resources to support requested config\n");
582 PMD_DRV_LOG(ERR,
583 "Num Queues Requested: Tx %d, Rx %d\n",
584 eth_dev->data->nb_tx_queues,
585 eth_dev->data->nb_rx_queues);
586 PMD_DRV_LOG(ERR,
587 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
588 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
589 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
590 return -ENOSPC;
591 }
592
7c673cae
FG		 593 bp->rx_cp_nr_rings = bp->rx_nr_rings;
594 bp->tx_cp_nr_rings = bp->tx_nr_rings;
595
9f95a23c 596 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
7c673cae
FG		 597 eth_dev->data->mtu =
598 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
9f95a23c
TL		 599 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
600 BNXT_NUM_VLANS;
601 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
602 }
7c673cae
FG		 603 return 0;
604}
605
606static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
607{
608 struct rte_eth_link *link = &eth_dev->data->dev_link;
609
610 if (link->link_status)
9f95a23c
TL		 611 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
612 eth_dev->data->port_id,
7c673cae
FG		 613 (uint32_t)link->link_speed,
614 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
615 ("full-duplex") : ("half-duplex\n"));
616 else
9f95a23c
TL		 617 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
618 eth_dev->data->port_id);
7c673cae
FG		 619}
620
621static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
622{
623 bnxt_print_link_info(eth_dev);
624 return 0;
625}
626
627static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
628{
629 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
9f95a23c
TL		 630 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
631 int vlan_mask = 0;
7c673cae
FG		 632 int rc;
633
9f95a23c
TL		 634 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
635 PMD_DRV_LOG(ERR,
636 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
637 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
7c673cae 638 }
9f95a23c 639 bp->dev_stopped = 0;
7c673cae 640
9f95a23c 641 rc = bnxt_init_chip(bp);
7c673cae
FG		 642 if (rc)
643 goto error;
644
9f95a23c 645 bnxt_link_update_op(eth_dev, 1);
7c673cae 646
9f95a23c
TL		 647 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
648 vlan_mask |= ETH_VLAN_FILTER_MASK;
649 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
650 vlan_mask |= ETH_VLAN_STRIP_MASK;
651 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
7c673cae
FG		 652 if (rc)
653 goto error;
654
9f95a23c 655 bp->flags |= BNXT_FLAG_INIT_DONE;
7c673cae
FG		 656 return 0;
657
658error:
659 bnxt_shutdown_nic(bp);
7c673cae
FG		 660 bnxt_free_tx_mbufs(bp);
661 bnxt_free_rx_mbufs(bp);
7c673cae
FG		 662 return rc;
663}
664
665static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
666{
667 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
9f95a23c
TL		 668 int rc = 0;
669
670 if (!bp->link_info.link_up)
671 rc = bnxt_set_hwrm_link_config(bp, true);
672 if (!rc)
673 eth_dev->data->dev_link.link_status = 1;
7c673cae 674
9f95a23c 675 bnxt_print_link_info(eth_dev);
7c673cae
FG		 676 return 0;
677}
678
679static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
680{
681 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
682
683 eth_dev->data->dev_link.link_status = 0;
684 bnxt_set_hwrm_link_config(bp, false);
9f95a23c
TL		 685 bp->link_info.link_up = 0;
686
7c673cae
FG		 687 return 0;
688}
689
690/* Unload the driver, release resources */
691static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
692{
693 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
694
9f95a23c 695 bp->flags &= ~BNXT_FLAG_INIT_DONE;
7c673cae
FG		 696 if (bp->eth_dev->data->dev_started) {
697 /* TBD: STOP HW queues DMA */
698 eth_dev->data->dev_link.link_status = 0;
699 }
700 bnxt_set_hwrm_link_config(bp, false);
9f95a23c
TL		 701 bnxt_hwrm_port_clr_stats(bp);
702 bnxt_free_tx_mbufs(bp);
703 bnxt_free_rx_mbufs(bp);
7c673cae
FG		 704 bnxt_shutdown_nic(bp);
705 bp->dev_stopped = 1;
706}
707
708static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
709{
710 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
711
712 if (bp->dev_stopped == 0)
713 bnxt_dev_stop_op(eth_dev);
714
7c673cae
FG		 715 if (eth_dev->data->mac_addrs != NULL) {
716 rte_free(eth_dev->data->mac_addrs);
717 eth_dev->data->mac_addrs = NULL;
718 }
719 if (bp->grp_info != NULL) {
720 rte_free(bp->grp_info);
721 bp->grp_info = NULL;
722 }
9f95a23c
TL		 723
724 bnxt_dev_uninit(eth_dev);
7c673cae
FG		 725}
726
727static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
728 uint32_t index)
729{
730 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
731 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
732 struct bnxt_vnic_info *vnic;
733 struct bnxt_filter_info *filter, *temp_filter;
9f95a23c 734 uint32_t i;
7c673cae
FG		 735
736 /*
737 * Loop through all VNICs from the specified filter flow pools to
738 * remove the corresponding MAC addr filter
739 */
9f95a23c 740 for (i = 0; i < bp->nr_vnics; i++) {
7c673cae
FG		 741 if (!(pool_mask & (1ULL << i)))
742 continue;
743
9f95a23c
TL		 744 vnic = &bp->vnic_info[i];
745 filter = STAILQ_FIRST(&vnic->filter);
746 while (filter) {
747 temp_filter = STAILQ_NEXT(filter, next);
748 if (filter->mac_index == index) {
749 STAILQ_REMOVE(&vnic->filter, filter,
750 bnxt_filter_info, next);
751 bnxt_hwrm_clear_l2_filter(bp, filter);
752 filter->mac_index = INVALID_MAC_INDEX;
753 memset(&filter->l2_addr, 0, ETHER_ADDR_LEN);
754 STAILQ_INSERT_TAIL(&bp->free_filter_list,
755 filter, next);
7c673cae 756 }
9f95a23c 757 filter = temp_filter;
7c673cae
FG		 758 }
759 }
760}
761
11fdf7f2
TL		 762static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
763 struct ether_addr *mac_addr,
764 uint32_t index, uint32_t pool)
7c673cae
FG		 765{
766 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
9f95a23c 767 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
7c673cae
FG		 768 struct bnxt_filter_info *filter;
769
9f95a23c
TL		 770 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
771 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
11fdf7f2 772 return -ENOTSUP;
7c673cae
FG		 773 }
774
775 if (!vnic) {
9f95a23c 776 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
11fdf7f2 777 return -EINVAL;
7c673cae
FG		 778 }
779 /* Attach requested MAC address to the new l2_filter */
780 STAILQ_FOREACH(filter, &vnic->filter, next) {
781 if (filter->mac_index == index) {
9f95a23c 782 PMD_DRV_LOG(ERR,
7c673cae 783 "MAC addr already existed for pool %d\n", pool);
9f95a23c 784 return 0;
7c673cae
FG		 785 }
786 }
787 filter = bnxt_alloc_filter(bp);
788 if (!filter) {
9f95a23c 789 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
11fdf7f2 790 return -ENODEV;
7c673cae
FG		 791 }
792 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
793 filter->mac_index = index;
794 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
9f95a23c 795 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
7c673cae
FG		 796}
797
798int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
799{
800 int rc = 0;
801 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
802 struct rte_eth_link new;
803 unsigned int cnt = BNXT_LINK_WAIT_CNT;
804
805 memset(&new, 0, sizeof(new));
806 do {
807 /* Retrieve link info from hardware */
808 rc = bnxt_get_hwrm_link_config(bp, &new);
809 if (rc) {
810 new.link_speed = ETH_LINK_SPEED_100M;
811 new.link_duplex = ETH_LINK_FULL_DUPLEX;
9f95a23c
TL		 812 PMD_DRV_LOG(ERR,
813 "Failed to retrieve link rc = 0x%x!\n", rc);
7c673cae
FG		 814 goto out;
815 }
816 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
817
818 if (!wait_to_complete)
819 break;
820 } while (!new.link_status && cnt--);
821
822out:
823 /* Timed out or success */
824 if (new.link_status != eth_dev->data->dev_link.link_status ||
825 new.link_speed != eth_dev->data->dev_link.link_speed) {
9f95a23c
TL		 826 memcpy(&eth_dev->data->dev_link, &new,
827 sizeof(struct rte_eth_link));
828
829 _rte_eth_dev_callback_process(eth_dev,
830 RTE_ETH_EVENT_INTR_LSC,
831 NULL);
832
7c673cae
FG		 833 bnxt_print_link_info(eth_dev);
834 }
835
836 return rc;
837}
838
839static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
840{
841 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
842 struct bnxt_vnic_info *vnic;
843
844 if (bp->vnic_info == NULL)
845 return;
846
847 vnic = &bp->vnic_info[0];
848
849 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
9f95a23c 850 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
7c673cae
FG		 851}
852
853static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
854{
855 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
856 struct bnxt_vnic_info *vnic;
857
858 if (bp->vnic_info == NULL)
859 return;
860
861 vnic = &bp->vnic_info[0];
862
863 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
9f95a23c 864 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
7c673cae
FG		 865}
866
867static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
868{
869 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
870 struct bnxt_vnic_info *vnic;
871
872 if (bp->vnic_info == NULL)
873 return;
874
875 vnic = &bp->vnic_info[0];
876
877 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
9f95a23c 878 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
7c673cae
FG		 879}
880
881static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
882{
883 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
884 struct bnxt_vnic_info *vnic;
885
886 if (bp->vnic_info == NULL)
887 return;
888
889 vnic = &bp->vnic_info[0];
890
891 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
9f95a23c 892 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
7c673cae
FG		 893}
894
895static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
896 struct rte_eth_rss_reta_entry64 *reta_conf,
897 uint16_t reta_size)
898{
899 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
900 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
901 struct bnxt_vnic_info *vnic;
902 int i;
903
904 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
905 return -EINVAL;
906
907 if (reta_size != HW_HASH_INDEX_SIZE) {
9f95a23c 908 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
7c673cae
FG		 909 "(%d) must equal the size supported by the hardware "
910 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
911 return -EINVAL;
912 }
913 /* Update the RSS VNIC(s) */
9f95a23c
TL		 914 for (i = 0; i < bp->max_vnics; i++) {
915 vnic = &bp->vnic_info[i];
916 memcpy(vnic->rss_table, reta_conf, reta_size);
917 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
7c673cae
FG		 918 }
919 return 0;
920}
921
922static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
923 struct rte_eth_rss_reta_entry64 *reta_conf,
924 uint16_t reta_size)
925{
926 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
927 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11fdf7f2
TL		 928 struct rte_intr_handle *intr_handle
929 = &bp->pdev->intr_handle;
7c673cae
FG		 930
931 /* Retrieve from the default VNIC */
932 if (!vnic)
933 return -EINVAL;
934 if (!vnic->rss_table)
935 return -EINVAL;
936
937 if (reta_size != HW_HASH_INDEX_SIZE) {
9f95a23c 938 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
7c673cae
FG		 939 "(%d) must equal the size supported by the hardware "
940 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
941 return -EINVAL;
942 }
9f95a23c 943 /* EW - need to revisit here copying from uint64_t to uint16_t */
7c673cae
FG		 944 memcpy(reta_conf, vnic->rss_table, reta_size);
945
11fdf7f2 946 if (rte_intr_allow_others(intr_handle)) {
7c673cae
FG		 947 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
948 bnxt_dev_lsc_intr_setup(eth_dev);
949 }
950
951 return 0;
952}
953
954static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
955 struct rte_eth_rss_conf *rss_conf)
956{
957 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
958 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
959 struct bnxt_vnic_info *vnic;
960 uint16_t hash_type = 0;
9f95a23c 961 unsigned int i;
7c673cae
FG		 962
963 /*
964 * If RSS enablement were different than dev_configure,
965 * then return -EINVAL
966 */
967 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
968 if (!rss_conf->rss_hf)
9f95a23c 969 PMD_DRV_LOG(ERR, "Hash type NONE\n");
7c673cae
FG		 970 } else {
971 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
972 return -EINVAL;
973 }
9f95a23c
TL		 974
975 bp->flags |= BNXT_FLAG_UPDATE_HASH;
976 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
977
7c673cae
FG		 978 if (rss_conf->rss_hf & ETH_RSS_IPV4)
979 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
980 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
981 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
982 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
983 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
984 if (rss_conf->rss_hf & ETH_RSS_IPV6)
985 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
986 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
987 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
988 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
989 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
990
991 /* Update the RSS VNIC(s) */
9f95a23c
TL		 992 for (i = 0; i < bp->nr_vnics; i++) {
993 vnic = &bp->vnic_info[i];
994 vnic->hash_type = hash_type;
995
996 /*
997 * Use the supplied key if the key length is
998 * acceptable and the rss_key is not NULL
999 */
1000 if (rss_conf->rss_key &&
1001 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1002 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1003 rss_conf->rss_key_len);
1004
1005 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
7c673cae
FG		 1006 }
1007 return 0;
1008}
1009
1010static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1011 struct rte_eth_rss_conf *rss_conf)
1012{
1013 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1014 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1015 int len;
1016 uint32_t hash_types;
1017
1018 /* RSS configuration is the same for all VNICs */
1019 if (vnic && vnic->rss_hash_key) {
1020 if (rss_conf->rss_key) {
1021 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1022 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1023 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1024 }
1025
1026 hash_types = vnic->hash_type;
1027 rss_conf->rss_hf = 0;
1028 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1029 rss_conf->rss_hf |= ETH_RSS_IPV4;
1030 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1031 }
1032 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1033 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1034 hash_types &=
1035 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1036 }
1037 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1038 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1039 hash_types &=
1040 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1041 }
1042 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1043 rss_conf->rss_hf |= ETH_RSS_IPV6;
1044 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1045 }
1046 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1047 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1048 hash_types &=
1049 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1050 }
1051 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1052 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1053 hash_types &=
1054 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1055 }
1056 if (hash_types) {
9f95a23c 1057 PMD_DRV_LOG(ERR,
7c673cae
FG		 1058 "Unknwon RSS config from firmware (%08x), RSS disabled",
1059 vnic->hash_type);
1060 return -ENOTSUP;
1061 }
1062 } else {
1063 rss_conf->rss_hf = 0;
1064 }
1065 return 0;
1066}
1067
1068static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
9f95a23c 1069 struct rte_eth_fc_conf *fc_conf)
7c673cae
FG		 1070{
1071 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1072 struct rte_eth_link link_info;
1073 int rc;
1074
1075 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1076 if (rc)
1077 return rc;
1078
1079 memset(fc_conf, 0, sizeof(*fc_conf));
1080 if (bp->link_info.auto_pause)
1081 fc_conf->autoneg = 1;
1082 switch (bp->link_info.pause) {
1083 case 0:
1084 fc_conf->mode = RTE_FC_NONE;
1085 break;
1086 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1087 fc_conf->mode = RTE_FC_TX_PAUSE;
1088 break;
1089 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1090 fc_conf->mode = RTE_FC_RX_PAUSE;
1091 break;
1092 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1093 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1094 fc_conf->mode = RTE_FC_FULL;
1095 break;
1096 }
1097 return 0;
1098}
1099
1100static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1101 struct rte_eth_fc_conf *fc_conf)
1102{
1103 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1104
9f95a23c
TL		 1105 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1106 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
7c673cae
FG		 1107 return -ENOTSUP;
1108 }
1109
1110 switch (fc_conf->mode) {
1111 case RTE_FC_NONE:
1112 bp->link_info.auto_pause = 0;
1113 bp->link_info.force_pause = 0;
1114 break;
1115 case RTE_FC_RX_PAUSE:
1116 if (fc_conf->autoneg) {
1117 bp->link_info.auto_pause =
1118 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1119 bp->link_info.force_pause = 0;
1120 } else {
1121 bp->link_info.auto_pause = 0;
1122 bp->link_info.force_pause =
1123 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1124 }
1125 break;
1126 case RTE_FC_TX_PAUSE:
1127 if (fc_conf->autoneg) {
1128 bp->link_info.auto_pause =
1129 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1130 bp->link_info.force_pause = 0;
1131 } else {
1132 bp->link_info.auto_pause = 0;
1133 bp->link_info.force_pause =
1134 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1135 }
1136 break;
1137 case RTE_FC_FULL:
1138 if (fc_conf->autoneg) {
1139 bp->link_info.auto_pause =
1140 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1141 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1142 bp->link_info.force_pause = 0;
1143 } else {
1144 bp->link_info.auto_pause = 0;
1145 bp->link_info.force_pause =
1146 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1147 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1148 }
1149 break;
1150 }
1151 return bnxt_set_hwrm_link_config(bp, true);
1152}
1153
9f95a23c
TL		 1154/* Add UDP tunneling port */
1155static int
1156bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1157 struct rte_eth_udp_tunnel *udp_tunnel)
7c673cae 1158{
9f95a23c
TL		 1159 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1160 uint16_t tunnel_type = 0;
1161 int rc = 0;
1162
1163 switch (udp_tunnel->prot_type) {
1164 case RTE_TUNNEL_TYPE_VXLAN:
1165 if (bp->vxlan_port_cnt) {
1166 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1167 udp_tunnel->udp_port);
1168 if (bp->vxlan_port != udp_tunnel->udp_port) {
1169 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1170 return -ENOSPC;
1171 }
1172 bp->vxlan_port_cnt++;
1173 return 0;
1174 }
1175 tunnel_type =
1176 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1177 bp->vxlan_port_cnt++;
1178 break;
1179 case RTE_TUNNEL_TYPE_GENEVE:
1180 if (bp->geneve_port_cnt) {
1181 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1182 udp_tunnel->udp_port);
1183 if (bp->geneve_port != udp_tunnel->udp_port) {
1184 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1185 return -ENOSPC;
1186 }
1187 bp->geneve_port_cnt++;
1188 return 0;
1189 }
1190 tunnel_type =
1191 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1192 bp->geneve_port_cnt++;
1193 break;
1194 default:
1195 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1196 return -ENOTSUP;
1197 }
1198 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1199 tunnel_type);
1200 return rc;
7c673cae
FG		 1201}
1202
9f95a23c
TL		 1203static int
1204bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1205 struct rte_eth_udp_tunnel *udp_tunnel)
7c673cae 1206{
9f95a23c
TL		 1207 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1208 uint16_t tunnel_type = 0;
1209 uint16_t port = 0;
1210 int rc = 0;
7c673cae 1211
9f95a23c
TL		 1212 switch (udp_tunnel->prot_type) {
1213 case RTE_TUNNEL_TYPE_VXLAN:
1214 if (!bp->vxlan_port_cnt) {
1215 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1216 return -EINVAL;
1217 }
1218 if (bp->vxlan_port != udp_tunnel->udp_port) {
1219 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1220 udp_tunnel->udp_port, bp->vxlan_port);
1221 return -EINVAL;
1222 }
1223 if (--bp->vxlan_port_cnt)
1224 return 0;
7c673cae 1225
9f95a23c
TL		 1226 tunnel_type =
1227 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1228 port = bp->vxlan_fw_dst_port_id;
1229 break;
1230 case RTE_TUNNEL_TYPE_GENEVE:
1231 if (!bp->geneve_port_cnt) {
1232 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1233 return -EINVAL;
1234 }
1235 if (bp->geneve_port != udp_tunnel->udp_port) {
1236 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1237 udp_tunnel->udp_port, bp->geneve_port);
1238 return -EINVAL;
1239 }
1240 if (--bp->geneve_port_cnt)
1241 return 0;
7c673cae 1242
9f95a23c
TL		 1243 tunnel_type =
1244 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1245 port = bp->geneve_fw_dst_port_id;
1246 break;
1247 default:
1248 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1249 return -ENOTSUP;
7c673cae 1250 }
7c673cae 1251
9f95a23c
TL		 1252 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1253 if (!rc) {
1254 if (tunnel_type ==
1255 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1256 bp->vxlan_port = 0;
1257 if (tunnel_type ==
1258 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1259 bp->geneve_port = 0;
1260 }
1261 return rc;
1262}
7c673cae 1263
9f95a23c
TL		 1264static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1265{
1266 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1267 struct bnxt_vnic_info *vnic;
1268 unsigned int i;
1269 int rc = 0;
1270 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
7c673cae 1271
9f95a23c
TL		 1272 /* Cycle through all VNICs */
1273 for (i = 0; i < bp->nr_vnics; i++) {
1274 /*
1275 * For each VNIC and each associated filter(s)
1276 * if VLAN exists && VLAN matches vlan_id
1277 * remove the MAC+VLAN filter
1278 * add a new MAC only filter
1279 * else
1280 * VLAN filter doesn't exist, just skip and continue
1281 */
1282 vnic = &bp->vnic_info[i];
1283 filter = STAILQ_FIRST(&vnic->filter);
1284 while (filter) {
1285 temp_filter = STAILQ_NEXT(filter, next);
1286
1287 if (filter->enables & chk &&
1288 filter->l2_ovlan == vlan_id) {
1289 /* Must delete the filter */
1290 STAILQ_REMOVE(&vnic->filter, filter,
1291 bnxt_filter_info, next);
1292 bnxt_hwrm_clear_l2_filter(bp, filter);
1293 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1294 filter, next);
1295
1296 /*
1297 * Need to examine to see if the MAC
1298 * filter already existed or not before
1299 * allocating a new one
1300 */
1301
1302 new_filter = bnxt_alloc_filter(bp);
1303 if (!new_filter) {
1304 PMD_DRV_LOG(ERR,
1305 "MAC/VLAN filter alloc failed\n");
1306 rc = -ENOMEM;
1307 goto exit;
1308 }
1309 STAILQ_INSERT_TAIL(&vnic->filter,
1310 new_filter, next);
1311 /* Inherit MAC from previous filter */
1312 new_filter->mac_index =
1313 filter->mac_index;
1314 memcpy(new_filter->l2_addr, filter->l2_addr,
1315 ETHER_ADDR_LEN);
1316 /* MAC only filter */
1317 rc = bnxt_hwrm_set_l2_filter(bp,
1318 vnic->fw_vnic_id,
1319 new_filter);
1320 if (rc)
1321 goto exit;
1322 PMD_DRV_LOG(INFO,
1323 "Del Vlan filter for %d\n",
1324 vlan_id);
1325 }
1326 filter = temp_filter;
1327 }
1328 }
1329exit:
7c673cae
FG		 1330 return rc;
1331}
1332
9f95a23c 1333static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
7c673cae 1334{
9f95a23c
TL		 1335 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1336 struct bnxt_vnic_info *vnic;
1337 unsigned int i;
1338 int rc = 0;
1339 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1340 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1341 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
7c673cae 1342
9f95a23c
TL		 1343 /* Cycle through all VNICs */
1344 for (i = 0; i < bp->nr_vnics; i++) {
1345 /*
1346 * For each VNIC and each associated filter(s)
1347 * if VLAN exists:
1348 * if VLAN matches vlan_id
1349 * VLAN filter already exists, just skip and continue
1350 * else
1351 * add a new MAC+VLAN filter
1352 * else
1353 * Remove the old MAC only filter
1354 * Add a new MAC+VLAN filter
1355 */
1356 vnic = &bp->vnic_info[i];
1357 filter = STAILQ_FIRST(&vnic->filter);
1358 while (filter) {
1359 temp_filter = STAILQ_NEXT(filter, next);
1360
1361 if (filter->enables & chk) {
1362 if (filter->l2_ivlan == vlan_id)
1363 goto cont;
1364 } else {
1365 /* Must delete the MAC filter */
1366 STAILQ_REMOVE(&vnic->filter, filter,
1367 bnxt_filter_info, next);
1368 bnxt_hwrm_clear_l2_filter(bp, filter);
1369 filter->l2_ovlan = 0;
1370 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1371 filter, next);
1372 }
1373 new_filter = bnxt_alloc_filter(bp);
1374 if (!new_filter) {
1375 PMD_DRV_LOG(ERR,
1376 "MAC/VLAN filter alloc failed\n");
1377 rc = -ENOMEM;
1378 goto exit;
1379 }
1380 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1381 /* Inherit MAC from the previous filter */
1382 new_filter->mac_index = filter->mac_index;
1383 memcpy(new_filter->l2_addr, filter->l2_addr,
1384 ETHER_ADDR_LEN);
1385 /* MAC + VLAN ID filter */
1386 new_filter->l2_ivlan = vlan_id;
1387 new_filter->l2_ivlan_mask = 0xF000;
1388 new_filter->enables |= en;
1389 rc = bnxt_hwrm_set_l2_filter(bp,
1390 vnic->fw_vnic_id,
1391 new_filter);
1392 if (rc)
1393 goto exit;
1394 PMD_DRV_LOG(INFO,
1395 "Added Vlan filter for %d\n", vlan_id);
1396cont:
1397 filter = temp_filter;
1398 }
1399 }
1400exit:
1401 return rc;
1402}
7c673cae 1403
9f95a23c
TL		 1404static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1405 uint16_t vlan_id, int on)
1406{
1407 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
11fdf7f2 1408
9f95a23c
TL		 1409 /* These operations apply to ALL existing MAC/VLAN filters */
1410 if (on)
1411 return bnxt_add_vlan_filter(bp, vlan_id);
1412 else
1413 return bnxt_del_vlan_filter(bp, vlan_id);
1414}
7c673cae 1415
9f95a23c
TL		 1416static int
1417bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1418{
1419 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1420 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1421 unsigned int i;
1422
1423 if (mask & ETH_VLAN_FILTER_MASK) {
1424 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1425 /* Remove any VLAN filters programmed */
1426 for (i = 0; i < 4095; i++)
1427 bnxt_del_vlan_filter(bp, i);
1428 }
1429 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1430 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1431 }
1432
1433 if (mask & ETH_VLAN_STRIP_MASK) {
1434 /* Enable or disable VLAN stripping */
1435 for (i = 0; i < bp->nr_vnics; i++) {
1436 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1437 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1438 vnic->vlan_strip = true;
1439 else
1440 vnic->vlan_strip = false;
1441 bnxt_hwrm_vnic_cfg(bp, vnic);
1442 }
1443 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1444 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1445 }
1446
1447 if (mask & ETH_VLAN_EXTEND_MASK)
1448 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1449
1450 return 0;
1451}
1452
1453static int
1454bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1455{
1456 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1457 /* Default Filter is tied to VNIC 0 */
1458 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1459 struct bnxt_filter_info *filter;
1460 int rc;
1461
1462 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1463 return -EPERM;
1464
1465 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1466
1467 STAILQ_FOREACH(filter, &vnic->filter, next) {
1468 /* Default Filter is at Index 0 */
1469 if (filter->mac_index != 0)
1470 continue;
1471 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1472 if (rc)
1473 return rc;
1474 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1475 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1476 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1477 filter->enables |=
1478 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1479 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1480 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1481 if (rc)
1482 return rc;
1483 filter->mac_index = 0;
1484 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1485 }
1486
1487 return 0;
1488}
1489
1490static int
1491bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1492 struct ether_addr *mc_addr_set,
1493 uint32_t nb_mc_addr)
1494{
1495 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1496 char *mc_addr_list = (char *)mc_addr_set;
1497 struct bnxt_vnic_info *vnic;
1498 uint32_t off = 0, i = 0;
1499
1500 vnic = &bp->vnic_info[0];
1501
1502 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1503 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1504 goto allmulti;
1505 }
1506
1507 /* TODO Check for Duplicate mcast addresses */
1508 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1509 for (i = 0; i < nb_mc_addr; i++) {
1510 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1511 off += ETHER_ADDR_LEN;
1512 }
1513
1514 vnic->mc_addr_cnt = i;
1515
1516allmulti:
1517 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1518}
1519
1520static int
1521bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1522{
1523 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1524 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1525 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1526 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1527 int ret;
1528
1529 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1530 fw_major, fw_minor, fw_updt);
1531
1532 ret += 1; /* add the size of '\0' */
1533 if (fw_size < (uint32_t)ret)
1534 return ret;
1535 else
1536 return 0;
1537}
1538
1539static void
1540bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1541 struct rte_eth_rxq_info *qinfo)
1542{
1543 struct bnxt_rx_queue *rxq;
1544
1545 rxq = dev->data->rx_queues[queue_id];
1546
1547 qinfo->mp = rxq->mb_pool;
1548 qinfo->scattered_rx = dev->data->scattered_rx;
1549 qinfo->nb_desc = rxq->nb_rx_desc;
1550
1551 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1552 qinfo->conf.rx_drop_en = 0;
1553 qinfo->conf.rx_deferred_start = 0;
1554}
1555
1556static void
1557bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1558 struct rte_eth_txq_info *qinfo)
1559{
1560 struct bnxt_tx_queue *txq;
1561
1562 txq = dev->data->tx_queues[queue_id];
1563
1564 qinfo->nb_desc = txq->nb_tx_desc;
1565
1566 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1567 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1568 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1569
1570 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1571 qinfo->conf.tx_rs_thresh = 0;
1572 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1573}
1574
1575static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1576{
1577 struct bnxt *bp = eth_dev->data->dev_private;
1578 struct rte_eth_dev_info dev_info;
1579 uint32_t rc = 0;
1580 uint32_t i;
1581
1582 bnxt_dev_info_get_op(eth_dev, &dev_info);
1583
1584 if (new_mtu < ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1585 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1586 ETHER_MIN_MTU, BNXT_MAX_MTU);
1587 return -EINVAL;
1588 }
1589
1590 if (new_mtu > ETHER_MTU) {
1591 bp->flags |= BNXT_FLAG_JUMBO;
1592 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1593 DEV_RX_OFFLOAD_JUMBO_FRAME;
1594 } else {
1595 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1596 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1597 bp->flags &= ~BNXT_FLAG_JUMBO;
1598 }
1599
1600 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1601 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1602
1603 eth_dev->data->mtu = new_mtu;
1604 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1605
1606 for (i = 0; i < bp->nr_vnics; i++) {
1607 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1608 uint16_t size = 0;
1609
1610 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1611 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1612 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1613 if (rc)
1614 break;
1615
1616 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1617 size -= RTE_PKTMBUF_HEADROOM;
1618
1619 if (size < new_mtu) {
1620 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1621 if (rc)
1622 return rc;
1623 }
1624 }
1625
1626 return rc;
1627}
1628
1629static int
1630bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1631{
1632 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1633 uint16_t vlan = bp->vlan;
1634 int rc;
1635
1636 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1637 PMD_DRV_LOG(ERR,
1638 "PVID cannot be modified for this function\n");
1639 return -ENOTSUP;
1640 }
1641 bp->vlan = on ? pvid : 0;
1642
1643 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1644 if (rc)
1645 bp->vlan = vlan;
1646 return rc;
1647}
1648
1649static int
1650bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1651{
1652 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1653
1654 return bnxt_hwrm_port_led_cfg(bp, true);
1655}
1656
1657static int
1658bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1659{
1660 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1661
1662 return bnxt_hwrm_port_led_cfg(bp, false);
1663}
1664
1665static uint32_t
1666bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1667{
1668 uint32_t desc = 0, raw_cons = 0, cons;
1669 struct bnxt_cp_ring_info *cpr;
1670 struct bnxt_rx_queue *rxq;
1671 struct rx_pkt_cmpl *rxcmp;
1672 uint16_t cmp_type;
1673 uint8_t cmp = 1;
1674 bool valid;
1675
1676 rxq = dev->data->rx_queues[rx_queue_id];
1677 cpr = rxq->cp_ring;
1678 valid = cpr->valid;
1679
1680 while (raw_cons < rxq->nb_rx_desc) {
1681 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1682 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1683
1684 if (!CMPL_VALID(rxcmp, valid))
1685 goto nothing_to_do;
1686 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1687 cmp_type = CMP_TYPE(rxcmp);
1688 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1689 cmp = (rte_le_to_cpu_32(
1690 ((struct rx_tpa_end_cmpl *)
1691 (rxcmp))->agg_bufs_v1) &
1692 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1693 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1694 desc++;
1695 } else if (cmp_type == 0x11) {
1696 desc++;
1697 cmp = (rxcmp->agg_bufs_v1 &
1698 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1699 RX_PKT_CMPL_AGG_BUFS_SFT;
1700 } else {
1701 cmp = 1;
1702 }
1703nothing_to_do:
1704 raw_cons += cmp ? cmp : 2;
1705 }
1706
1707 return desc;
1708}
1709
1710static int
1711bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1712{
1713 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1714 struct bnxt_rx_ring_info *rxr;
1715 struct bnxt_cp_ring_info *cpr;
1716 struct bnxt_sw_rx_bd *rx_buf;
1717 struct rx_pkt_cmpl *rxcmp;
1718 uint32_t cons, cp_cons;
1719
1720 if (!rxq)
1721 return -EINVAL;
1722
1723 cpr = rxq->cp_ring;
1724 rxr = rxq->rx_ring;
1725
1726 if (offset >= rxq->nb_rx_desc)
1727 return -EINVAL;
1728
1729 cons = RING_CMP(cpr->cp_ring_struct, offset);
1730 cp_cons = cpr->cp_raw_cons;
1731 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1732
1733 if (cons > cp_cons) {
1734 if (CMPL_VALID(rxcmp, cpr->valid))
1735 return RTE_ETH_RX_DESC_DONE;
1736 } else {
1737 if (CMPL_VALID(rxcmp, !cpr->valid))
1738 return RTE_ETH_RX_DESC_DONE;
1739 }
1740 rx_buf = &rxr->rx_buf_ring[cons];
1741 if (rx_buf->mbuf == NULL)
1742 return RTE_ETH_RX_DESC_UNAVAIL;
1743
1744
1745 return RTE_ETH_RX_DESC_AVAIL;
1746}
1747
1748static int
1749bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1750{
1751 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1752 struct bnxt_tx_ring_info *txr;
1753 struct bnxt_cp_ring_info *cpr;
1754 struct bnxt_sw_tx_bd *tx_buf;
1755 struct tx_pkt_cmpl *txcmp;
1756 uint32_t cons, cp_cons;
1757
1758 if (!txq)
1759 return -EINVAL;
1760
1761 cpr = txq->cp_ring;
1762 txr = txq->tx_ring;
1763
1764 if (offset >= txq->nb_tx_desc)
1765 return -EINVAL;
1766
1767 cons = RING_CMP(cpr->cp_ring_struct, offset);
1768 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1769 cp_cons = cpr->cp_raw_cons;
1770
1771 if (cons > cp_cons) {
1772 if (CMPL_VALID(txcmp, cpr->valid))
1773 return RTE_ETH_TX_DESC_UNAVAIL;
1774 } else {
1775 if (CMPL_VALID(txcmp, !cpr->valid))
1776 return RTE_ETH_TX_DESC_UNAVAIL;
1777 }
1778 tx_buf = &txr->tx_buf_ring[cons];
1779 if (tx_buf->mbuf == NULL)
1780 return RTE_ETH_TX_DESC_DONE;
1781
1782 return RTE_ETH_TX_DESC_FULL;
1783}
1784
1785static struct bnxt_filter_info *
1786bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1787 struct rte_eth_ethertype_filter *efilter,
1788 struct bnxt_vnic_info *vnic0,
1789 struct bnxt_vnic_info *vnic,
1790 int *ret)
1791{
1792 struct bnxt_filter_info *mfilter = NULL;
1793 int match = 0;
1794 *ret = 0;
1795
1796 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1797 efilter->ether_type == ETHER_TYPE_IPv6) {
1798 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1799 " ethertype filter.", efilter->ether_type);
1800 *ret = -EINVAL;
1801 goto exit;
1802 }
1803 if (efilter->queue >= bp->rx_nr_rings) {
1804 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1805 *ret = -EINVAL;
1806 goto exit;
1807 }
1808
1809 vnic0 = &bp->vnic_info[0];
1810 vnic = &bp->vnic_info[efilter->queue];
1811 if (vnic == NULL) {
1812 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1813 *ret = -EINVAL;
1814 goto exit;
1815 }
1816
1817 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1818 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1819 if ((!memcmp(efilter->mac_addr.addr_bytes,
1820 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1821 mfilter->flags ==
1822 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1823 mfilter->ethertype == efilter->ether_type)) {
1824 match = 1;
1825 break;
1826 }
1827 }
1828 } else {
1829 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1830 if ((!memcmp(efilter->mac_addr.addr_bytes,
1831 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1832 mfilter->ethertype == efilter->ether_type &&
1833 mfilter->flags ==
1834 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1835 match = 1;
1836 break;
1837 }
1838 }
1839
1840 if (match)
1841 *ret = -EEXIST;
1842
1843exit:
1844 return mfilter;
1845}
1846
1847static int
1848bnxt_ethertype_filter(struct rte_eth_dev *dev,
1849 enum rte_filter_op filter_op,
1850 void *arg)
1851{
1852 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1853 struct rte_eth_ethertype_filter *efilter =
1854 (struct rte_eth_ethertype_filter *)arg;
1855 struct bnxt_filter_info *bfilter, *filter1;
1856 struct bnxt_vnic_info *vnic, *vnic0;
1857 int ret;
1858
1859 if (filter_op == RTE_ETH_FILTER_NOP)
1860 return 0;
1861
1862 if (arg == NULL) {
1863 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1864 filter_op);
1865 return -EINVAL;
1866 }
1867
1868 vnic0 = &bp->vnic_info[0];
1869 vnic = &bp->vnic_info[efilter->queue];
1870
1871 switch (filter_op) {
1872 case RTE_ETH_FILTER_ADD:
1873 bnxt_match_and_validate_ether_filter(bp, efilter,
1874 vnic0, vnic, &ret);
1875 if (ret < 0)
1876 return ret;
1877
1878 bfilter = bnxt_get_unused_filter(bp);
1879 if (bfilter == NULL) {
1880 PMD_DRV_LOG(ERR,
1881 "Not enough resources for a new filter.\n");
1882 return -ENOMEM;
1883 }
1884 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1885 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1886 ETHER_ADDR_LEN);
1887 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1888 ETHER_ADDR_LEN);
1889 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1890 bfilter->ethertype = efilter->ether_type;
1891 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1892
1893 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1894 if (filter1 == NULL) {
1895 ret = -1;
1896 goto cleanup;
1897 }
1898 bfilter->enables |=
1899 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1900 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1901
1902 bfilter->dst_id = vnic->fw_vnic_id;
1903
1904 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1905 bfilter->flags =
1906 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1907 }
1908
1909 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1910 if (ret)
1911 goto cleanup;
1912 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1913 break;
1914 case RTE_ETH_FILTER_DELETE:
1915 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1916 vnic0, vnic, &ret);
1917 if (ret == -EEXIST) {
1918 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1919
1920 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1921 next);
1922 bnxt_free_filter(bp, filter1);
1923 } else if (ret == 0) {
1924 PMD_DRV_LOG(ERR, "No matching filter found\n");
1925 }
1926 break;
1927 default:
1928 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1929 ret = -EINVAL;
1930 goto error;
1931 }
1932 return ret;
1933cleanup:
1934 bnxt_free_filter(bp, bfilter);
1935error:
1936 return ret;
1937}
1938
1939static inline int
1940parse_ntuple_filter(struct bnxt *bp,
1941 struct rte_eth_ntuple_filter *nfilter,
1942 struct bnxt_filter_info *bfilter)
1943{
1944 uint32_t en = 0;
1945
1946 if (nfilter->queue >= bp->rx_nr_rings) {
1947 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1948 return -EINVAL;
1949 }
1950
1951 switch (nfilter->dst_port_mask) {
1952 case UINT16_MAX:
1953 bfilter->dst_port_mask = -1;
1954 bfilter->dst_port = nfilter->dst_port;
1955 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1956 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1957 break;
1958 default:
1959 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1960 return -EINVAL;
1961 }
1962
1963 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1964 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1965
1966 switch (nfilter->proto_mask) {
1967 case UINT8_MAX:
1968 if (nfilter->proto == 17) /* IPPROTO_UDP */
1969 bfilter->ip_protocol = 17;
1970 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1971 bfilter->ip_protocol = 6;
1972 else
1973 return -EINVAL;
1974 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1975 break;
1976 default:
1977 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1978 return -EINVAL;
1979 }
1980
1981 switch (nfilter->dst_ip_mask) {
1982 case UINT32_MAX:
1983 bfilter->dst_ipaddr_mask[0] = -1;
1984 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1985 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1986 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1987 break;
1988 default:
1989 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1990 return -EINVAL;
1991 }
1992
1993 switch (nfilter->src_ip_mask) {
1994 case UINT32_MAX:
1995 bfilter->src_ipaddr_mask[0] = -1;
1996 bfilter->src_ipaddr[0] = nfilter->src_ip;
1997 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1998 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1999 break;
2000 default:
2001 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2002 return -EINVAL;
2003 }
2004
2005 switch (nfilter->src_port_mask) {
2006 case UINT16_MAX:
2007 bfilter->src_port_mask = -1;
2008 bfilter->src_port = nfilter->src_port;
2009 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2010 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2011 break;
2012 default:
2013 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2014 return -EINVAL;
2015 }
2016
2017 //TODO Priority
2018 //nfilter->priority = (uint8_t)filter->priority;
2019
2020 bfilter->enables = en;
2021 return 0;
2022}
2023
2024static struct bnxt_filter_info*
2025bnxt_match_ntuple_filter(struct bnxt *bp,
2026 struct bnxt_filter_info *bfilter,
2027 struct bnxt_vnic_info **mvnic)
2028{
2029 struct bnxt_filter_info *mfilter = NULL;
2030 int i;
2031
2032 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2033 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2034 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2035 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2036 bfilter->src_ipaddr_mask[0] ==
2037 mfilter->src_ipaddr_mask[0] &&
2038 bfilter->src_port == mfilter->src_port &&
2039 bfilter->src_port_mask == mfilter->src_port_mask &&
2040 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2041 bfilter->dst_ipaddr_mask[0] ==
2042 mfilter->dst_ipaddr_mask[0] &&
2043 bfilter->dst_port == mfilter->dst_port &&
2044 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2045 bfilter->flags == mfilter->flags &&
2046 bfilter->enables == mfilter->enables) {
2047 if (mvnic)
2048 *mvnic = vnic;
2049 return mfilter;
2050 }
2051 }
2052 }
2053 return NULL;
2054}
2055
2056static int
2057bnxt_cfg_ntuple_filter(struct bnxt *bp,
2058 struct rte_eth_ntuple_filter *nfilter,
2059 enum rte_filter_op filter_op)
2060{
2061 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2062 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2063 int ret;
2064
2065 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2066 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2067 return -EINVAL;
2068 }
2069
2070 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2071 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2072 return -EINVAL;
2073 }
2074
2075 bfilter = bnxt_get_unused_filter(bp);
2076 if (bfilter == NULL) {
2077 PMD_DRV_LOG(ERR,
2078 "Not enough resources for a new filter.\n");
2079 return -ENOMEM;
2080 }
2081 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2082 if (ret < 0)
2083 goto free_filter;
2084
2085 vnic = &bp->vnic_info[nfilter->queue];
2086 vnic0 = &bp->vnic_info[0];
2087 filter1 = STAILQ_FIRST(&vnic0->filter);
2088 if (filter1 == NULL) {
2089 ret = -1;
2090 goto free_filter;
2091 }
2092
2093 bfilter->dst_id = vnic->fw_vnic_id;
2094 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2095 bfilter->enables |=
2096 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2097 bfilter->ethertype = 0x800;
2098 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2099
2100 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2101
2102 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2103 bfilter->dst_id == mfilter->dst_id) {
2104 PMD_DRV_LOG(ERR, "filter exists.\n");
2105 ret = -EEXIST;
2106 goto free_filter;
2107 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2108 bfilter->dst_id != mfilter->dst_id) {
2109 mfilter->dst_id = vnic->fw_vnic_id;
2110 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2111 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2112 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2113 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2114 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2115 goto free_filter;
2116 }
2117 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2118 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2119 ret = -ENOENT;
2120 goto free_filter;
2121 }
2122
2123 if (filter_op == RTE_ETH_FILTER_ADD) {
2124 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2125 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2126 if (ret)
2127 goto free_filter;
2128 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2129 } else {
2130 if (mfilter == NULL) {
2131 /* This should not happen. But for Coverity! */
2132 ret = -ENOENT;
2133 goto free_filter;
2134 }
2135 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2136
2137 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2138 bnxt_free_filter(bp, mfilter);
2139 mfilter->fw_l2_filter_id = -1;
2140 bnxt_free_filter(bp, bfilter);
2141 bfilter->fw_l2_filter_id = -1;
2142 }
2143
2144 return 0;
2145free_filter:
2146 bfilter->fw_l2_filter_id = -1;
2147 bnxt_free_filter(bp, bfilter);
2148 return ret;
2149}
2150
2151static int
2152bnxt_ntuple_filter(struct rte_eth_dev *dev,
2153 enum rte_filter_op filter_op,
2154 void *arg)
2155{
2156 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2157 int ret;
2158
2159 if (filter_op == RTE_ETH_FILTER_NOP)
2160 return 0;
2161
2162 if (arg == NULL) {
2163 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2164 filter_op);
2165 return -EINVAL;
2166 }
2167
2168 switch (filter_op) {
2169 case RTE_ETH_FILTER_ADD:
2170 ret = bnxt_cfg_ntuple_filter(bp,
2171 (struct rte_eth_ntuple_filter *)arg,
2172 filter_op);
2173 break;
2174 case RTE_ETH_FILTER_DELETE:
2175 ret = bnxt_cfg_ntuple_filter(bp,
2176 (struct rte_eth_ntuple_filter *)arg,
2177 filter_op);
2178 break;
2179 default:
2180 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2181 ret = -EINVAL;
2182 break;
2183 }
2184 return ret;
2185}
2186
2187static int
2188bnxt_parse_fdir_filter(struct bnxt *bp,
2189 struct rte_eth_fdir_filter *fdir,
2190 struct bnxt_filter_info *filter)
2191{
2192 enum rte_fdir_mode fdir_mode =
2193 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2194 struct bnxt_vnic_info *vnic0, *vnic;
2195 struct bnxt_filter_info *filter1;
2196 uint32_t en = 0;
2197 int i;
2198
2199 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2200 return -EINVAL;
2201
2202 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2203 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2204
2205 switch (fdir->input.flow_type) {
2206 case RTE_ETH_FLOW_IPV4:
2207 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2208 /* FALLTHROUGH */
2209 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2210 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2211 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2213 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2214 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2215 filter->ip_addr_type =
2216 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2217 filter->src_ipaddr_mask[0] = 0xffffffff;
2218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2219 filter->dst_ipaddr_mask[0] = 0xffffffff;
2220 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2221 filter->ethertype = 0x800;
2222 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2223 break;
2224 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2225 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2226 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2227 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2228 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2229 filter->dst_port_mask = 0xffff;
2230 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2231 filter->src_port_mask = 0xffff;
2232 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2233 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2234 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2235 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2236 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2237 filter->ip_protocol = 6;
2238 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2239 filter->ip_addr_type =
2240 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2241 filter->src_ipaddr_mask[0] = 0xffffffff;
2242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2243 filter->dst_ipaddr_mask[0] = 0xffffffff;
2244 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2245 filter->ethertype = 0x800;
2246 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2247 break;
2248 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2249 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2250 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2251 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2252 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2253 filter->dst_port_mask = 0xffff;
2254 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2255 filter->src_port_mask = 0xffff;
2256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2257 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2259 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2260 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2261 filter->ip_protocol = 17;
2262 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2263 filter->ip_addr_type =
2264 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2265 filter->src_ipaddr_mask[0] = 0xffffffff;
2266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2267 filter->dst_ipaddr_mask[0] = 0xffffffff;
2268 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2269 filter->ethertype = 0x800;
2270 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2271 break;
2272 case RTE_ETH_FLOW_IPV6:
2273 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2274 /* FALLTHROUGH */
2275 filter->ip_addr_type =
2276 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2277 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2278 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2279 rte_memcpy(filter->src_ipaddr,
2280 fdir->input.flow.ipv6_flow.src_ip, 16);
2281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2282 rte_memcpy(filter->dst_ipaddr,
2283 fdir->input.flow.ipv6_flow.dst_ip, 16);
2284 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2285 memset(filter->dst_ipaddr_mask, 0xff, 16);
2286 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2287 memset(filter->src_ipaddr_mask, 0xff, 16);
2288 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2289 filter->ethertype = 0x86dd;
2290 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2291 break;
2292 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2293 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2294 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2295 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2296 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2297 filter->dst_port_mask = 0xffff;
2298 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2299 filter->src_port_mask = 0xffff;
2300 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2301 filter->ip_addr_type =
2302 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2303 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2304 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2305 rte_memcpy(filter->src_ipaddr,
2306 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2307 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2308 rte_memcpy(filter->dst_ipaddr,
2309 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2310 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2311 memset(filter->dst_ipaddr_mask, 0xff, 16);
2312 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2313 memset(filter->src_ipaddr_mask, 0xff, 16);
2314 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2315 filter->ethertype = 0x86dd;
2316 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2317 break;
2318 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2319 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2320 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2321 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2322 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2323 filter->dst_port_mask = 0xffff;
2324 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2325 filter->src_port_mask = 0xffff;
2326 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2327 filter->ip_addr_type =
2328 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2329 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2330 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2331 rte_memcpy(filter->src_ipaddr,
2332 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2333 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2334 rte_memcpy(filter->dst_ipaddr,
2335 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2336 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2337 memset(filter->dst_ipaddr_mask, 0xff, 16);
2338 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2339 memset(filter->src_ipaddr_mask, 0xff, 16);
2340 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2341 filter->ethertype = 0x86dd;
2342 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2343 break;
2344 case RTE_ETH_FLOW_L2_PAYLOAD:
2345 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2346 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2347 break;
2348 case RTE_ETH_FLOW_VXLAN:
2349 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2350 return -EINVAL;
2351 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2352 filter->tunnel_type =
2353 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2354 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2355 break;
2356 case RTE_ETH_FLOW_NVGRE:
2357 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2358 return -EINVAL;
2359 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2360 filter->tunnel_type =
2361 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2362 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2363 break;
2364 case RTE_ETH_FLOW_UNKNOWN:
2365 case RTE_ETH_FLOW_RAW:
2366 case RTE_ETH_FLOW_FRAG_IPV4:
2367 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2368 case RTE_ETH_FLOW_FRAG_IPV6:
2369 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2370 case RTE_ETH_FLOW_IPV6_EX:
2371 case RTE_ETH_FLOW_IPV6_TCP_EX:
2372 case RTE_ETH_FLOW_IPV6_UDP_EX:
2373 case RTE_ETH_FLOW_GENEVE:
2374 /* FALLTHROUGH */
2375 default:
2376 return -EINVAL;
2377 }
2378
2379 vnic0 = &bp->vnic_info[0];
2380 vnic = &bp->vnic_info[fdir->action.rx_queue];
2381 if (vnic == NULL) {
2382 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2383 return -EINVAL;
2384 }
2385
2386
2387 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2388 rte_memcpy(filter->dst_macaddr,
2389 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2390 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2391 }
2392
2393 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2394 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2395 filter1 = STAILQ_FIRST(&vnic0->filter);
2396 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2397 } else {
2398 filter->dst_id = vnic->fw_vnic_id;
2399 for (i = 0; i < ETHER_ADDR_LEN; i++)
2400 if (filter->dst_macaddr[i] == 0x00)
2401 filter1 = STAILQ_FIRST(&vnic0->filter);
2402 else
2403 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2404 }
2405
2406 if (filter1 == NULL)
2407 return -EINVAL;
2408
2409 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2410 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2411
2412 filter->enables = en;
2413
2414 return 0;
2415}
2416
2417static struct bnxt_filter_info *
2418bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2419 struct bnxt_vnic_info **mvnic)
2420{
2421 struct bnxt_filter_info *mf = NULL;
2422 int i;
2423
2424 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2425 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2426
2427 STAILQ_FOREACH(mf, &vnic->filter, next) {
2428 if (mf->filter_type == nf->filter_type &&
2429 mf->flags == nf->flags &&
2430 mf->src_port == nf->src_port &&
2431 mf->src_port_mask == nf->src_port_mask &&
2432 mf->dst_port == nf->dst_port &&
2433 mf->dst_port_mask == nf->dst_port_mask &&
2434 mf->ip_protocol == nf->ip_protocol &&
2435 mf->ip_addr_type == nf->ip_addr_type &&
2436 mf->ethertype == nf->ethertype &&
2437 mf->vni == nf->vni &&
2438 mf->tunnel_type == nf->tunnel_type &&
2439 mf->l2_ovlan == nf->l2_ovlan &&
2440 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2441 mf->l2_ivlan == nf->l2_ivlan &&
2442 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2443 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2444 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2445 ETHER_ADDR_LEN) &&
2446 !memcmp(mf->src_macaddr, nf->src_macaddr,
2447 ETHER_ADDR_LEN) &&
2448 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2449 ETHER_ADDR_LEN) &&
2450 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2451 sizeof(nf->src_ipaddr)) &&
2452 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2453 sizeof(nf->src_ipaddr_mask)) &&
2454 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2455 sizeof(nf->dst_ipaddr)) &&
2456 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2457 sizeof(nf->dst_ipaddr_mask))) {
2458 if (mvnic)
2459 *mvnic = vnic;
2460 return mf;
2461 }
2462 }
2463 }
2464 return NULL;
2465}
2466
2467static int
2468bnxt_fdir_filter(struct rte_eth_dev *dev,
2469 enum rte_filter_op filter_op,
2470 void *arg)
2471{
2472 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2473 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2474 struct bnxt_filter_info *filter, *match;
2475 struct bnxt_vnic_info *vnic, *mvnic;
2476 int ret = 0, i;
2477
2478 if (filter_op == RTE_ETH_FILTER_NOP)
2479 return 0;
2480
2481 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2482 return -EINVAL;
2483
2484 switch (filter_op) {
2485 case RTE_ETH_FILTER_ADD:
2486 case RTE_ETH_FILTER_DELETE:
2487 /* FALLTHROUGH */
2488 filter = bnxt_get_unused_filter(bp);
2489 if (filter == NULL) {
2490 PMD_DRV_LOG(ERR,
2491 "Not enough resources for a new flow.\n");
2492 return -ENOMEM;
2493 }
2494
2495 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2496 if (ret != 0)
2497 goto free_filter;
2498 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2499
2500 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2501 vnic = &bp->vnic_info[0];
2502 else
2503 vnic = &bp->vnic_info[fdir->action.rx_queue];
2504
2505 match = bnxt_match_fdir(bp, filter, &mvnic);
2506 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2507 if (match->dst_id == vnic->fw_vnic_id) {
2508 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2509 ret = -EEXIST;
2510 goto free_filter;
2511 } else {
2512 match->dst_id = vnic->fw_vnic_id;
2513 ret = bnxt_hwrm_set_ntuple_filter(bp,
2514 match->dst_id,
2515 match);
2516 STAILQ_REMOVE(&mvnic->filter, match,
2517 bnxt_filter_info, next);
2518 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2519 PMD_DRV_LOG(ERR,
2520 "Filter with matching pattern exist\n");
2521 PMD_DRV_LOG(ERR,
2522 "Updated it to new destination q\n");
2523 goto free_filter;
2524 }
2525 }
2526 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2527 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2528 ret = -ENOENT;
2529 goto free_filter;
2530 }
2531
2532 if (filter_op == RTE_ETH_FILTER_ADD) {
2533 ret = bnxt_hwrm_set_ntuple_filter(bp,
2534 filter->dst_id,
2535 filter);
2536 if (ret)
2537 goto free_filter;
2538 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2539 } else {
2540 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2541 STAILQ_REMOVE(&vnic->filter, match,
2542 bnxt_filter_info, next);
2543 bnxt_free_filter(bp, match);
2544 filter->fw_l2_filter_id = -1;
2545 bnxt_free_filter(bp, filter);
2546 }
2547 break;
2548 case RTE_ETH_FILTER_FLUSH:
2549 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2550 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2551
2552 STAILQ_FOREACH(filter, &vnic->filter, next) {
2553 if (filter->filter_type ==
2554 HWRM_CFA_NTUPLE_FILTER) {
2555 ret =
2556 bnxt_hwrm_clear_ntuple_filter(bp,
2557 filter);
2558 STAILQ_REMOVE(&vnic->filter, filter,
2559 bnxt_filter_info, next);
2560 }
2561 }
2562 }
2563 return ret;
2564 case RTE_ETH_FILTER_UPDATE:
2565 case RTE_ETH_FILTER_STATS:
2566 case RTE_ETH_FILTER_INFO:
2567 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2568 break;
2569 default:
2570 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2571 ret = -EINVAL;
2572 break;
2573 }
2574 return ret;
2575
2576free_filter:
2577 filter->fw_l2_filter_id = -1;
2578 bnxt_free_filter(bp, filter);
2579 return ret;
2580}
2581
2582static int
2583bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2584 enum rte_filter_type filter_type,
2585 enum rte_filter_op filter_op, void *arg)
2586{
2587 int ret = 0;
2588
2589 switch (filter_type) {
2590 case RTE_ETH_FILTER_TUNNEL:
2591 PMD_DRV_LOG(ERR,
2592 "filter type: %d: To be implemented\n", filter_type);
2593 break;
2594 case RTE_ETH_FILTER_FDIR:
2595 ret = bnxt_fdir_filter(dev, filter_op, arg);
2596 break;
2597 case RTE_ETH_FILTER_NTUPLE:
2598 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2599 break;
2600 case RTE_ETH_FILTER_ETHERTYPE:
2601 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2602 break;
2603 case RTE_ETH_FILTER_GENERIC:
2604 if (filter_op != RTE_ETH_FILTER_GET)
2605 return -EINVAL;
2606 *(const void **)arg = &bnxt_flow_ops;
2607 break;
2608 default:
2609 PMD_DRV_LOG(ERR,
2610 "Filter type (%d) not supported", filter_type);
2611 ret = -EINVAL;
2612 break;
2613 }
2614 return ret;
2615}
2616
2617static const uint32_t *
2618bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2619{
2620 static const uint32_t ptypes[] = {
2621 RTE_PTYPE_L2_ETHER_VLAN,
2622 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2623 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2624 RTE_PTYPE_L4_ICMP,
2625 RTE_PTYPE_L4_TCP,
2626 RTE_PTYPE_L4_UDP,
2627 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2628 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2629 RTE_PTYPE_INNER_L4_ICMP,
2630 RTE_PTYPE_INNER_L4_TCP,
2631 RTE_PTYPE_INNER_L4_UDP,
2632 RTE_PTYPE_UNKNOWN
2633 };
2634
2635 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2636 return ptypes;
2637 return NULL;
2638}
2639
2640static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2641 int reg_win)
2642{
2643 uint32_t reg_base = *reg_arr & 0xfffff000;
2644 uint32_t win_off;
2645 int i;
2646
2647 for (i = 0; i < count; i++) {
2648 if ((reg_arr[i] & 0xfffff000) != reg_base)
2649 return -ERANGE;
2650 }
2651 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2652 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2653 return 0;
2654}
2655
2656static int bnxt_map_ptp_regs(struct bnxt *bp)
2657{
2658 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2659 uint32_t *reg_arr;
2660 int rc, i;
2661
2662 reg_arr = ptp->rx_regs;
2663 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2664 if (rc)
2665 return rc;
2666
2667 reg_arr = ptp->tx_regs;
2668 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2669 if (rc)
2670 return rc;
2671
2672 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2673 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2674
2675 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2676 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2677
2678 return 0;
2679}
2680
2681static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2682{
2683 rte_write32(0, (uint8_t *)bp->bar0 +
2684 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2685 rte_write32(0, (uint8_t *)bp->bar0 +
2686 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2687}
2688
2689static uint64_t bnxt_cc_read(struct bnxt *bp)
2690{
2691 uint64_t ns;
2692
2693 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2694 BNXT_GRCPF_REG_SYNC_TIME));
2695 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2696 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2697 return ns;
2698}
2699
2700static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2701{
2702 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2703 uint32_t fifo;
2704
2705 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2706 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2707 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2708 return -EAGAIN;
2709
2710 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2711 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2712 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2713 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2714 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2715 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2716
2717 return 0;
2718}
2719
2720static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2721{
2722 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2723 struct bnxt_pf_info *pf = &bp->pf;
2724 uint16_t port_id;
2725 uint32_t fifo;
2726
2727 if (!ptp)
2728 return -ENODEV;
2729
2730 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2731 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2732 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2733 return -EAGAIN;
2734
2735 port_id = pf->port_id;
2736 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2737 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2738
2739 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2740 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2741 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2742/* bnxt_clr_rx_ts(bp); TBD */
2743 return -EBUSY;
2744 }
2745
2746 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2747 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2748 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2749 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2750
2751 return 0;
2752}
2753
2754static int
2755bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2756{
2757 uint64_t ns;
2758 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2759 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2760
2761 if (!ptp)
2762 return 0;
2763
2764 ns = rte_timespec_to_ns(ts);
2765 /* Set the timecounters to a new value. */
2766 ptp->tc.nsec = ns;
2767
2768 return 0;
2769}
2770
2771static int
2772bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2773{
2774 uint64_t ns, systime_cycles;
2775 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2776 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2777
2778 if (!ptp)
2779 return 0;
2780
2781 systime_cycles = bnxt_cc_read(bp);
2782 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2783 *ts = rte_ns_to_timespec(ns);
2784
2785 return 0;
2786}
2787static int
2788bnxt_timesync_enable(struct rte_eth_dev *dev)
2789{
2790 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2791 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2792 uint32_t shift = 0;
2793
2794 if (!ptp)
2795 return 0;
2796
2797 ptp->rx_filter = 1;
2798 ptp->tx_tstamp_en = 1;
2799 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2800
2801 if (!bnxt_hwrm_ptp_cfg(bp))
2802 bnxt_map_ptp_regs(bp);
2803
2804 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2805 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2806 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2807
2808 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2809 ptp->tc.cc_shift = shift;
2810 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2811
2812 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2813 ptp->rx_tstamp_tc.cc_shift = shift;
2814 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2815
2816 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2817 ptp->tx_tstamp_tc.cc_shift = shift;
2818 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2819
2820 return 0;
2821}
2822
2823static int
2824bnxt_timesync_disable(struct rte_eth_dev *dev)
2825{
2826 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2827 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2828
2829 if (!ptp)
2830 return 0;
2831
2832 ptp->rx_filter = 0;
2833 ptp->tx_tstamp_en = 0;
2834 ptp->rxctl = 0;
2835
2836 bnxt_hwrm_ptp_cfg(bp);
2837
2838 bnxt_unmap_ptp_regs(bp);
2839
2840 return 0;
2841}
2842
2843static int
2844bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2845 struct timespec *timestamp,
2846 uint32_t flags __rte_unused)
2847{
2848 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2849 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2850 uint64_t rx_tstamp_cycles = 0;
2851 uint64_t ns;
2852
2853 if (!ptp)
2854 return 0;
2855
2856 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2857 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2858 *timestamp = rte_ns_to_timespec(ns);
2859 return 0;
2860}
2861
2862static int
2863bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2864 struct timespec *timestamp)
2865{
2866 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2867 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2868 uint64_t tx_tstamp_cycles = 0;
2869 uint64_t ns;
2870
2871 if (!ptp)
2872 return 0;
2873
2874 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2875 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2876 *timestamp = rte_ns_to_timespec(ns);
2877
2878 return 0;
2879}
2880
2881static int
2882bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2883{
2884 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2885 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2886
2887 if (!ptp)
2888 return 0;
2889
2890 ptp->tc.nsec += delta;
2891
2892 return 0;
2893}
2894
2895static int
2896bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2897{
2898 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2899 int rc;
2900 uint32_t dir_entries;
2901 uint32_t entry_length;
2902
2903 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2904 bp->pdev->addr.domain, bp->pdev->addr.bus,
2905 bp->pdev->addr.devid, bp->pdev->addr.function);
2906
2907 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2908 if (rc != 0)
2909 return rc;
2910
2911 return dir_entries * entry_length;
2912}
2913
2914static int
2915bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2916 struct rte_dev_eeprom_info *in_eeprom)
2917{
2918 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2919 uint32_t index;
2920 uint32_t offset;
2921
2922 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2923 "len = %d\n", bp->pdev->addr.domain,
2924 bp->pdev->addr.bus, bp->pdev->addr.devid,
2925 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2926
2927 if (in_eeprom->offset == 0) /* special offset value to get directory */
2928 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2929 in_eeprom->data);
2930
2931 index = in_eeprom->offset >> 24;
2932 offset = in_eeprom->offset & 0xffffff;
2933
2934 if (index != 0)
2935 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2936 in_eeprom->length, in_eeprom->data);
2937
2938 return 0;
2939}
2940
2941static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2942{
2943 switch (dir_type) {
2944 case BNX_DIR_TYPE_CHIMP_PATCH:
2945 case BNX_DIR_TYPE_BOOTCODE:
2946 case BNX_DIR_TYPE_BOOTCODE_2:
2947 case BNX_DIR_TYPE_APE_FW:
2948 case BNX_DIR_TYPE_APE_PATCH:
2949 case BNX_DIR_TYPE_KONG_FW:
2950 case BNX_DIR_TYPE_KONG_PATCH:
2951 case BNX_DIR_TYPE_BONO_FW:
2952 case BNX_DIR_TYPE_BONO_PATCH:
2953 /* FALLTHROUGH */
2954 return true;
2955 }
2956
2957 return false;
2958}
2959
2960static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2961{
2962 switch (dir_type) {
2963 case BNX_DIR_TYPE_AVS:
2964 case BNX_DIR_TYPE_EXP_ROM_MBA:
2965 case BNX_DIR_TYPE_PCIE:
2966 case BNX_DIR_TYPE_TSCF_UCODE:
2967 case BNX_DIR_TYPE_EXT_PHY:
2968 case BNX_DIR_TYPE_CCM:
2969 case BNX_DIR_TYPE_ISCSI_BOOT:
2970 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2971 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2972 /* FALLTHROUGH */
2973 return true;
2974 }
2975
2976 return false;
2977}
2978
2979static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2980{
2981 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2982 bnxt_dir_type_is_other_exec_format(dir_type);
2983}
2984
2985static int
2986bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2987 struct rte_dev_eeprom_info *in_eeprom)
2988{
2989 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2990 uint8_t index, dir_op;
2991 uint16_t type, ext, ordinal, attr;
2992
2993 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2994 "len = %d\n", bp->pdev->addr.domain,
2995 bp->pdev->addr.bus, bp->pdev->addr.devid,
2996 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2997
2998 if (!BNXT_PF(bp)) {
2999 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3000 return -EINVAL;
3001 }
3002
3003 type = in_eeprom->magic >> 16;
3004
3005 if (type == 0xffff) { /* special value for directory operations */
3006 index = in_eeprom->magic & 0xff;
3007 dir_op = in_eeprom->magic >> 8;
3008 if (index == 0)
3009 return -EINVAL;
3010 switch (dir_op) {
3011 case 0x0e: /* erase */
3012 if (in_eeprom->offset != ~in_eeprom->magic)
3013 return -EINVAL;
3014 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3015 default:
3016 return -EINVAL;
3017 }
3018 }
3019
3020 /* Create or re-write an NVM item: */
3021 if (bnxt_dir_type_is_executable(type) == true)
3022 return -EOPNOTSUPP;
3023 ext = in_eeprom->magic & 0xffff;
3024 ordinal = in_eeprom->offset >> 16;
3025 attr = in_eeprom->offset & 0xffff;
3026
3027 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3028 in_eeprom->data, in_eeprom->length);
3029 return 0;
3030}
3031
3032/*
3033 * Initialization
3034 */
3035
3036static const struct eth_dev_ops bnxt_dev_ops = {
3037 .dev_infos_get = bnxt_dev_info_get_op,
3038 .dev_close = bnxt_dev_close_op,
3039 .dev_configure = bnxt_dev_configure_op,
3040 .dev_start = bnxt_dev_start_op,
3041 .dev_stop = bnxt_dev_stop_op,
3042 .dev_set_link_up = bnxt_dev_set_link_up_op,
3043 .dev_set_link_down = bnxt_dev_set_link_down_op,
3044 .stats_get = bnxt_stats_get_op,
3045 .stats_reset = bnxt_stats_reset_op,
3046 .rx_queue_setup = bnxt_rx_queue_setup_op,
3047 .rx_queue_release = bnxt_rx_queue_release_op,
3048 .tx_queue_setup = bnxt_tx_queue_setup_op,
3049 .tx_queue_release = bnxt_tx_queue_release_op,
3050 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3051 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3052 .reta_update = bnxt_reta_update_op,
3053 .reta_query = bnxt_reta_query_op,
3054 .rss_hash_update = bnxt_rss_hash_update_op,
3055 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3056 .link_update = bnxt_link_update_op,
3057 .promiscuous_enable = bnxt_promiscuous_enable_op,
3058 .promiscuous_disable = bnxt_promiscuous_disable_op,
3059 .allmulticast_enable = bnxt_allmulticast_enable_op,
3060 .allmulticast_disable = bnxt_allmulticast_disable_op,
3061 .mac_addr_add = bnxt_mac_addr_add_op,
3062 .mac_addr_remove = bnxt_mac_addr_remove_op,
3063 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3064 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3065 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3066 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3067 .vlan_filter_set = bnxt_vlan_filter_set_op,
3068 .vlan_offload_set = bnxt_vlan_offload_set_op,
3069 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3070 .mtu_set = bnxt_mtu_set_op,
3071 .mac_addr_set = bnxt_set_default_mac_addr_op,
3072 .xstats_get = bnxt_dev_xstats_get_op,
3073 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3074 .xstats_reset = bnxt_dev_xstats_reset_op,
3075 .fw_version_get = bnxt_fw_version_get,
3076 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3077 .rxq_info_get = bnxt_rxq_info_get_op,
3078 .txq_info_get = bnxt_txq_info_get_op,
3079 .dev_led_on = bnxt_dev_led_on_op,
3080 .dev_led_off = bnxt_dev_led_off_op,
3081 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3082 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3083 .rx_queue_count = bnxt_rx_queue_count_op,
3084 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3085 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3086 .rx_queue_start = bnxt_rx_queue_start,
3087 .rx_queue_stop = bnxt_rx_queue_stop,
3088 .tx_queue_start = bnxt_tx_queue_start,
3089 .tx_queue_stop = bnxt_tx_queue_stop,
3090 .filter_ctrl = bnxt_filter_ctrl_op,
3091 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3092 .get_eeprom_length = bnxt_get_eeprom_length_op,
3093 .get_eeprom = bnxt_get_eeprom_op,
3094 .set_eeprom = bnxt_set_eeprom_op,
3095 .timesync_enable = bnxt_timesync_enable,
3096 .timesync_disable = bnxt_timesync_disable,
3097 .timesync_read_time = bnxt_timesync_read_time,
3098 .timesync_write_time = bnxt_timesync_write_time,
3099 .timesync_adjust_time = bnxt_timesync_adjust_time,
3100 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3101 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3102};
3103
3104static bool bnxt_vf_pciid(uint16_t id)
3105{
3106 if (id == BROADCOM_DEV_ID_57304_VF ||
3107 id == BROADCOM_DEV_ID_57406_VF ||
3108 id == BROADCOM_DEV_ID_5731X_VF ||
3109 id == BROADCOM_DEV_ID_5741X_VF ||
3110 id == BROADCOM_DEV_ID_57414_VF ||
3111 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3112 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3113 id == BROADCOM_DEV_ID_58802_VF)
3114 return true;
3115 return false;
3116}
3117
3118bool bnxt_stratus_device(struct bnxt *bp)
3119{
3120 uint16_t id = bp->pdev->id.device_id;
3121
3122 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3123 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3124 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3125 return true;
3126 return false;
3127}
3128
3129static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3130{
3131 struct bnxt *bp = eth_dev->data->dev_private;
3132 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3133 int rc;
3134
3135 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3136 if (!pci_dev->mem_resource[0].addr) {
3137 PMD_DRV_LOG(ERR,
3138 "Cannot find PCI device base address, aborting\n");
3139 rc = -ENODEV;
3140 goto init_err_disable;
3141 }
3142
3143 bp->eth_dev = eth_dev;
3144 bp->pdev = pci_dev;
3145
3146 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3147 if (!bp->bar0) {
3148 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3149 rc = -ENOMEM;
3150 goto init_err_release;
3151 }
3152
3153 if (!pci_dev->mem_resource[2].addr) {
3154 PMD_DRV_LOG(ERR,
3155 "Cannot find PCI device BAR 2 address, aborting\n");
3156 rc = -ENODEV;
3157 goto init_err_release;
3158 } else {
3159 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3160 }
3161
3162 return 0;
3163
3164init_err_release:
3165 if (bp->bar0)
3166 bp->bar0 = NULL;
3167 if (bp->doorbell_base)
3168 bp->doorbell_base = NULL;
3169
3170init_err_disable:
3171
3172 return rc;
3173}
3174
3175
3176#define ALLOW_FUNC(x) \
3177 { \
3178 typeof(x) arg = (x); \
3179 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3180 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3181 }
3182static int
3183bnxt_dev_init(struct rte_eth_dev *eth_dev)
3184{
3185 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3186 char mz_name[RTE_MEMZONE_NAMESIZE];
3187 const struct rte_memzone *mz = NULL;
3188 static int version_printed;
3189 uint32_t total_alloc_len;
3190 rte_iova_t mz_phys_addr;
3191 struct bnxt *bp;
3192 int rc;
3193
3194 if (version_printed++ == 0)
3195 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3196
3197 rte_eth_copy_pci_info(eth_dev, pci_dev);
3198
3199 bp = eth_dev->data->dev_private;
3200
3201 bp->dev_stopped = 1;
3202
3203 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3204 goto skip_init;
3205
3206 if (bnxt_vf_pciid(pci_dev->id.device_id))
7c673cae
FG		 3207 bp->flags |= BNXT_FLAG_VF;
3208
3209 rc = bnxt_init_board(eth_dev);
3210 if (rc) {
9f95a23c 3211 PMD_DRV_LOG(ERR,
7c673cae
FG		 3212 "Board initialization failed rc: %x\n", rc);
3213 goto error;
3214 }
9f95a23c 3215skip_init:
7c673cae
FG		 3216 eth_dev->dev_ops = &bnxt_dev_ops;
3217 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3218 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
9f95a23c
TL		 3219 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3220 return 0;
3221
3222 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3223 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3224 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3225 pci_dev->addr.bus, pci_dev->addr.devid,
3226 pci_dev->addr.function, "rx_port_stats");
3227 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3228 mz = rte_memzone_lookup(mz_name);
3229 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3230 sizeof(struct rx_port_stats) +
3231 sizeof(struct rx_port_stats_ext) +
3232 512);
3233 if (!mz) {
3234 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3235 SOCKET_ID_ANY,
3236 RTE_MEMZONE_2MB |
3237 RTE_MEMZONE_SIZE_HINT_ONLY |
3238 RTE_MEMZONE_IOVA_CONTIG);
3239 if (mz == NULL)
3240 return -ENOMEM;
3241 }
3242 memset(mz->addr, 0, mz->len);
3243 mz_phys_addr = mz->iova;
3244 if ((unsigned long)mz->addr == mz_phys_addr) {
3245 PMD_DRV_LOG(INFO,
3246 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3247 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3248 if (mz_phys_addr == 0) {
3249 PMD_DRV_LOG(ERR,
3250 "unable to map address to physical memory\n");
3251 return -ENOMEM;
3252 }
3253 }
3254
3255 bp->rx_mem_zone = (const void *)mz;
3256 bp->hw_rx_port_stats = mz->addr;
3257 bp->hw_rx_port_stats_map = mz_phys_addr;
3258
3259 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3260 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3261 pci_dev->addr.bus, pci_dev->addr.devid,
3262 pci_dev->addr.function, "tx_port_stats");
3263 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3264 mz = rte_memzone_lookup(mz_name);
3265 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3266 sizeof(struct tx_port_stats) +
3267 sizeof(struct tx_port_stats_ext) +
3268 512);
3269 if (!mz) {
3270 mz = rte_memzone_reserve(mz_name,
3271 total_alloc_len,
3272 SOCKET_ID_ANY,
3273 RTE_MEMZONE_2MB |
3274 RTE_MEMZONE_SIZE_HINT_ONLY |
3275 RTE_MEMZONE_IOVA_CONTIG);
3276 if (mz == NULL)
3277 return -ENOMEM;
3278 }
3279 memset(mz->addr, 0, mz->len);
3280 mz_phys_addr = mz->iova;
3281 if ((unsigned long)mz->addr == mz_phys_addr) {
3282 PMD_DRV_LOG(WARNING,
3283 "Memzone physical address same as virtual.\n");
3284 PMD_DRV_LOG(WARNING,
3285 "Using rte_mem_virt2iova()\n");
3286 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3287 if (mz_phys_addr == 0) {
3288 PMD_DRV_LOG(ERR,
3289 "unable to map address to physical memory\n");
3290 return -ENOMEM;
3291 }
3292 }
3293
3294 bp->tx_mem_zone = (const void *)mz;
3295 bp->hw_tx_port_stats = mz->addr;
3296 bp->hw_tx_port_stats_map = mz_phys_addr;
3297
3298 bp->flags |= BNXT_FLAG_PORT_STATS;
3299
3300 /* Display extended statistics if FW supports it */
3301 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3302 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3303 goto skip_ext_stats;
3304
3305 bp->hw_rx_port_stats_ext = (void *)
3306 (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3307 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3308 sizeof(struct rx_port_stats);
3309 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3310
3311
3312 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3313 bp->hw_tx_port_stats_ext = (void *)
3314 (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3315 bp->hw_tx_port_stats_ext_map =
3316 bp->hw_tx_port_stats_map +
3317 sizeof(struct tx_port_stats);
3318 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3319 }
3320 }
7c673cae 3321
9f95a23c 3322skip_ext_stats:
7c673cae
FG		 3323 rc = bnxt_alloc_hwrm_resources(bp);
3324 if (rc) {
9f95a23c 3325 PMD_DRV_LOG(ERR,
7c673cae
FG		 3326 "hwrm resource allocation failure rc: %x\n", rc);
3327 goto error_free;
3328 }
3329 rc = bnxt_hwrm_ver_get(bp);
3330 if (rc)
3331 goto error_free;
9f95a23c
TL		 3332 rc = bnxt_hwrm_queue_qportcfg(bp);
3333 if (rc) {
3334 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3335 goto error_free;
3336 }
7c673cae 3337
9f95a23c
TL		 3338 rc = bnxt_hwrm_func_qcfg(bp);
3339 if (rc) {
3340 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3341 goto error_free;
3342 }
7c673cae
FG		 3343
3344 /* Get the MAX capabilities for this function */
3345 rc = bnxt_hwrm_func_qcaps(bp);
3346 if (rc) {
9f95a23c
TL		 3347 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3348 goto error_free;
3349 }
3350 if (bp->max_tx_rings == 0) {
3351 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3352 rc = -EBUSY;
7c673cae
FG		 3353 goto error_free;
3354 }
3355 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
9f95a23c 3356 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
7c673cae 3357 if (eth_dev->data->mac_addrs == NULL) {
9f95a23c 3358 PMD_DRV_LOG(ERR,
7c673cae 3359 "Failed to alloc %u bytes needed to store MAC addr tbl",
9f95a23c 3360 ETHER_ADDR_LEN * bp->max_l2_ctx);
7c673cae
FG		 3361 rc = -ENOMEM;
3362 goto error_free;
3363 }
9f95a23c
TL		 3364
3365 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3366 PMD_DRV_LOG(ERR,
3367 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3368 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3369 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3370 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3371 rc = -EINVAL;
3372 goto error_free;
3373 }
7c673cae 3374 /* Copy the permanent MAC from the qcap response address now. */
9f95a23c 3375 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
7c673cae 3376 memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
9f95a23c
TL		 3377
3378 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3379 /* 1 ring is for default completion ring */
3380 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3381 rc = -ENOSPC;
3382 goto error_free;
3383 }
3384
7c673cae
FG		 3385 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3386 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3387 if (!bp->grp_info) {
9f95a23c
TL		 3388 PMD_DRV_LOG(ERR,
3389 "Failed to alloc %zu bytes to store group info table\n",
7c673cae
FG		 3390 sizeof(*bp->grp_info) * bp->max_ring_grps);
3391 rc = -ENOMEM;
3392 goto error_free;
3393 }
3394
9f95a23c
TL		 3395 /* Forward all requests if firmware is new enough */
3396 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3397 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3398 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3399 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3400 } else {
3401 PMD_DRV_LOG(WARNING,
3402 "Firmware too old for VF mailbox functionality\n");
3403 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3404 }
3405
3406 /*
3407 * The following are used for driver cleanup. If we disallow these,
3408 * VF drivers can't clean up cleanly.
3409 */
3410 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3411 ALLOW_FUNC(HWRM_VNIC_FREE);
3412 ALLOW_FUNC(HWRM_RING_FREE);
3413 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3414 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3415 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3416 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3417 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3418 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3419 rc = bnxt_hwrm_func_driver_register(bp);
7c673cae 3420 if (rc) {
9f95a23c 3421 PMD_DRV_LOG(ERR,
7c673cae
FG		 3422 "Failed to register driver");
3423 rc = -EBUSY;
3424 goto error_free;
3425 }
3426
9f95a23c 3427 PMD_DRV_LOG(INFO,
7c673cae 3428 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
11fdf7f2
TL		 3429 pci_dev->mem_resource[0].phys_addr,
3430 pci_dev->mem_resource[0].addr);
7c673cae 3431
9f95a23c
TL		 3432 rc = bnxt_hwrm_func_reset(bp);
3433 if (rc) {
3434 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3435 rc = -EIO;
3436 goto error_free;
3437 }
3438
3439 if (BNXT_PF(bp)) {
3440 //if (bp->pf.active_vfs) {
3441 // TODO: Deallocate VF resources?
3442 //}
3443 if (bp->pdev->max_vfs) {
3444 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3445 if (rc) {
3446 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3447 goto error_free;
3448 }
3449 } else {
3450 rc = bnxt_hwrm_allocate_pf_only(bp);
3451 if (rc) {
3452 PMD_DRV_LOG(ERR,
3453 "Failed to allocate PF resources\n");
3454 goto error_free;
3455 }
3456 }
3457 }
3458
3459 bnxt_hwrm_port_led_qcaps(bp);
3460
3461 rc = bnxt_setup_int(bp);
3462 if (rc)
3463 goto error_free;
3464
3465 rc = bnxt_alloc_mem(bp);
3466 if (rc)
3467 goto error_free_int;
3468
3469 rc = bnxt_request_int(bp);
3470 if (rc)
3471 goto error_free_int;
3472
3473 bnxt_enable_int(bp);
3474 bnxt_init_nic(bp);
7c673cae
FG		 3475
3476 return 0;
3477
9f95a23c
TL		 3478error_free_int:
3479 bnxt_disable_int(bp);
3480 bnxt_hwrm_func_buf_unrgtr(bp);
3481 bnxt_free_int(bp);
3482 bnxt_free_mem(bp);
7c673cae 3483error_free:
11fdf7f2 3484 bnxt_dev_uninit(eth_dev);
7c673cae
FG		 3485error:
3486 return rc;
3487}
3488
3489static int
9f95a23c
TL		 3490bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3491{
7c673cae
FG		 3492 struct bnxt *bp = eth_dev->data->dev_private;
3493 int rc;
3494
9f95a23c
TL		 3495 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3496 return -EPERM;
3497
3498 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3499 bnxt_disable_int(bp);
3500 bnxt_free_int(bp);
3501 bnxt_free_mem(bp);
7c673cae
FG		 3502 if (bp->grp_info != NULL) {
3503 rte_free(bp->grp_info);
3504 bp->grp_info = NULL;
3505 }
3506 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3507 bnxt_free_hwrm_resources(bp);
9f95a23c
TL		 3508
3509 if (bp->tx_mem_zone) {
3510 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3511 bp->tx_mem_zone = NULL;
3512 }
3513
3514 if (bp->rx_mem_zone) {
3515 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3516 bp->rx_mem_zone = NULL;
3517 }
3518
7c673cae
FG		 3519 if (bp->dev_stopped == 0)
3520 bnxt_dev_close_op(eth_dev);
9f95a23c
TL		 3521 if (bp->pf.vf_info)
3522 rte_free(bp->pf.vf_info);
7c673cae
FG		 3523 eth_dev->dev_ops = NULL;
3524 eth_dev->rx_pkt_burst = NULL;
3525 eth_dev->tx_pkt_burst = NULL;
3526
3527 return rc;
3528}
3529
11fdf7f2
TL		 3530static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3531 struct rte_pci_device *pci_dev)
3532{
3533 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3534 bnxt_dev_init);
3535}
3536
3537static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3538{
9f95a23c
TL		 3539 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3540 return rte_eth_dev_pci_generic_remove(pci_dev,
3541 bnxt_dev_uninit);
3542 else
3543 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
11fdf7f2
TL		 3544}
3545
3546static struct rte_pci_driver bnxt_rte_pmd = {
3547 .id_table = bnxt_pci_id_map,
3548 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
9f95a23c 3549 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
11fdf7f2
TL		 3550 .probe = bnxt_pci_probe,
3551 .remove = bnxt_pci_remove,
7c673cae
FG		 3552};
3553
9f95a23c
TL		 3554static bool
3555is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3556{
3557 if (strcmp(dev->device->driver->name, drv->driver.name))
3558 return false;
3559
3560 return true;
3561}
3562
3563bool is_bnxt_supported(struct rte_eth_dev *dev)
3564{
3565 return is_device_supported(dev, &bnxt_rte_pmd);
3566}
3567
3568RTE_INIT(bnxt_init_log)
3569{
3570 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
3571 if (bnxt_logtype_driver >= 0)
3572 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
3573}
3574
11fdf7f2 3575RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
7c673cae 3576RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
9f95a23c 3577RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");
Ceph