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7c673cae FG |
1 | /*- |
2 | * BSD LICENSE | |
3 | * | |
4 | * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * | |
11 | * * Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * * Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in | |
15 | * the documentation and/or other materials provided with the | |
16 | * distribution. | |
17 | * * Neither the name of copyright holder nor the names of its | |
18 | * contributors may be used to endorse or promote products derived | |
19 | * from this software without specific prior written permission. | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
22 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
23 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
24 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
25 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
26 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
27 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
28 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
29 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | */ | |
33 | ||
34 | #ifndef ENA_COM | |
35 | #define ENA_COM | |
36 | ||
37 | #include "ena_plat.h" | |
9f95a23c | 38 | #include "ena_includes.h" |
7c673cae FG |
39 | |
40 | #define ENA_MAX_NUM_IO_QUEUES 128U | |
41 | /* We need to queues for each IO (on for Tx and one for Rx) */ | |
42 | #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) | |
43 | ||
44 | #define ENA_MAX_HANDLERS 256 | |
45 | ||
46 | #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48 | |
47 | ||
48 | /* Unit in usec */ | |
49 | #define ENA_REG_READ_TIMEOUT 200000 | |
50 | ||
51 | #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry)) | |
52 | #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) | |
53 | #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) | |
54 | ||
55 | /*****************************************************************************/ | |
56 | /*****************************************************************************/ | |
57 | /* ENA adaptive interrupt moderation settings */ | |
58 | ||
59 | #define ENA_INTR_LOWEST_USECS (0) | |
60 | #define ENA_INTR_LOWEST_PKTS (3) | |
61 | #define ENA_INTR_LOWEST_BYTES (2 * 1524) | |
62 | ||
63 | #define ENA_INTR_LOW_USECS (32) | |
64 | #define ENA_INTR_LOW_PKTS (12) | |
65 | #define ENA_INTR_LOW_BYTES (16 * 1024) | |
66 | ||
67 | #define ENA_INTR_MID_USECS (80) | |
68 | #define ENA_INTR_MID_PKTS (48) | |
69 | #define ENA_INTR_MID_BYTES (64 * 1024) | |
70 | ||
71 | #define ENA_INTR_HIGH_USECS (128) | |
72 | #define ENA_INTR_HIGH_PKTS (96) | |
73 | #define ENA_INTR_HIGH_BYTES (128 * 1024) | |
74 | ||
75 | #define ENA_INTR_HIGHEST_USECS (192) | |
76 | #define ENA_INTR_HIGHEST_PKTS (128) | |
77 | #define ENA_INTR_HIGHEST_BYTES (192 * 1024) | |
78 | ||
79 | #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 196 | |
80 | #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4 | |
81 | #define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6 | |
82 | #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4 | |
9f95a23c TL |
83 | #define ENA_INTR_MODER_LEVEL_STRIDE 1 |
84 | #define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF | |
85 | ||
86 | #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF | |
87 | ||
88 | #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 | |
7c673cae FG |
89 | |
90 | enum ena_intr_moder_level { | |
91 | ENA_INTR_MODER_LOWEST = 0, | |
92 | ENA_INTR_MODER_LOW, | |
93 | ENA_INTR_MODER_MID, | |
94 | ENA_INTR_MODER_HIGH, | |
95 | ENA_INTR_MODER_HIGHEST, | |
96 | ENA_INTR_MAX_NUM_OF_LEVELS, | |
97 | }; | |
98 | ||
9f95a23c TL |
99 | struct ena_llq_configurations { |
100 | enum ena_admin_llq_header_location llq_header_location; | |
101 | enum ena_admin_llq_ring_entry_size llq_ring_entry_size; | |
102 | enum ena_admin_llq_stride_ctrl llq_stride_ctrl; | |
103 | enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header; | |
104 | u16 llq_ring_entry_size_value; | |
105 | }; | |
106 | ||
7c673cae FG |
107 | struct ena_intr_moder_entry { |
108 | unsigned int intr_moder_interval; | |
109 | unsigned int pkts_per_interval; | |
110 | unsigned int bytes_per_interval; | |
111 | }; | |
112 | ||
113 | enum queue_direction { | |
114 | ENA_COM_IO_QUEUE_DIRECTION_TX, | |
115 | ENA_COM_IO_QUEUE_DIRECTION_RX | |
116 | }; | |
117 | ||
118 | struct ena_com_buf { | |
119 | dma_addr_t paddr; /**< Buffer physical address */ | |
120 | u16 len; /**< Buffer length in bytes */ | |
121 | }; | |
122 | ||
123 | struct ena_com_rx_buf_info { | |
124 | u16 len; | |
125 | u16 req_id; | |
126 | }; | |
127 | ||
128 | struct ena_com_io_desc_addr { | |
9f95a23c TL |
129 | u8 __iomem *pbuf_dev_addr; /* LLQ address */ |
130 | u8 *virt_addr; | |
7c673cae FG |
131 | dma_addr_t phys_addr; |
132 | ena_mem_handle_t mem_handle; | |
133 | }; | |
134 | ||
135 | struct ena_com_tx_meta { | |
136 | u16 mss; | |
137 | u16 l3_hdr_len; | |
138 | u16 l3_hdr_offset; | |
7c673cae FG |
139 | u16 l4_hdr_len; /* In words */ |
140 | }; | |
141 | ||
9f95a23c TL |
142 | struct ena_com_llq_info { |
143 | bool inline_header; | |
144 | u16 header_location_ctrl; | |
145 | u16 desc_stride_ctrl; | |
146 | u16 desc_list_entry_size_ctrl; | |
147 | u16 desc_list_entry_size; | |
148 | u16 descs_num_before_header; | |
149 | u16 descs_per_entry; | |
150 | u16 max_entries_in_tx_burst; | |
151 | }; | |
152 | ||
7c673cae FG |
153 | struct ena_com_io_cq { |
154 | struct ena_com_io_desc_addr cdesc_addr; | |
9f95a23c | 155 | void *bus; |
7c673cae FG |
156 | |
157 | /* Interrupt unmask register */ | |
158 | u32 __iomem *unmask_reg; | |
159 | ||
160 | /* The completion queue head doorbell register */ | |
161 | u32 __iomem *cq_head_db_reg; | |
162 | ||
163 | /* numa configuration register (for TPH) */ | |
164 | u32 __iomem *numa_node_cfg_reg; | |
165 | ||
166 | /* The value to write to the above register to unmask | |
167 | * the interrupt of this queue | |
168 | */ | |
169 | u32 msix_vector; | |
170 | ||
171 | enum queue_direction direction; | |
172 | ||
173 | /* holds the number of cdesc of the current packet */ | |
174 | u16 cur_rx_pkt_cdesc_count; | |
175 | /* save the firt cdesc idx of the current packet */ | |
176 | u16 cur_rx_pkt_cdesc_start_idx; | |
177 | ||
178 | u16 q_depth; | |
179 | /* Caller qid */ | |
180 | u16 qid; | |
181 | ||
182 | /* Device queue index */ | |
183 | u16 idx; | |
184 | u16 head; | |
185 | u16 last_head_update; | |
186 | u8 phase; | |
187 | u8 cdesc_entry_size_in_bytes; | |
188 | ||
189 | } ____cacheline_aligned; | |
190 | ||
9f95a23c TL |
191 | struct ena_com_io_bounce_buffer_control { |
192 | u8 *base_buffer; | |
193 | u16 next_to_use; | |
194 | u16 buffer_size; | |
195 | u16 buffers_num; /* Must be a power of 2 */ | |
196 | }; | |
197 | ||
198 | /* This struct is to keep tracking the current location of the next llq entry */ | |
199 | struct ena_com_llq_pkt_ctrl { | |
200 | u8 *curr_bounce_buf; | |
201 | u16 idx; | |
202 | u16 descs_left_in_line; | |
203 | }; | |
204 | ||
7c673cae FG |
205 | struct ena_com_io_sq { |
206 | struct ena_com_io_desc_addr desc_addr; | |
9f95a23c | 207 | void *bus; |
7c673cae FG |
208 | |
209 | u32 __iomem *db_addr; | |
210 | u8 __iomem *header_addr; | |
211 | ||
212 | enum queue_direction direction; | |
213 | enum ena_admin_placement_policy_type mem_queue_type; | |
214 | ||
215 | u32 msix_vector; | |
216 | struct ena_com_tx_meta cached_tx_meta; | |
9f95a23c TL |
217 | struct ena_com_llq_info llq_info; |
218 | struct ena_com_llq_pkt_ctrl llq_buf_ctrl; | |
219 | struct ena_com_io_bounce_buffer_control bounce_buf_ctrl; | |
7c673cae FG |
220 | |
221 | u16 q_depth; | |
222 | u16 qid; | |
223 | ||
224 | u16 idx; | |
225 | u16 tail; | |
226 | u16 next_to_comp; | |
9f95a23c | 227 | u16 llq_last_copy_tail; |
7c673cae FG |
228 | u32 tx_max_header_size; |
229 | u8 phase; | |
230 | u8 desc_entry_size; | |
231 | u8 dma_addr_bits; | |
9f95a23c | 232 | u16 entries_in_tx_burst_left; |
7c673cae FG |
233 | } ____cacheline_aligned; |
234 | ||
235 | struct ena_com_admin_cq { | |
236 | struct ena_admin_acq_entry *entries; | |
237 | ena_mem_handle_t mem_handle; | |
238 | dma_addr_t dma_addr; | |
239 | ||
240 | u16 head; | |
241 | u8 phase; | |
242 | }; | |
243 | ||
244 | struct ena_com_admin_sq { | |
245 | struct ena_admin_aq_entry *entries; | |
246 | ena_mem_handle_t mem_handle; | |
247 | dma_addr_t dma_addr; | |
248 | ||
249 | u32 __iomem *db_addr; | |
250 | ||
251 | u16 head; | |
252 | u16 tail; | |
253 | u8 phase; | |
254 | ||
255 | }; | |
256 | ||
257 | struct ena_com_stats_admin { | |
258 | u32 aborted_cmd; | |
259 | u32 submitted_cmd; | |
260 | u32 completed_cmd; | |
261 | u32 out_of_space; | |
262 | u32 no_completion; | |
263 | }; | |
264 | ||
265 | struct ena_com_admin_queue { | |
266 | void *q_dmadev; | |
9f95a23c | 267 | void *bus; |
7c673cae | 268 | ena_spinlock_t q_lock; /* spinlock for the admin queue */ |
9f95a23c | 269 | |
7c673cae | 270 | struct ena_comp_ctx *comp_ctx; |
9f95a23c | 271 | u32 completion_timeout; |
7c673cae FG |
272 | u16 q_depth; |
273 | struct ena_com_admin_cq cq; | |
274 | struct ena_com_admin_sq sq; | |
275 | ||
276 | /* Indicate if the admin queue should poll for completion */ | |
277 | bool polling; | |
278 | ||
279 | u16 curr_cmd_id; | |
280 | ||
281 | /* Indicate that the ena was initialized and can | |
282 | * process new admin commands | |
283 | */ | |
284 | bool running_state; | |
285 | ||
286 | /* Count the number of outstanding admin commands */ | |
287 | ena_atomic32_t outstanding_cmds; | |
288 | ||
289 | struct ena_com_stats_admin stats; | |
290 | }; | |
291 | ||
292 | struct ena_aenq_handlers; | |
293 | ||
294 | struct ena_com_aenq { | |
295 | u16 head; | |
296 | u8 phase; | |
297 | struct ena_admin_aenq_entry *entries; | |
298 | dma_addr_t dma_addr; | |
299 | ena_mem_handle_t mem_handle; | |
300 | u16 q_depth; | |
301 | struct ena_aenq_handlers *aenq_handlers; | |
302 | }; | |
303 | ||
304 | struct ena_com_mmio_read { | |
305 | struct ena_admin_ena_mmio_req_read_less_resp *read_resp; | |
306 | dma_addr_t read_resp_dma_addr; | |
307 | ena_mem_handle_t read_resp_mem_handle; | |
9f95a23c | 308 | u32 reg_read_to; /* in us */ |
7c673cae FG |
309 | u16 seq_num; |
310 | bool readless_supported; | |
311 | /* spin lock to ensure a single outstanding read */ | |
312 | ena_spinlock_t lock; | |
313 | }; | |
314 | ||
315 | struct ena_rss { | |
316 | /* Indirect table */ | |
317 | u16 *host_rss_ind_tbl; | |
318 | struct ena_admin_rss_ind_table_entry *rss_ind_tbl; | |
319 | dma_addr_t rss_ind_tbl_dma_addr; | |
320 | ena_mem_handle_t rss_ind_tbl_mem_handle; | |
321 | u16 tbl_log_size; | |
322 | ||
323 | /* Hash key */ | |
324 | enum ena_admin_hash_functions hash_func; | |
325 | struct ena_admin_feature_rss_flow_hash_control *hash_key; | |
326 | dma_addr_t hash_key_dma_addr; | |
327 | ena_mem_handle_t hash_key_mem_handle; | |
328 | u32 hash_init_val; | |
329 | ||
330 | /* Flow Control */ | |
331 | struct ena_admin_feature_rss_hash_control *hash_ctrl; | |
332 | dma_addr_t hash_ctrl_dma_addr; | |
333 | ena_mem_handle_t hash_ctrl_mem_handle; | |
334 | ||
335 | }; | |
336 | ||
337 | struct ena_host_attribute { | |
338 | /* Debug area */ | |
339 | u8 *debug_area_virt_addr; | |
340 | dma_addr_t debug_area_dma_addr; | |
341 | ena_mem_handle_t debug_area_dma_handle; | |
342 | u32 debug_area_size; | |
343 | ||
344 | /* Host information */ | |
345 | struct ena_admin_host_info *host_info; | |
346 | dma_addr_t host_info_dma_addr; | |
347 | ena_mem_handle_t host_info_dma_handle; | |
348 | }; | |
349 | ||
9f95a23c TL |
350 | struct ena_extra_properties_strings { |
351 | u8 *virt_addr; | |
352 | dma_addr_t dma_addr; | |
353 | ena_mem_handle_t dma_handle; | |
354 | u32 size; | |
355 | }; | |
356 | ||
7c673cae FG |
357 | /* Each ena_dev is a PCI function. */ |
358 | struct ena_com_dev { | |
359 | struct ena_com_admin_queue admin_queue; | |
360 | struct ena_com_aenq aenq; | |
361 | struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES]; | |
362 | struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES]; | |
363 | u8 __iomem *reg_bar; | |
364 | void __iomem *mem_bar; | |
365 | void *dmadev; | |
9f95a23c | 366 | void *bus; |
7c673cae FG |
367 | |
368 | enum ena_admin_placement_policy_type tx_mem_queue_type; | |
369 | u32 tx_max_header_size; | |
370 | u16 stats_func; /* Selected function for extended statistic dump */ | |
371 | u16 stats_queue; /* Selected queue for extended statistic dump */ | |
372 | ||
373 | struct ena_com_mmio_read mmio_read; | |
374 | ||
375 | struct ena_rss rss; | |
376 | u32 supported_features; | |
377 | u32 dma_addr_bits; | |
378 | ||
379 | struct ena_host_attribute host_attr; | |
380 | bool adaptive_coalescing; | |
381 | u16 intr_delay_resolution; | |
382 | u32 intr_moder_tx_interval; | |
383 | struct ena_intr_moder_entry *intr_moder_tbl; | |
9f95a23c TL |
384 | |
385 | struct ena_com_llq_info llq_info; | |
386 | struct ena_extra_properties_strings extra_properties_strings; | |
7c673cae FG |
387 | }; |
388 | ||
389 | struct ena_com_dev_get_features_ctx { | |
390 | struct ena_admin_queue_feature_desc max_queues; | |
9f95a23c | 391 | struct ena_admin_queue_ext_feature_desc max_queue_ext; |
7c673cae FG |
392 | struct ena_admin_device_attr_feature_desc dev_attr; |
393 | struct ena_admin_feature_aenq_desc aenq; | |
394 | struct ena_admin_feature_offload_desc offload; | |
9f95a23c TL |
395 | struct ena_admin_ena_hw_hints hw_hints; |
396 | struct ena_admin_feature_llq_desc llq; | |
397 | struct ena_admin_feature_rss_ind_table ind_table; | |
7c673cae FG |
398 | }; |
399 | ||
400 | struct ena_com_create_io_ctx { | |
401 | enum ena_admin_placement_policy_type mem_queue_type; | |
402 | enum queue_direction direction; | |
403 | int numa_node; | |
404 | u32 msix_vector; | |
405 | u16 queue_size; | |
406 | u16 qid; | |
407 | }; | |
408 | ||
409 | typedef void (*ena_aenq_handler)(void *data, | |
410 | struct ena_admin_aenq_entry *aenq_e); | |
411 | ||
412 | /* Holds aenq handlers. Indexed by AENQ event group */ | |
413 | struct ena_aenq_handlers { | |
414 | ena_aenq_handler handlers[ENA_MAX_HANDLERS]; | |
415 | ena_aenq_handler unimplemented_handler; | |
416 | }; | |
417 | ||
418 | /*****************************************************************************/ | |
419 | /*****************************************************************************/ | |
420 | #if defined(__cplusplus) | |
421 | extern "C" { | |
422 | #endif | |
423 | ||
424 | /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism | |
425 | * @ena_dev: ENA communication layer struct | |
426 | * | |
427 | * Initialize the register read mechanism. | |
428 | * | |
429 | * @note: This method must be the first stage in the initialization sequence. | |
430 | * | |
431 | * @return - 0 on success, negative value on failure. | |
432 | */ | |
433 | int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); | |
434 | ||
435 | /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism | |
436 | * @ena_dev: ENA communication layer struct | |
9f95a23c | 437 | * @readless_supported: readless mode (enable/disable) |
7c673cae FG |
438 | */ |
439 | void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, | |
440 | bool readless_supported); | |
441 | ||
442 | /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return | |
443 | * value physical address. | |
444 | * @ena_dev: ENA communication layer struct | |
445 | */ | |
446 | void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev); | |
447 | ||
448 | /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism | |
449 | * @ena_dev: ENA communication layer struct | |
450 | */ | |
451 | void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev); | |
452 | ||
453 | /* ena_com_admin_init - Init the admin and the async queues | |
454 | * @ena_dev: ENA communication layer struct | |
455 | * @aenq_handlers: Those handlers to be called upon event. | |
7c673cae FG |
456 | * |
457 | * Initialize the admin submission and completion queues. | |
458 | * Initialize the asynchronous events notification queues. | |
459 | * | |
460 | * @return - 0 on success, negative value on failure. | |
461 | */ | |
462 | int ena_com_admin_init(struct ena_com_dev *ena_dev, | |
9f95a23c | 463 | struct ena_aenq_handlers *aenq_handlers); |
7c673cae FG |
464 | |
465 | /* ena_com_admin_destroy - Destroy the admin and the async events queues. | |
466 | * @ena_dev: ENA communication layer struct | |
467 | * | |
468 | * @note: Before calling this method, the caller must validate that the device | |
469 | * won't send any additional admin completions/aenq. | |
470 | * To achieve that, a FLR is recommended. | |
471 | */ | |
472 | void ena_com_admin_destroy(struct ena_com_dev *ena_dev); | |
473 | ||
474 | /* ena_com_dev_reset - Perform device FLR to the device. | |
475 | * @ena_dev: ENA communication layer struct | |
9f95a23c | 476 | * @reset_reason: Specify what is the trigger for the reset in case of an error. |
7c673cae FG |
477 | * |
478 | * @return - 0 on success, negative value on failure. | |
479 | */ | |
9f95a23c TL |
480 | int ena_com_dev_reset(struct ena_com_dev *ena_dev, |
481 | enum ena_regs_reset_reason_types reset_reason); | |
7c673cae FG |
482 | |
483 | /* ena_com_create_io_queue - Create io queue. | |
484 | * @ena_dev: ENA communication layer struct | |
9f95a23c | 485 | * @ctx - create context structure |
7c673cae FG |
486 | * |
487 | * Create the submission and the completion queues. | |
488 | * | |
489 | * @return - 0 on success, negative value on failure. | |
490 | */ | |
491 | int ena_com_create_io_queue(struct ena_com_dev *ena_dev, | |
492 | struct ena_com_create_io_ctx *ctx); | |
493 | ||
9f95a23c | 494 | /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid. |
7c673cae | 495 | * @ena_dev: ENA communication layer struct |
9f95a23c | 496 | * @qid - the caller virtual queue id. |
7c673cae FG |
497 | */ |
498 | void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid); | |
499 | ||
500 | /* ena_com_get_io_handlers - Return the io queue handlers | |
501 | * @ena_dev: ENA communication layer struct | |
502 | * @qid - the caller virtual queue id. | |
503 | * @io_sq - IO submission queue handler | |
504 | * @io_cq - IO completion queue handler. | |
505 | * | |
506 | * @return - 0 on success, negative value on failure. | |
507 | */ | |
508 | int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, | |
509 | struct ena_com_io_sq **io_sq, | |
510 | struct ena_com_io_cq **io_cq); | |
511 | ||
512 | /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications | |
513 | * @ena_dev: ENA communication layer struct | |
514 | * | |
515 | * After this method, aenq event can be received via AENQ. | |
516 | */ | |
517 | void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev); | |
518 | ||
519 | /* ena_com_set_admin_running_state - Set the state of the admin queue | |
520 | * @ena_dev: ENA communication layer struct | |
521 | * | |
522 | * Change the state of the admin queue (enable/disable) | |
523 | */ | |
524 | void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state); | |
525 | ||
526 | /* ena_com_get_admin_running_state - Get the admin queue state | |
527 | * @ena_dev: ENA communication layer struct | |
528 | * | |
529 | * Retrieve the state of the admin queue (enable/disable) | |
530 | * | |
531 | * @return - current polling mode (enable/disable) | |
532 | */ | |
533 | bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev); | |
534 | ||
535 | /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode | |
536 | * @ena_dev: ENA communication layer struct | |
537 | * @polling: ENAble/Disable polling mode | |
538 | * | |
539 | * Set the admin completion mode. | |
540 | */ | |
541 | void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling); | |
542 | ||
543 | /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode | |
544 | * @ena_dev: ENA communication layer struct | |
545 | * | |
546 | * Get the admin completion mode. | |
547 | * If polling mode is on, ena_com_execute_admin_command will perform a | |
548 | * polling on the admin completion queue for the commands completion, | |
549 | * otherwise it will wait on wait event. | |
550 | * | |
551 | * @return state | |
552 | */ | |
553 | bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev); | |
554 | ||
555 | /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler | |
556 | * @ena_dev: ENA communication layer struct | |
557 | * | |
558 | * This method go over the admin completion queue and wake up all the pending | |
559 | * threads that wait on the commands wait event. | |
560 | * | |
561 | * @note: Should be called after MSI-X interrupt. | |
562 | */ | |
563 | void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); | |
564 | ||
565 | /* ena_com_aenq_intr_handler - AENQ interrupt handler | |
566 | * @ena_dev: ENA communication layer struct | |
567 | * | |
568 | * This method go over the async event notification queue and call the proper | |
569 | * aenq handler. | |
570 | */ | |
571 | void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); | |
572 | ||
573 | /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. | |
574 | * @ena_dev: ENA communication layer struct | |
575 | * | |
576 | * This method aborts all the outstanding admin commands. | |
577 | * The caller should then call ena_com_wait_for_abort_completion to make sure | |
578 | * all the commands were completed. | |
579 | */ | |
580 | void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); | |
581 | ||
582 | /* ena_com_wait_for_abort_completion - Wait for admin commands abort. | |
583 | * @ena_dev: ENA communication layer struct | |
584 | * | |
585 | * This method wait until all the outstanding admin commands will be completed. | |
586 | */ | |
587 | void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); | |
588 | ||
589 | /* ena_com_validate_version - Validate the device parameters | |
590 | * @ena_dev: ENA communication layer struct | |
591 | * | |
592 | * This method validate the device parameters are the same as the saved | |
593 | * parameters in ena_dev. | |
594 | * This method is useful after device reset, to validate the device mac address | |
595 | * and the device offloads are the same as before the reset. | |
596 | * | |
597 | * @return - 0 on success negative value otherwise. | |
598 | */ | |
599 | int ena_com_validate_version(struct ena_com_dev *ena_dev); | |
600 | ||
601 | /* ena_com_get_link_params - Retrieve physical link parameters. | |
602 | * @ena_dev: ENA communication layer struct | |
603 | * @resp: Link parameters | |
604 | * | |
605 | * Retrieve the physical link parameters, | |
606 | * like speed, auto-negotiation and full duplex support. | |
607 | * | |
608 | * @return - 0 on Success negative value otherwise. | |
609 | */ | |
610 | int ena_com_get_link_params(struct ena_com_dev *ena_dev, | |
611 | struct ena_admin_get_feat_resp *resp); | |
612 | ||
9f95a23c TL |
613 | /* ena_com_extra_properties_strings_init - Initialize the extra properties strings buffer. |
614 | * @ena_dev: ENA communication layer struct | |
615 | * | |
616 | * Initialize the extra properties strings buffer. | |
617 | */ | |
618 | int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev); | |
619 | ||
620 | /* ena_com_delete_extra_properties_strings - Free the extra properties strings buffer. | |
621 | * @ena_dev: ENA communication layer struct | |
622 | * | |
623 | * Free the allocated extra properties strings buffer. | |
624 | */ | |
625 | void ena_com_delete_extra_properties_strings(struct ena_com_dev *ena_dev); | |
626 | ||
627 | /* ena_com_get_extra_properties_flags - Retrieve extra properties flags. | |
628 | * @ena_dev: ENA communication layer struct | |
629 | * @resp: Extra properties flags. | |
630 | * | |
631 | * Retrieve the extra properties flags. | |
632 | * | |
633 | * @return - 0 on Success negative value otherwise. | |
634 | */ | |
635 | int ena_com_get_extra_properties_flags(struct ena_com_dev *ena_dev, | |
636 | struct ena_admin_get_feat_resp *resp); | |
637 | ||
7c673cae FG |
638 | /* ena_com_get_dma_width - Retrieve physical dma address width the device |
639 | * supports. | |
640 | * @ena_dev: ENA communication layer struct | |
641 | * | |
642 | * Retrieve the maximum physical address bits the device can handle. | |
643 | * | |
644 | * @return: > 0 on Success and negative value otherwise. | |
645 | */ | |
646 | int ena_com_get_dma_width(struct ena_com_dev *ena_dev); | |
647 | ||
648 | /* ena_com_set_aenq_config - Set aenq groups configurations | |
649 | * @ena_dev: ENA communication layer struct | |
650 | * @groups flag: bit fields flags of enum ena_admin_aenq_group. | |
651 | * | |
652 | * Configure which aenq event group the driver would like to receive. | |
653 | * | |
654 | * @return: 0 on Success and negative value otherwise. | |
655 | */ | |
656 | int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag); | |
657 | ||
658 | /* ena_com_get_dev_attr_feat - Get device features | |
659 | * @ena_dev: ENA communication layer struct | |
660 | * @get_feat_ctx: returned context that contain the get features. | |
661 | * | |
662 | * @return: 0 on Success and negative value otherwise. | |
663 | */ | |
9f95a23c TL |
664 | int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, |
665 | struct ena_com_dev_get_features_ctx *get_feat_ctx); | |
7c673cae FG |
666 | |
667 | /* ena_com_get_dev_basic_stats - Get device basic statistics | |
668 | * @ena_dev: ENA communication layer struct | |
669 | * @stats: stats return value | |
670 | * | |
671 | * @return: 0 on Success and negative value otherwise. | |
672 | */ | |
673 | int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, | |
674 | struct ena_admin_basic_stats *stats); | |
675 | ||
676 | /* ena_com_set_dev_mtu - Configure the device mtu. | |
677 | * @ena_dev: ENA communication layer struct | |
678 | * @mtu: mtu value | |
679 | * | |
680 | * @return: 0 on Success and negative value otherwise. | |
681 | */ | |
682 | int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu); | |
683 | ||
684 | /* ena_com_get_offload_settings - Retrieve the device offloads capabilities | |
685 | * @ena_dev: ENA communication layer struct | |
686 | * @offlad: offload return value | |
687 | * | |
688 | * @return: 0 on Success and negative value otherwise. | |
689 | */ | |
9f95a23c TL |
690 | int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, |
691 | struct ena_admin_feature_offload_desc *offload); | |
7c673cae FG |
692 | |
693 | /* ena_com_rss_init - Init RSS | |
694 | * @ena_dev: ENA communication layer struct | |
695 | * @log_size: indirection log size | |
696 | * | |
697 | * Allocate RSS/RFS resources. | |
698 | * The caller then can configure rss using ena_com_set_hash_function, | |
699 | * ena_com_set_hash_ctrl and ena_com_indirect_table_set. | |
700 | * | |
701 | * @return: 0 on Success and negative value otherwise. | |
702 | */ | |
703 | int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); | |
704 | ||
705 | /* ena_com_rss_destroy - Destroy rss | |
706 | * @ena_dev: ENA communication layer struct | |
707 | * | |
708 | * Free all the RSS/RFS resources. | |
709 | */ | |
710 | void ena_com_rss_destroy(struct ena_com_dev *ena_dev); | |
711 | ||
712 | /* ena_com_fill_hash_function - Fill RSS hash function | |
713 | * @ena_dev: ENA communication layer struct | |
714 | * @func: The hash function (Toeplitz or crc) | |
715 | * @key: Hash key (for toeplitz hash) | |
716 | * @key_len: key length (max length 10 DW) | |
717 | * @init_val: initial value for the hash function | |
718 | * | |
719 | * Fill the ena_dev resources with the desire hash function, hash key, key_len | |
720 | * and key initial value (if needed by the hash function). | |
721 | * To flush the key into the device the caller should call | |
722 | * ena_com_set_hash_function. | |
723 | * | |
724 | * @return: 0 on Success and negative value otherwise. | |
725 | */ | |
726 | int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, | |
727 | enum ena_admin_hash_functions func, | |
728 | const u8 *key, u16 key_len, u32 init_val); | |
729 | ||
730 | /* ena_com_set_hash_function - Flush the hash function and it dependencies to | |
731 | * the device. | |
732 | * @ena_dev: ENA communication layer struct | |
733 | * | |
734 | * Flush the hash function and it dependencies (key, key length and | |
735 | * initial value) if needed. | |
736 | * | |
737 | * @note: Prior to this method the caller should call ena_com_fill_hash_function | |
738 | * | |
739 | * @return: 0 on Success and negative value otherwise. | |
740 | */ | |
741 | int ena_com_set_hash_function(struct ena_com_dev *ena_dev); | |
742 | ||
743 | /* ena_com_get_hash_function - Retrieve the hash function and the hash key | |
744 | * from the device. | |
745 | * @ena_dev: ENA communication layer struct | |
746 | * @func: hash function | |
747 | * @key: hash key | |
748 | * | |
749 | * Retrieve the hash function and the hash key from the device. | |
750 | * | |
751 | * @note: If the caller called ena_com_fill_hash_function but didn't flash | |
752 | * it to the device, the new configuration will be lost. | |
753 | * | |
754 | * @return: 0 on Success and negative value otherwise. | |
755 | */ | |
756 | int ena_com_get_hash_function(struct ena_com_dev *ena_dev, | |
757 | enum ena_admin_hash_functions *func, | |
758 | u8 *key); | |
759 | ||
760 | /* ena_com_fill_hash_ctrl - Fill RSS hash control | |
761 | * @ena_dev: ENA communication layer struct. | |
762 | * @proto: The protocol to configure. | |
763 | * @hash_fields: bit mask of ena_admin_flow_hash_fields | |
764 | * | |
765 | * Fill the ena_dev resources with the desire hash control (the ethernet | |
766 | * fields that take part of the hash) for a specific protocol. | |
767 | * To flush the hash control to the device, the caller should call | |
768 | * ena_com_set_hash_ctrl. | |
769 | * | |
770 | * @return: 0 on Success and negative value otherwise. | |
771 | */ | |
772 | int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, | |
773 | enum ena_admin_flow_hash_proto proto, | |
774 | u16 hash_fields); | |
775 | ||
776 | /* ena_com_set_hash_ctrl - Flush the hash control resources to the device. | |
777 | * @ena_dev: ENA communication layer struct | |
778 | * | |
779 | * Flush the hash control (the ethernet fields that take part of the hash) | |
780 | * | |
781 | * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl. | |
782 | * | |
783 | * @return: 0 on Success and negative value otherwise. | |
784 | */ | |
785 | int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); | |
786 | ||
787 | /* ena_com_get_hash_ctrl - Retrieve the hash control from the device. | |
788 | * @ena_dev: ENA communication layer struct | |
789 | * @proto: The protocol to retrieve. | |
790 | * @fields: bit mask of ena_admin_flow_hash_fields. | |
791 | * | |
792 | * Retrieve the hash control from the device. | |
793 | * | |
794 | * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash | |
795 | * it to the device, the new configuration will be lost. | |
796 | * | |
797 | * @return: 0 on Success and negative value otherwise. | |
798 | */ | |
799 | int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, | |
800 | enum ena_admin_flow_hash_proto proto, | |
801 | u16 *fields); | |
802 | ||
803 | /* ena_com_set_default_hash_ctrl - Set the hash control to a default | |
804 | * configuration. | |
805 | * @ena_dev: ENA communication layer struct | |
806 | * | |
807 | * Fill the ena_dev resources with the default hash control configuration. | |
808 | * To flush the hash control to the device, the caller should call | |
809 | * ena_com_set_hash_ctrl. | |
810 | * | |
811 | * @return: 0 on Success and negative value otherwise. | |
812 | */ | |
813 | int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev); | |
814 | ||
815 | /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS | |
816 | * indirection table | |
817 | * @ena_dev: ENA communication layer struct. | |
818 | * @entry_idx - indirection table entry. | |
819 | * @entry_value - redirection value | |
820 | * | |
821 | * Fill a single entry of the RSS indirection table in the ena_dev resources. | |
822 | * To flush the indirection table to the device, the called should call | |
823 | * ena_com_indirect_table_set. | |
824 | * | |
825 | * @return: 0 on Success and negative value otherwise. | |
826 | */ | |
827 | int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, | |
828 | u16 entry_idx, u16 entry_value); | |
829 | ||
830 | /* ena_com_indirect_table_set - Flush the indirection table to the device. | |
831 | * @ena_dev: ENA communication layer struct | |
832 | * | |
833 | * Flush the indirection hash control to the device. | |
834 | * Prior to this method the caller should call ena_com_indirect_table_fill_entry | |
835 | * | |
836 | * @return: 0 on Success and negative value otherwise. | |
837 | */ | |
838 | int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); | |
839 | ||
840 | /* ena_com_indirect_table_get - Retrieve the indirection table from the device. | |
841 | * @ena_dev: ENA communication layer struct | |
842 | * @ind_tbl: indirection table | |
843 | * | |
844 | * Retrieve the RSS indirection table from the device. | |
845 | * | |
9f95a23c TL |
846 | * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash |
847 | * it to the device, the new configuration will be lost. | |
7c673cae FG |
848 | * |
849 | * @return: 0 on Success and negative value otherwise. | |
850 | */ | |
851 | int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl); | |
852 | ||
853 | /* ena_com_allocate_host_info - Allocate host info resources. | |
854 | * @ena_dev: ENA communication layer struct | |
855 | * | |
856 | * @return: 0 on Success and negative value otherwise. | |
857 | */ | |
858 | int ena_com_allocate_host_info(struct ena_com_dev *ena_dev); | |
859 | ||
860 | /* ena_com_allocate_debug_area - Allocate debug area. | |
861 | * @ena_dev: ENA communication layer struct | |
862 | * @debug_area_size - debug area size. | |
863 | * | |
864 | * @return: 0 on Success and negative value otherwise. | |
865 | */ | |
866 | int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, | |
867 | u32 debug_area_size); | |
868 | ||
869 | /* ena_com_delete_debug_area - Free the debug area resources. | |
870 | * @ena_dev: ENA communication layer struct | |
871 | * | |
872 | * Free the allocate debug area. | |
873 | */ | |
874 | void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); | |
875 | ||
876 | /* ena_com_delete_host_info - Free the host info resources. | |
877 | * @ena_dev: ENA communication layer struct | |
878 | * | |
879 | * Free the allocate host info. | |
880 | */ | |
881 | void ena_com_delete_host_info(struct ena_com_dev *ena_dev); | |
882 | ||
883 | /* ena_com_set_host_attributes - Update the device with the host | |
884 | * attributes (debug area and host info) base address. | |
885 | * @ena_dev: ENA communication layer struct | |
886 | * | |
887 | * @return: 0 on Success and negative value otherwise. | |
888 | */ | |
889 | int ena_com_set_host_attributes(struct ena_com_dev *ena_dev); | |
890 | ||
891 | /* ena_com_create_io_cq - Create io completion queue. | |
892 | * @ena_dev: ENA communication layer struct | |
893 | * @io_cq - io completion queue handler | |
894 | ||
895 | * Create IO completion queue. | |
896 | * | |
897 | * @return - 0 on success, negative value on failure. | |
898 | */ | |
899 | int ena_com_create_io_cq(struct ena_com_dev *ena_dev, | |
900 | struct ena_com_io_cq *io_cq); | |
901 | ||
902 | /* ena_com_destroy_io_cq - Destroy io completion queue. | |
903 | * @ena_dev: ENA communication layer struct | |
904 | * @io_cq - io completion queue handler | |
905 | ||
906 | * Destroy IO completion queue. | |
907 | * | |
908 | * @return - 0 on success, negative value on failure. | |
909 | */ | |
910 | int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, | |
911 | struct ena_com_io_cq *io_cq); | |
912 | ||
913 | /* ena_com_execute_admin_command - Execute admin command | |
914 | * @admin_queue: admin queue. | |
915 | * @cmd: the admin command to execute. | |
916 | * @cmd_size: the command size. | |
917 | * @cmd_completion: command completion return value. | |
918 | * @cmd_comp_size: command completion size. | |
919 | ||
920 | * Submit an admin command and then wait until the device will return a | |
921 | * completion. | |
922 | * The completion will be copyed into cmd_comp. | |
923 | * | |
924 | * @return - 0 on success, negative value on failure. | |
925 | */ | |
926 | int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, | |
927 | struct ena_admin_aq_entry *cmd, | |
928 | size_t cmd_size, | |
929 | struct ena_admin_acq_entry *cmd_comp, | |
930 | size_t cmd_comp_size); | |
931 | ||
932 | /* ena_com_init_interrupt_moderation - Init interrupt moderation | |
933 | * @ena_dev: ENA communication layer struct | |
934 | * | |
935 | * @return - 0 on success, negative value on failure. | |
936 | */ | |
937 | int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); | |
938 | ||
939 | /* ena_com_destroy_interrupt_moderation - Destroy interrupt moderation resources | |
940 | * @ena_dev: ENA communication layer struct | |
941 | */ | |
942 | void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev); | |
943 | ||
944 | /* ena_com_interrupt_moderation_supported - Return if interrupt moderation | |
945 | * capability is supported by the device. | |
946 | * | |
947 | * @return - supported or not. | |
948 | */ | |
949 | bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); | |
950 | ||
951 | /* ena_com_config_default_interrupt_moderation_table - Restore the interrupt | |
952 | * moderation table back to the default parameters. | |
953 | * @ena_dev: ENA communication layer struct | |
954 | */ | |
9f95a23c | 955 | void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev); |
7c673cae FG |
956 | |
957 | /* ena_com_update_nonadaptive_moderation_interval_tx - Update the | |
958 | * non-adaptive interval in Tx direction. | |
959 | * @ena_dev: ENA communication layer struct | |
960 | * @tx_coalesce_usecs: Interval in usec. | |
961 | * | |
962 | * @return - 0 on success, negative value on failure. | |
963 | */ | |
9f95a23c TL |
964 | int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, |
965 | u32 tx_coalesce_usecs); | |
7c673cae FG |
966 | |
967 | /* ena_com_update_nonadaptive_moderation_interval_rx - Update the | |
968 | * non-adaptive interval in Rx direction. | |
969 | * @ena_dev: ENA communication layer struct | |
970 | * @rx_coalesce_usecs: Interval in usec. | |
971 | * | |
972 | * @return - 0 on success, negative value on failure. | |
973 | */ | |
9f95a23c TL |
974 | int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, |
975 | u32 rx_coalesce_usecs); | |
7c673cae FG |
976 | |
977 | /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the | |
978 | * non-adaptive interval in Tx direction. | |
979 | * @ena_dev: ENA communication layer struct | |
980 | * | |
981 | * @return - interval in usec | |
982 | */ | |
9f95a23c | 983 | unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev); |
7c673cae FG |
984 | |
985 | /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the | |
986 | * non-adaptive interval in Rx direction. | |
987 | * @ena_dev: ENA communication layer struct | |
988 | * | |
989 | * @return - interval in usec | |
990 | */ | |
9f95a23c | 991 | unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); |
7c673cae FG |
992 | |
993 | /* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt | |
994 | * moderation table. | |
995 | * @ena_dev: ENA communication layer struct | |
996 | * @level: Interrupt moderation table level | |
997 | * @entry: Entry value | |
998 | * | |
999 | * Update a single entry in the interrupt moderation table. | |
1000 | */ | |
1001 | void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, | |
1002 | enum ena_intr_moder_level level, | |
1003 | struct ena_intr_moder_entry *entry); | |
1004 | ||
1005 | /* ena_com_get_intr_moderation_entry - Init ena_intr_moder_entry. | |
1006 | * @ena_dev: ENA communication layer struct | |
1007 | * @level: Interrupt moderation table level | |
1008 | * @entry: Entry to fill. | |
1009 | * | |
1010 | * Initialize the entry according to the adaptive interrupt moderation table. | |
1011 | */ | |
1012 | void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, | |
1013 | enum ena_intr_moder_level level, | |
1014 | struct ena_intr_moder_entry *entry); | |
1015 | ||
9f95a23c TL |
1016 | |
1017 | /* ena_com_config_dev_mode - Configure the placement policy of the device. | |
1018 | * @ena_dev: ENA communication layer struct | |
1019 | * @llq_features: LLQ feature descriptor, retrieve via ena_com_get_dev_attr_feat. | |
1020 | * @ena_llq_config: The default driver LLQ parameters configurations | |
1021 | */ | |
1022 | int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, | |
1023 | struct ena_admin_feature_llq_desc *llq_features, | |
1024 | struct ena_llq_configurations *llq_default_config); | |
1025 | ||
1026 | static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) | |
7c673cae FG |
1027 | { |
1028 | return ena_dev->adaptive_coalescing; | |
1029 | } | |
1030 | ||
9f95a23c | 1031 | static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev) |
7c673cae FG |
1032 | { |
1033 | ena_dev->adaptive_coalescing = true; | |
1034 | } | |
1035 | ||
9f95a23c | 1036 | static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev) |
7c673cae FG |
1037 | { |
1038 | ena_dev->adaptive_coalescing = false; | |
1039 | } | |
1040 | ||
1041 | /* ena_com_calculate_interrupt_delay - Calculate new interrupt delay | |
1042 | * @ena_dev: ENA communication layer struct | |
1043 | * @pkts: Number of packets since the last update | |
1044 | * @bytes: Number of bytes received since the last update. | |
1045 | * @smoothed_interval: Returned interval | |
1046 | * @moder_tbl_idx: Current table level as input update new level as return | |
1047 | * value. | |
1048 | */ | |
9f95a23c TL |
1049 | static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev, |
1050 | unsigned int pkts, | |
1051 | unsigned int bytes, | |
1052 | unsigned int *smoothed_interval, | |
1053 | unsigned int *moder_tbl_idx) | |
7c673cae FG |
1054 | { |
1055 | enum ena_intr_moder_level curr_moder_idx, new_moder_idx; | |
1056 | struct ena_intr_moder_entry *curr_moder_entry; | |
1057 | struct ena_intr_moder_entry *pred_moder_entry; | |
1058 | struct ena_intr_moder_entry *new_moder_entry; | |
1059 | struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; | |
1060 | unsigned int interval; | |
1061 | ||
1062 | /* We apply adaptive moderation on Rx path only. | |
1063 | * Tx uses static interrupt moderation. | |
1064 | */ | |
1065 | if (!pkts || !bytes) | |
1066 | /* Tx interrupt, or spurious interrupt, | |
1067 | * in both cases we just use same delay values | |
1068 | */ | |
1069 | return; | |
1070 | ||
1071 | curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx); | |
1072 | if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) { | |
1073 | ena_trc_err("Wrong moderation index %u\n", curr_moder_idx); | |
1074 | return; | |
1075 | } | |
1076 | ||
1077 | curr_moder_entry = &intr_moder_tbl[curr_moder_idx]; | |
1078 | new_moder_idx = curr_moder_idx; | |
1079 | ||
1080 | if (curr_moder_idx == ENA_INTR_MODER_LOWEST) { | |
1081 | if ((pkts > curr_moder_entry->pkts_per_interval) || | |
1082 | (bytes > curr_moder_entry->bytes_per_interval)) | |
9f95a23c TL |
1083 | new_moder_idx = |
1084 | (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); | |
7c673cae | 1085 | } else { |
9f95a23c | 1086 | pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE]; |
7c673cae FG |
1087 | |
1088 | if ((pkts <= pred_moder_entry->pkts_per_interval) || | |
1089 | (bytes <= pred_moder_entry->bytes_per_interval)) | |
9f95a23c TL |
1090 | new_moder_idx = |
1091 | (enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE); | |
7c673cae FG |
1092 | else if ((pkts > curr_moder_entry->pkts_per_interval) || |
1093 | (bytes > curr_moder_entry->bytes_per_interval)) { | |
1094 | if (curr_moder_idx != ENA_INTR_MODER_HIGHEST) | |
9f95a23c TL |
1095 | new_moder_idx = |
1096 | (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); | |
7c673cae FG |
1097 | } |
1098 | } | |
1099 | new_moder_entry = &intr_moder_tbl[new_moder_idx]; | |
1100 | ||
1101 | interval = new_moder_entry->intr_moder_interval; | |
1102 | *smoothed_interval = ( | |
1103 | (interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT + | |
1104 | ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) / | |
1105 | 10; | |
1106 | ||
1107 | *moder_tbl_idx = new_moder_idx; | |
1108 | } | |
1109 | ||
1110 | /* ena_com_update_intr_reg - Prepare interrupt register | |
1111 | * @intr_reg: interrupt register to update. | |
1112 | * @rx_delay_interval: Rx interval in usecs | |
1113 | * @tx_delay_interval: Tx interval in usecs | |
1114 | * @unmask: unask enable/disable | |
1115 | * | |
1116 | * Prepare interrupt update register with the supplied parameters. | |
1117 | */ | |
1118 | static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, | |
1119 | u32 rx_delay_interval, | |
1120 | u32 tx_delay_interval, | |
1121 | bool unmask) | |
1122 | { | |
1123 | intr_reg->intr_control = 0; | |
1124 | intr_reg->intr_control |= rx_delay_interval & | |
1125 | ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; | |
1126 | ||
1127 | intr_reg->intr_control |= | |
1128 | (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) | |
9f95a23c | 1129 | & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; |
7c673cae FG |
1130 | |
1131 | if (unmask) | |
1132 | intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; | |
1133 | } | |
1134 | ||
9f95a23c TL |
1135 | static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl) |
1136 | { | |
1137 | u16 size, buffers_num; | |
1138 | u8 *buf; | |
1139 | ||
1140 | size = bounce_buf_ctrl->buffer_size; | |
1141 | buffers_num = bounce_buf_ctrl->buffers_num; | |
1142 | ||
1143 | buf = bounce_buf_ctrl->base_buffer + | |
1144 | (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size; | |
7c673cae | 1145 | |
9f95a23c TL |
1146 | prefetch(bounce_buf_ctrl->base_buffer + |
1147 | (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size); | |
1148 | ||
1149 | return buf; | |
1150 | } | |
7c673cae FG |
1151 | |
1152 | #if defined(__cplusplus) | |
1153 | } | |
1154 | #endif /* __cplusplus */ | |
1155 | #endif /* !(ENA_COM) */ |