[ceph.git] / ceph / src / seastar / dpdk / drivers / net / enic / base / vnic_wq.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
 */

#ifndef _VNIC_WQ_H_
#define _VNIC_WQ_H_


#include "vnic_dev.h"
#include "vnic_cq.h"
#include <rte_memzone.h>

/* Work queue control */
struct vnic_wq_ctrl {
	u64 ring_base;			/* 0x00 */
	u32 ring_size;			/* 0x08 */
	u32 pad0;
	u32 posted_index;		/* 0x10 */
	u32 pad1;
	u32 cq_index;			/* 0x18 */
	u32 pad2;
	u32 enable;			/* 0x20 */
	u32 pad3;
	u32 running;			/* 0x28 */
	u32 pad4;
	u32 fetch_index;		/* 0x30 */
	u32 pad5;
	u32 dca_value;			/* 0x38 */
	u32 pad6;
	u32 error_interrupt_enable;	/* 0x40 */
	u32 pad7;
	u32 error_interrupt_offset;	/* 0x48 */
	u32 pad8;
	u32 error_status;		/* 0x50 */
	u32 pad9;
};

struct vnic_wq {
	unsigned int index;
	uint64_t tx_offload_notsup_mask;
	struct vnic_dev *vdev;
	struct vnic_wq_ctrl __iomem *ctrl;              /* memory-mapped */
	struct vnic_dev_ring ring;
	struct rte_mbuf **bufs;
	unsigned int head_idx;
	unsigned int cq_pend;
	unsigned int tail_idx;
	unsigned int socket_id;
	const struct rte_memzone *cqmsg_rz;
	uint16_t last_completed_index;
	uint64_t offloads;
};

static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
{
	/* how many does SW own? */
	return wq->ring.desc_avail;
}

static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
{
	/* how many does HW own? */
	return wq->ring.desc_count - wq->ring.desc_avail - 1;
}

#define PI_LOG2_CACHE_LINE_SIZE        5
#define PI_INDEX_BITS            12
#define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
#define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
#define PI_PREFETCH_LEN_OFF 16
#define PI_PREFETCH_ADDR_BITS 43
#define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
#define PI_PREFETCH_ADDR_OFF 21

/** How many cache lines are touched by buffer (addr, len). */
static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
							unsigned int len)
{
	const unsigned long mask = PI_PREFETCH_LEN_MASK;
	const unsigned long laddr = (unsigned long)addr;
	unsigned long lines, equiv_len;
	/* A. If addr is aligned, our solution is just to round up len to the
	next boundary.

	e.g. addr = 0, len = 48
	+--------------------+
	|XXXXXXXXXXXXXXXXXXXX|    32-byte cacheline a
	+--------------------+
	|XXXXXXXXXX          |    cacheline b
	+--------------------+

	B. If addr is not aligned, however, we may use an extra
	cacheline.  e.g. addr = 12, len = 22

	+--------------------+
	|       XXXXXXXXXXXXX|
	+--------------------+
	|XX                  |
	+--------------------+

	Our solution is to make the problem equivalent to case A
	above by adding the empty space in the first cacheline to the length:
	unsigned long len;

	+--------------------+
	|eeeeeeeXXXXXXXXXXXXX|    "e" is empty space, which we add to len
	+--------------------+
	|XX                  |
	+--------------------+

	*/
	equiv_len = len + (laddr & mask);

	/* Now we can just round up this len to the next 32-byte boundary. */
	lines = (equiv_len + mask) & (~mask);

	/* Scale bytes -> cachelines. */
	return lines >> PI_LOG2_CACHE_LINE_SIZE;
}

static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
						unsigned int index)
{
	unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
	/* Wish we could avoid a branch here.  We could have separate
	 * vnic_wq_post() and vinc_wq_post_inline(), the latter
	 * only supporting < 1k (2^5 * 2^5) sends, I suppose.  This would
	 * eliminate the if (eop) branch as well.
	 */
	if (num_cache_lines > PI_PREFETCH_LEN_MASK)
		num_cache_lines = 0;
	return (index & PI_INDEX_MASK) |
	((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |
		(((addr >> PI_LOG2_CACHE_LINE_SIZE) &
	PI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);
}

static inline uint32_t
buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
{
	idx++;
	if (unlikely(idx == n_descriptors))
		idx = 0;
	return idx;
}

void vnic_wq_free(struct vnic_wq *wq);
int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
	unsigned int desc_count, unsigned int desc_size);
void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
	unsigned int fetch_index, unsigned int posted_index,
	unsigned int error_interrupt_enable,
	unsigned int error_interrupt_offset);
void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
	unsigned int error_interrupt_enable,
	unsigned int error_interrupt_offset);
void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
unsigned int vnic_wq_error_status(struct vnic_wq *wq);
void vnic_wq_enable(struct vnic_wq *wq);
int vnic_wq_disable(struct vnic_wq *wq);
void vnic_wq_clean(struct vnic_wq *wq,
		   void (*buf_clean)(struct rte_mbuf **buf));
#endif /* _VNIC_WQ_H_ */
Commit	Line	Data
9f95a23c TL	1	/* SPDX-License-Identifier: BSD-3-Clause
9f95a23c TL	2	* Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
7c673cae	3	* Copyright 2007 Nuova Systems, Inc. All rights reserved.
7c673cae FG	4	*/
	5
	6	#ifndef _VNIC_WQ_H_
	7	#define _VNIC_WQ_H_
	8
	9
	10	#include "vnic_dev.h"
	11	#include "vnic_cq.h"
	12	#include <rte_memzone.h>
	13
	14	/* Work queue control */
	15	struct vnic_wq_ctrl {
	16	u64 ring_base; /* 0x00 */
	17	u32 ring_size; /* 0x08 */
	18	u32 pad0;
	19	u32 posted_index; /* 0x10 */
	20	u32 pad1;
	21	u32 cq_index; /* 0x18 */
	22	u32 pad2;
	23	u32 enable; /* 0x20 */
	24	u32 pad3;
	25	u32 running; /* 0x28 */
	26	u32 pad4;
	27	u32 fetch_index; /* 0x30 */
	28	u32 pad5;
	29	u32 dca_value; /* 0x38 */
	30	u32 pad6;
	31	u32 error_interrupt_enable; /* 0x40 */
	32	u32 pad7;
	33	u32 error_interrupt_offset; /* 0x48 */
	34	u32 pad8;
	35	u32 error_status; /* 0x50 */
	36	u32 pad9;
	37	};
	38
7c673cae FG	39	struct vnic_wq {
7c673cae FG	40	unsigned int index;
9f95a23c	41	uint64_t tx_offload_notsup_mask;
7c673cae FG	42	struct vnic_dev *vdev;
	43	struct vnic_wq_ctrl __iomem ctrl; / memory-mapped */
	44	struct vnic_dev_ring ring;
9f95a23c	45	struct rte_mbuf **bufs;
7c673cae	46	unsigned int head_idx;
9f95a23c	47	unsigned int cq_pend;
7c673cae FG	48	unsigned int tail_idx;
	49	unsigned int socket_id;
	50	const struct rte_memzone *cqmsg_rz;
	51	uint16_t last_completed_index;
9f95a23c	52	uint64_t offloads;
7c673cae FG	53	};
	54
	55	static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
	56	{
	57	/* how many does SW own? */
	58	return wq->ring.desc_avail;
	59	}
	60
	61	static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
	62	{
	63	/* how many does HW own? */
	64	return wq->ring.desc_count - wq->ring.desc_avail - 1;
	65	}
	66
	67	#define PI_LOG2_CACHE_LINE_SIZE 5
	68	#define PI_INDEX_BITS 12
	69	#define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
	70	#define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
	71	#define PI_PREFETCH_LEN_OFF 16
	72	#define PI_PREFETCH_ADDR_BITS 43
	73	#define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
	74	#define PI_PREFETCH_ADDR_OFF 21
	75
	76	/** How many cache lines are touched by buffer (addr, len). */
	77	static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
	78	unsigned int len)
	79	{
	80	const unsigned long mask = PI_PREFETCH_LEN_MASK;
	81	const unsigned long laddr = (unsigned long)addr;
	82	unsigned long lines, equiv_len;
	83	/* A. If addr is aligned, our solution is just to round up len to the
	84	next boundary.
	85
	86	e.g. addr = 0, len = 48
	87	+--------------------+
	88	\|XXXXXXXXXXXXXXXXXXXX\| 32-byte cacheline a
	89	+--------------------+
	90	\|XXXXXXXXXX \| cacheline b
	91	+--------------------+
	92
	93	B. If addr is not aligned, however, we may use an extra
	94	cacheline. e.g. addr = 12, len = 22
	95
	96	+--------------------+
	97	\| XXXXXXXXXXXXX\|
	98	+--------------------+
	99	\|XX \|
	100	+--------------------+
	101
	102	Our solution is to make the problem equivalent to case A
	103	above by adding the empty space in the first cacheline to the length:
	104	unsigned long len;
	105
	106	+--------------------+
	107	\|eeeeeeeXXXXXXXXXXXXX\| "e" is empty space, which we add to len
	108	+--------------------+
	109	\|XX \|
	110	+--------------------+
	111
	112	*/
	113	equiv_len = len + (laddr & mask);
	114
	115	/* Now we can just round up this len to the next 32-byte boundary. */
	116	lines = (equiv_len + mask) & (~mask);
117
118	/* Scale bytes -> cachelines. */
119	return lines >> PI_LOG2_CACHE_LINE_SIZE;
120	}
121
122	static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
123	unsigned int index)
124	{
125	unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
126	/* Wish we could avoid a branch here. We could have separate
127	* vnic_wq_post() and vinc_wq_post_inline(), the latter
128	* only supporting < 1k (2^5 * 2^5) sends, I suppose. This would
129	* eliminate the if (eop) branch as well.
130	*/
131	if (num_cache_lines > PI_PREFETCH_LEN_MASK)
132	num_cache_lines = 0;
133	return (index & PI_INDEX_MASK) \|
134	((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) \|
135	(((addr >> PI_LOG2_CACHE_LINE_SIZE) &
136	PI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);
137	}
138
139	static inline uint32_t
140	buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
141	{
142	idx++;
143	if (unlikely(idx == n_descriptors))
144	idx = 0;
145	return idx;
146	}
147
148	void vnic_wq_free(struct vnic_wq *wq);
149	int vnic_wq_alloc(struct vnic_dev vdev, struct vnic_wq wq, unsigned int index,
150	unsigned int desc_count, unsigned int desc_size);
151	void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
152	unsigned int fetch_index, unsigned int posted_index,
153	unsigned int error_interrupt_enable,
154	unsigned int error_interrupt_offset);
155	void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
156	unsigned int error_interrupt_enable,
157	unsigned int error_interrupt_offset);
158	void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
159	unsigned int vnic_wq_error_status(struct vnic_wq *wq);
160	void vnic_wq_enable(struct vnic_wq *wq);
161	int vnic_wq_disable(struct vnic_wq *wq);
162	void vnic_wq_clean(struct vnic_wq *wq,
9f95a23c	163	void (buf_clean)(struct rte_mbuf *buf));
7c673cae	164	#endif /* _VNIC_WQ_H_ */