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9f95a23c TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(c) 2010-2017 Intel Corporation | |
7c673cae FG |
3 | */ |
4 | ||
5 | #ifndef _I40E_ETHDEV_H_ | |
6 | #define _I40E_ETHDEV_H_ | |
7 | ||
9f95a23c TL |
8 | #include <stdint.h> |
9 | ||
7c673cae FG |
10 | #include <rte_time.h> |
11 | #include <rte_kvargs.h> | |
11fdf7f2 | 12 | #include <rte_hash.h> |
9f95a23c | 13 | #include <rte_flow.h> |
11fdf7f2 | 14 | #include <rte_flow_driver.h> |
9f95a23c TL |
15 | #include <rte_tm_driver.h> |
16 | #include "rte_pmd_i40e.h" | |
17 | ||
18 | #include "base/i40e_register.h" | |
7c673cae FG |
19 | |
20 | #define I40E_VLAN_TAG_SIZE 4 | |
21 | ||
22 | #define I40E_AQ_LEN 32 | |
23 | #define I40E_AQ_BUF_SZ 4096 | |
24 | /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ | |
25 | #define I40E_MAX_Q_PER_TC 64 | |
26 | #define I40E_NUM_DESC_DEFAULT 512 | |
27 | #define I40E_NUM_DESC_ALIGN 32 | |
28 | #define I40E_BUF_SIZE_MIN 1024 | |
29 | #define I40E_FRAME_SIZE_MAX 9728 | |
9f95a23c | 30 | #define I40E_TSO_FRAME_SIZE_MAX 262144 |
7c673cae FG |
31 | #define I40E_QUEUE_BASE_ADDR_UNIT 128 |
32 | /* number of VSIs and queue default setting */ | |
33 | #define I40E_MAX_QP_NUM_PER_VF 16 | |
34 | #define I40E_DEFAULT_QP_NUM_FDIR 1 | |
35 | #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) | |
36 | #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) | |
37 | /* Maximun number of MAC addresses */ | |
38 | #define I40E_NUM_MACADDR_MAX 64 | |
39 | /* Maximum number of VFs */ | |
40 | #define I40E_MAX_VF 128 | |
9f95a23c TL |
41 | /*flag of no loopback*/ |
42 | #define I40E_AQ_LB_MODE_NONE 0x0 | |
7c673cae FG |
43 | /* |
44 | * vlan_id is a 12 bit number. | |
45 | * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. | |
46 | * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. | |
47 | * The higher 7 bit val specifies VFTA array index. | |
48 | */ | |
49 | #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) | |
50 | #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) | |
51 | ||
52 | /* Default TC traffic in case DCB is not enabled */ | |
53 | #define I40E_DEFAULT_TCMAP 0x1 | |
54 | #define I40E_FDIR_QUEUE_ID 0 | |
55 | ||
56 | /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ | |
57 | #define I40E_VMDQ_POOL_BASE 1 | |
58 | ||
59 | #define I40E_DEFAULT_RX_FREE_THRESH 32 | |
60 | #define I40E_DEFAULT_RX_PTHRESH 8 | |
61 | #define I40E_DEFAULT_RX_HTHRESH 8 | |
62 | #define I40E_DEFAULT_RX_WTHRESH 0 | |
63 | ||
64 | #define I40E_DEFAULT_TX_FREE_THRESH 32 | |
65 | #define I40E_DEFAULT_TX_PTHRESH 32 | |
66 | #define I40E_DEFAULT_TX_HTHRESH 0 | |
67 | #define I40E_DEFAULT_TX_WTHRESH 0 | |
68 | #define I40E_DEFAULT_TX_RSBIT_THRESH 32 | |
69 | ||
70 | /* Bit shift and mask */ | |
71 | #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) | |
72 | #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) | |
73 | #define I40E_8_BIT_WIDTH CHAR_BIT | |
74 | #define I40E_8_BIT_MASK UINT8_MAX | |
75 | #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) | |
76 | #define I40E_16_BIT_MASK UINT16_MAX | |
77 | #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) | |
78 | #define I40E_32_BIT_MASK UINT32_MAX | |
79 | #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) | |
80 | #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) | |
81 | ||
82 | /* Linux PF host with virtchnl version 1.1 */ | |
83 | #define PF_IS_V11(vf) \ | |
9f95a23c | 84 | (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ |
7c673cae FG |
85 | ((vf)->version_minor == 1)) |
86 | ||
9f95a23c TL |
87 | #define I40E_WRITE_GLB_REG(hw, reg, value) \ |
88 | do { \ | |
89 | uint32_t ori_val; \ | |
90 | struct rte_eth_dev *dev; \ | |
91 | ori_val = I40E_READ_REG((hw), (reg)); \ | |
92 | dev = ((struct i40e_adapter *)hw->back)->eth_dev; \ | |
93 | I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ | |
94 | (reg)), (value)); \ | |
95 | if (ori_val != value) \ | |
96 | PMD_DRV_LOG(WARNING, \ | |
97 | "i40e device %s changed global " \ | |
98 | "register [0x%08x]. original: 0x%08x, " \ | |
99 | "new: 0x%08x ", \ | |
100 | (dev->device->name), (reg), \ | |
101 | (ori_val), (value)); \ | |
102 | } while (0) | |
103 | ||
7c673cae FG |
104 | /* index flex payload per layer */ |
105 | enum i40e_flxpld_layer_idx { | |
106 | I40E_FLXPLD_L2_IDX = 0, | |
107 | I40E_FLXPLD_L3_IDX = 1, | |
108 | I40E_FLXPLD_L4_IDX = 2, | |
109 | I40E_MAX_FLXPLD_LAYER = 3, | |
110 | }; | |
111 | #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ | |
112 | #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ | |
113 | #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ | |
114 | #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ | |
115 | #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ | |
116 | ||
117 | /* i40e flags */ | |
118 | #define I40E_FLAG_RSS (1ULL << 0) | |
119 | #define I40E_FLAG_DCB (1ULL << 1) | |
120 | #define I40E_FLAG_VMDQ (1ULL << 2) | |
121 | #define I40E_FLAG_SRIOV (1ULL << 3) | |
122 | #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) | |
123 | #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) | |
124 | #define I40E_FLAG_FDIR (1ULL << 6) | |
125 | #define I40E_FLAG_VXLAN (1ULL << 7) | |
126 | #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) | |
11fdf7f2 | 127 | #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9) |
7c673cae FG |
128 | #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ |
129 | I40E_FLAG_DCB | \ | |
130 | I40E_FLAG_VMDQ | \ | |
131 | I40E_FLAG_SRIOV | \ | |
132 | I40E_FLAG_HEADER_SPLIT_DISABLED | \ | |
133 | I40E_FLAG_HEADER_SPLIT_ENABLED | \ | |
134 | I40E_FLAG_FDIR | \ | |
135 | I40E_FLAG_VXLAN | \ | |
11fdf7f2 TL |
136 | I40E_FLAG_RSS_AQ_CAPABLE | \ |
137 | I40E_FLAG_VF_MAC_BY_PF) | |
7c673cae FG |
138 | |
139 | #define I40E_RSS_OFFLOAD_ALL ( \ | |
140 | ETH_RSS_FRAG_IPV4 | \ | |
141 | ETH_RSS_NONFRAG_IPV4_TCP | \ | |
142 | ETH_RSS_NONFRAG_IPV4_UDP | \ | |
143 | ETH_RSS_NONFRAG_IPV4_SCTP | \ | |
144 | ETH_RSS_NONFRAG_IPV4_OTHER | \ | |
145 | ETH_RSS_FRAG_IPV6 | \ | |
146 | ETH_RSS_NONFRAG_IPV6_TCP | \ | |
147 | ETH_RSS_NONFRAG_IPV6_UDP | \ | |
148 | ETH_RSS_NONFRAG_IPV6_SCTP | \ | |
149 | ETH_RSS_NONFRAG_IPV6_OTHER | \ | |
150 | ETH_RSS_L2_PAYLOAD) | |
151 | ||
152 | /* All bits of RSS hash enable for X722*/ | |
153 | #define I40E_RSS_HENA_ALL_X722 ( \ | |
154 | (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ | |
155 | (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ | |
156 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ | |
157 | (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ | |
158 | (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ | |
159 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ | |
160 | I40E_RSS_HENA_ALL) | |
161 | ||
162 | /* All bits of RSS hash enable */ | |
163 | #define I40E_RSS_HENA_ALL ( \ | |
164 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ | |
165 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ | |
166 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ | |
167 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ | |
168 | (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ | |
169 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ | |
170 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ | |
171 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ | |
172 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ | |
173 | (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ | |
174 | (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ | |
175 | (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ | |
176 | (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ | |
177 | (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) | |
178 | ||
179 | #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET | |
180 | #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET | |
181 | ||
182 | /* Default queue interrupt throttling time in microseconds */ | |
183 | #define I40E_ITR_INDEX_DEFAULT 0 | |
9f95a23c | 184 | #define I40E_ITR_INDEX_NONE 3 |
7c673cae FG |
185 | #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ |
186 | #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ | |
9f95a23c | 187 | #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ |
7c673cae FG |
188 | /* Special FW support this floating VEB feature */ |
189 | #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 | |
190 | #define FLOATING_VEB_SUPPORTED_FW_MIN 0 | |
191 | ||
11fdf7f2 TL |
192 | #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) |
193 | #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 | |
194 | #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ | |
195 | I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) | |
196 | ||
197 | #define I40E_INSET_NONE 0x00000000000000000ULL | |
198 | ||
199 | /* bit0 ~ bit 7 */ | |
200 | #define I40E_INSET_DMAC 0x0000000000000001ULL | |
201 | #define I40E_INSET_SMAC 0x0000000000000002ULL | |
202 | #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL | |
203 | #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL | |
204 | #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL | |
205 | ||
206 | /* bit 8 ~ bit 15 */ | |
207 | #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL | |
208 | #define I40E_INSET_IPV4_DST 0x0000000000000200ULL | |
209 | #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL | |
210 | #define I40E_INSET_IPV6_DST 0x0000000000000800ULL | |
211 | #define I40E_INSET_SRC_PORT 0x0000000000001000ULL | |
212 | #define I40E_INSET_DST_PORT 0x0000000000002000ULL | |
213 | #define I40E_INSET_SCTP_VT 0x0000000000004000ULL | |
214 | ||
215 | /* bit 16 ~ bit 31 */ | |
216 | #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL | |
217 | #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL | |
218 | #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL | |
219 | #define I40E_INSET_IPV6_TC 0x0000000000080000ULL | |
220 | #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL | |
221 | #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL | |
222 | #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL | |
223 | #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL | |
224 | ||
225 | /* bit 32 ~ bit 47, tunnel fields */ | |
226 | #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL | |
227 | #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL | |
228 | #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL | |
229 | #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL | |
230 | #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL | |
231 | #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL | |
232 | ||
233 | /* bit 48 ~ bit 55 */ | |
234 | #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL | |
235 | ||
236 | /* bit 56 ~ bit 63, Flex Payload */ | |
237 | #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL | |
238 | #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL | |
239 | #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL | |
240 | #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL | |
241 | #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL | |
242 | #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL | |
243 | #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL | |
244 | #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL | |
245 | #define I40E_INSET_FLEX_PAYLOAD \ | |
246 | (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ | |
247 | I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ | |
248 | I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ | |
249 | I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) | |
250 | ||
9f95a23c TL |
251 | /* The max bandwidth of i40e is 40Gbps. */ |
252 | #define I40E_QOS_BW_MAX 40000 | |
253 | /* The bandwidth should be the multiple of 50Mbps. */ | |
254 | #define I40E_QOS_BW_GRANULARITY 50 | |
255 | /* The min bandwidth weight is 1. */ | |
256 | #define I40E_QOS_BW_WEIGHT_MIN 1 | |
257 | /* The max bandwidth weight is 127. */ | |
258 | #define I40E_QOS_BW_WEIGHT_MAX 127 | |
259 | /* The max queue region index is 7. */ | |
260 | #define I40E_REGION_MAX_INDEX 7 | |
261 | ||
262 | #define I40E_MAX_PERCENT 100 | |
263 | #define I40E_DEFAULT_DCB_APP_NUM 1 | |
264 | #define I40E_DEFAULT_DCB_APP_PRIO 3 | |
265 | ||
11fdf7f2 TL |
266 | /** |
267 | * The overhead from MTU to max frame size. | |
268 | * Considering QinQ packet, the VLAN tag needs to be counted twice. | |
269 | */ | |
270 | #define I40E_ETH_OVERHEAD \ | |
271 | (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) | |
272 | ||
7c673cae FG |
273 | struct i40e_adapter; |
274 | ||
275 | /** | |
276 | * MAC filter structure | |
277 | */ | |
278 | struct i40e_mac_filter_info { | |
279 | enum rte_mac_filter_type filter_type; | |
280 | struct ether_addr mac_addr; | |
281 | }; | |
282 | ||
283 | TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); | |
284 | ||
285 | /* MAC filter list structure */ | |
286 | struct i40e_mac_filter { | |
287 | TAILQ_ENTRY(i40e_mac_filter) next; | |
288 | struct i40e_mac_filter_info mac_info; | |
289 | }; | |
290 | ||
291 | TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); | |
292 | ||
293 | struct i40e_vsi; | |
294 | ||
295 | /* VSI list structure */ | |
296 | struct i40e_vsi_list { | |
297 | TAILQ_ENTRY(i40e_vsi_list) list; | |
298 | struct i40e_vsi *vsi; | |
299 | }; | |
300 | ||
301 | struct i40e_rx_queue; | |
302 | struct i40e_tx_queue; | |
303 | ||
304 | /* Bandwidth limit information */ | |
305 | struct i40e_bw_info { | |
306 | uint16_t bw_limit; /* BW Limit (0 = disabled) */ | |
307 | uint8_t bw_max; /* Max BW limit if enabled */ | |
308 | ||
309 | /* Relative credits within same TC with respect to other VSIs or Comps */ | |
310 | uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; | |
311 | /* Bandwidth limit per TC */ | |
11fdf7f2 | 312 | uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; |
7c673cae FG |
313 | /* Max bandwidth limit per TC */ |
314 | uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; | |
315 | }; | |
316 | ||
317 | /* Structure that defines a VEB */ | |
318 | struct i40e_veb { | |
319 | struct i40e_vsi_list_head head; | |
320 | struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ | |
321 | struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ | |
322 | uint16_t seid; /* The seid of VEB itself */ | |
323 | uint16_t uplink_seid; /* The uplink seid of this VEB */ | |
324 | uint16_t stats_idx; | |
325 | struct i40e_eth_stats stats; | |
326 | uint8_t enabled_tc; /* The traffic class enabled */ | |
11fdf7f2 | 327 | uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ |
7c673cae FG |
328 | struct i40e_bw_info bw_info; /* VEB bandwidth information */ |
329 | }; | |
330 | ||
331 | /* i40e MACVLAN filter structure */ | |
332 | struct i40e_macvlan_filter { | |
333 | struct ether_addr macaddr; | |
334 | enum rte_mac_filter_type filter_type; | |
335 | uint16_t vlan_id; | |
336 | }; | |
337 | ||
338 | /* | |
339 | * Structure that defines a VSI, associated with a adapter. | |
340 | */ | |
341 | struct i40e_vsi { | |
342 | struct i40e_adapter *adapter; /* Backreference to associated adapter */ | |
343 | struct i40e_aqc_vsi_properties_data info; /* VSI properties */ | |
344 | ||
345 | struct i40e_eth_stats eth_stats_offset; | |
346 | struct i40e_eth_stats eth_stats; | |
347 | /* | |
348 | * When drivers loaded, only a default main VSI exists. In case new VSI | |
349 | * needs to add, HW needs to know the layout that VSIs are organized. | |
350 | * Besides that, VSI isan element and can't switch packets, which needs | |
351 | * to add new component VEB to perform switching. So, a new VSI needs | |
9f95a23c | 352 | * to specify the uplink VSI (Parent VSI) before created. The |
7c673cae FG |
353 | * uplink VSI will check whether it had a VEB to switch packets. If no, |
354 | * it will try to create one. Then, uplink VSI will move the new VSI | |
355 | * into its' sib_vsi_list to manage all the downlink VSI. | |
356 | * sib_vsi_list: the VSI list that shared the same uplink VSI. | |
357 | * parent_vsi : the uplink VSI. It's NULL for main VSI. | |
358 | * veb : the VEB associates with the VSI. | |
359 | */ | |
360 | struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ | |
361 | struct i40e_vsi *parent_vsi; | |
362 | struct i40e_veb *veb; /* Associated veb, could be null */ | |
363 | struct i40e_veb *floating_veb; /* Associated floating veb */ | |
364 | bool offset_loaded; | |
365 | enum i40e_vsi_type type; /* VSI types */ | |
366 | uint16_t vlan_num; /* Total VLAN number */ | |
367 | uint16_t mac_num; /* Total mac number */ | |
368 | uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ | |
369 | struct i40e_mac_filter_list mac_list; /* macvlan filter list */ | |
370 | /* specific VSI-defined parameters, SRIOV stored the vf_id */ | |
371 | uint32_t user_param; | |
372 | uint16_t seid; /* The seid of VSI itself */ | |
373 | uint16_t uplink_seid; /* The uplink seid of this VSI */ | |
374 | uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ | |
375 | uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ | |
376 | uint16_t max_macaddrs; /* Maximum number of MAC addresses */ | |
377 | uint16_t base_queue; /* The first queue index of this VSI */ | |
378 | /* | |
379 | * The offset to visit VSI related register, assigned by HW when | |
380 | * creating VSI | |
381 | */ | |
382 | uint16_t vsi_id; | |
383 | uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ | |
384 | uint16_t nb_msix; /* The max number of msix vector */ | |
385 | uint8_t enabled_tc; /* The traffic class enabled */ | |
11fdf7f2 TL |
386 | uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ |
387 | uint8_t vlan_filter_on; /* The VLAN filter enabled */ | |
7c673cae FG |
388 | struct i40e_bw_info bw_info; /* VSI bandwidth information */ |
389 | }; | |
390 | ||
391 | struct pool_entry { | |
392 | LIST_ENTRY(pool_entry) next; | |
393 | uint16_t base; | |
394 | uint16_t len; | |
395 | }; | |
396 | ||
397 | LIST_HEAD(res_list, pool_entry); | |
398 | ||
399 | struct i40e_res_pool_info { | |
400 | uint32_t base; /* Resource start index */ | |
401 | uint32_t num_alloc; /* Allocated resource number */ | |
402 | uint32_t num_free; /* Total available resource number */ | |
403 | struct res_list alloc_list; /* Allocated resource list */ | |
404 | struct res_list free_list; /* Available resource list */ | |
405 | }; | |
406 | ||
407 | enum I40E_VF_STATE { | |
408 | I40E_VF_INACTIVE = 0, | |
409 | I40E_VF_INRESET, | |
410 | I40E_VF_ININIT, | |
411 | I40E_VF_ACTIVE, | |
412 | }; | |
413 | ||
414 | /* | |
415 | * Structure to store private data for PF host. | |
416 | */ | |
417 | struct i40e_pf_vf { | |
418 | struct i40e_pf *pf; | |
419 | struct i40e_vsi *vsi; | |
9f95a23c | 420 | enum I40E_VF_STATE state; /* The number of queue pairs available */ |
7c673cae FG |
421 | uint16_t vf_idx; /* VF index in pf->vfs */ |
422 | uint16_t lan_nb_qps; /* Actual queues allocated */ | |
423 | uint16_t reset_cnt; /* Total vf reset times */ | |
424 | struct ether_addr mac_addr; /* Default MAC address */ | |
9f95a23c TL |
425 | /* version of the virtchnl from VF */ |
426 | struct virtchnl_version_info version; | |
427 | uint32_t request_caps; /* offload caps requested from VF */ | |
7c673cae FG |
428 | }; |
429 | ||
430 | /* | |
431 | * Structure to store private data for flow control. | |
432 | */ | |
433 | struct i40e_fc_conf { | |
434 | uint16_t pause_time; /* Flow control pause timer */ | |
435 | /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ | |
436 | uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; | |
437 | /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ | |
438 | uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; | |
439 | }; | |
440 | ||
441 | /* | |
442 | * Structure to store private data for VMDQ instance | |
443 | */ | |
444 | struct i40e_vmdq_info { | |
445 | struct i40e_pf *pf; | |
446 | struct i40e_vsi *vsi; | |
447 | }; | |
448 | ||
9f95a23c TL |
449 | #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ |
450 | #define I40E_MAX_FLX_SOURCE_OFF 480 | |
451 | #define NONUSE_FLX_PIT_DEST_OFF 63 | |
452 | #define NONUSE_FLX_PIT_FSIZE 1 | |
453 | #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 | |
454 | #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ | |
455 | (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ | |
456 | I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ | |
457 | (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ | |
458 | I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ | |
459 | ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ | |
460 | NONUSE_FLX_PIT_DEST_OFF : \ | |
461 | ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ | |
462 | I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ | |
463 | I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) | |
464 | #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) | |
465 | #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) | |
466 | #define I40E_FDIR_IPv6_TC_OFFSET 20 | |
467 | ||
468 | /* A structure used to define the input for GTP flow */ | |
469 | struct i40e_gtp_flow { | |
470 | struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ | |
471 | uint8_t msg_type; /* Message type. */ | |
472 | uint32_t teid; /* TEID in big endian. */ | |
473 | }; | |
474 | ||
475 | /* A structure used to define the input for GTP IPV4 flow */ | |
476 | struct i40e_gtp_ipv4_flow { | |
477 | struct i40e_gtp_flow gtp; | |
478 | struct rte_eth_ipv4_flow ip4; | |
479 | }; | |
480 | ||
481 | /* A structure used to define the input for GTP IPV6 flow */ | |
482 | struct i40e_gtp_ipv6_flow { | |
483 | struct i40e_gtp_flow gtp; | |
484 | struct rte_eth_ipv6_flow ip6; | |
485 | }; | |
486 | ||
487 | /* A structure used to define the input for raw type flow */ | |
488 | struct i40e_raw_flow { | |
489 | uint16_t pctype; | |
490 | void *packet; | |
491 | uint32_t length; | |
492 | }; | |
493 | ||
494 | /* | |
495 | * A union contains the inputs for all types of flow | |
496 | * items in flows need to be in big endian | |
497 | */ | |
498 | union i40e_fdir_flow { | |
499 | struct rte_eth_l2_flow l2_flow; | |
500 | struct rte_eth_udpv4_flow udp4_flow; | |
501 | struct rte_eth_tcpv4_flow tcp4_flow; | |
502 | struct rte_eth_sctpv4_flow sctp4_flow; | |
503 | struct rte_eth_ipv4_flow ip4_flow; | |
504 | struct rte_eth_udpv6_flow udp6_flow; | |
505 | struct rte_eth_tcpv6_flow tcp6_flow; | |
506 | struct rte_eth_sctpv6_flow sctp6_flow; | |
507 | struct rte_eth_ipv6_flow ipv6_flow; | |
508 | struct i40e_gtp_flow gtp_flow; | |
509 | struct i40e_gtp_ipv4_flow gtp_ipv4_flow; | |
510 | struct i40e_gtp_ipv6_flow gtp_ipv6_flow; | |
511 | struct i40e_raw_flow raw_flow; | |
512 | }; | |
513 | ||
514 | enum i40e_fdir_ip_type { | |
515 | I40E_FDIR_IPTYPE_IPV4, | |
516 | I40E_FDIR_IPTYPE_IPV6, | |
517 | }; | |
518 | ||
519 | /* A structure used to contain extend input of flow */ | |
520 | struct i40e_fdir_flow_ext { | |
521 | uint16_t vlan_tci; | |
522 | uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; | |
523 | /* It is filled by the flexible payload to match. */ | |
524 | uint8_t is_vf; /* 1 for VF, 0 for port dev */ | |
525 | uint16_t dst_id; /* VF ID, available when is_vf is 1*/ | |
526 | bool inner_ip; /* If there is inner ip */ | |
527 | enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ | |
528 | bool customized_pctype; /* If customized pctype is used */ | |
529 | bool pkt_template; /* If raw packet template is used */ | |
530 | }; | |
531 | ||
532 | /* A structure used to define the input for a flow director filter entry */ | |
533 | struct i40e_fdir_input { | |
534 | enum i40e_filter_pctype pctype; | |
535 | union i40e_fdir_flow flow; | |
536 | /* Flow fields to match, dependent on flow_type */ | |
537 | struct i40e_fdir_flow_ext flow_ext; | |
538 | /* Additional fields to match */ | |
539 | }; | |
540 | ||
541 | /* Behavior will be taken if FDIR match */ | |
542 | enum i40e_fdir_behavior { | |
543 | I40E_FDIR_ACCEPT = 0, | |
544 | I40E_FDIR_REJECT, | |
545 | I40E_FDIR_PASSTHRU, | |
546 | }; | |
547 | ||
548 | /* Flow director report status | |
549 | * It defines what will be reported if FDIR entry is matched. | |
550 | */ | |
551 | enum i40e_fdir_status { | |
552 | I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ | |
553 | I40E_FDIR_REPORT_ID, /* Only report FD ID. */ | |
554 | I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ | |
555 | I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ | |
556 | }; | |
557 | ||
558 | /* A structure used to define an action when match FDIR packet filter. */ | |
559 | struct i40e_fdir_action { | |
560 | uint16_t rx_queue; /* Queue assigned to if FDIR match. */ | |
561 | enum i40e_fdir_behavior behavior; /* Behavior will be taken */ | |
562 | enum i40e_fdir_status report_status; /* Status report option */ | |
563 | /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or | |
564 | * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported | |
565 | * flex bytes start from in flexible payload. | |
566 | */ | |
567 | uint8_t flex_off; | |
568 | }; | |
569 | ||
570 | /* A structure used to define the flow director filter entry by filter_ctrl API | |
571 | * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and | |
572 | * RTE_ETH_FILTER_DELETE operations. | |
573 | */ | |
574 | struct i40e_fdir_filter_conf { | |
575 | uint32_t soft_id; | |
576 | /* ID, an unique value is required when deal with FDIR entry */ | |
577 | struct i40e_fdir_input input; /* Input set */ | |
578 | struct i40e_fdir_action action; /* Action taken when match */ | |
579 | }; | |
580 | ||
7c673cae FG |
581 | /* |
582 | * Structure to store flex pit for flow diretor. | |
583 | */ | |
584 | struct i40e_fdir_flex_pit { | |
585 | uint8_t src_offset; /* offset in words from the beginning of payload */ | |
586 | uint8_t size; /* size in words */ | |
587 | uint8_t dst_offset; /* offset in words of flexible payload */ | |
588 | }; | |
589 | ||
590 | struct i40e_fdir_flex_mask { | |
591 | uint8_t word_mask; /**< Bit i enables word i of flexible payload */ | |
9f95a23c | 592 | uint8_t nb_bitmask; |
7c673cae FG |
593 | struct { |
594 | uint8_t offset; | |
595 | uint16_t mask; | |
596 | } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; | |
597 | }; | |
598 | ||
9f95a23c TL |
599 | #define I40E_FILTER_PCTYPE_INVALID 0 |
600 | #define I40E_FILTER_PCTYPE_MAX 64 | |
601 | #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) | |
11fdf7f2 TL |
602 | |
603 | struct i40e_fdir_filter { | |
604 | TAILQ_ENTRY(i40e_fdir_filter) rules; | |
9f95a23c | 605 | struct i40e_fdir_filter_conf fdir; |
11fdf7f2 TL |
606 | }; |
607 | ||
608 | TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); | |
7c673cae FG |
609 | /* |
610 | * A structure used to define fields of a FDIR related info. | |
611 | */ | |
612 | struct i40e_fdir_info { | |
613 | struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ | |
614 | uint16_t match_counter_index; /* Statistic counter index used for fdir*/ | |
615 | struct i40e_tx_queue *txq; | |
616 | struct i40e_rx_queue *rxq; | |
617 | void *prg_pkt; /* memory for fdir program packet */ | |
618 | uint64_t dma_addr; /* physic address of packet memory*/ | |
619 | /* input set bits for each pctype */ | |
620 | uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; | |
621 | /* | |
622 | * the rule how bytes stream is extracted as flexible payload | |
623 | * for each payload layer, the setting can up to three elements | |
624 | */ | |
625 | struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; | |
626 | struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; | |
11fdf7f2 TL |
627 | |
628 | struct i40e_fdir_filter_list fdir_list; | |
629 | struct i40e_fdir_filter **hash_map; | |
630 | struct rte_hash *hash_table; | |
9f95a23c TL |
631 | |
632 | /* Mark if flex pit and mask is set */ | |
633 | bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; | |
634 | bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; | |
635 | ||
636 | bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ | |
11fdf7f2 TL |
637 | }; |
638 | ||
639 | /* Ethertype filter number HW supports */ | |
640 | #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 | |
641 | ||
642 | /* Ethertype filter struct */ | |
643 | struct i40e_ethertype_filter_input { | |
644 | struct ether_addr mac_addr; /* Mac address to match */ | |
645 | uint16_t ether_type; /* Ether type to match */ | |
646 | }; | |
647 | ||
648 | struct i40e_ethertype_filter { | |
649 | TAILQ_ENTRY(i40e_ethertype_filter) rules; | |
650 | struct i40e_ethertype_filter_input input; | |
651 | uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ | |
652 | uint16_t queue; /* Queue assigned to when match */ | |
653 | }; | |
654 | ||
655 | TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); | |
656 | ||
657 | struct i40e_ethertype_rule { | |
658 | struct i40e_ethertype_filter_list ethertype_list; | |
659 | struct i40e_ethertype_filter **hash_map; | |
660 | struct rte_hash *hash_table; | |
661 | }; | |
662 | ||
9f95a23c TL |
663 | /* queue region info */ |
664 | struct i40e_queue_region_info { | |
665 | /* the region id for this configuration */ | |
666 | uint8_t region_id; | |
667 | /* the start queue index for this region */ | |
668 | uint8_t queue_start_index; | |
669 | /* the total queue number of this queue region */ | |
670 | uint8_t queue_num; | |
671 | /* the total number of user priority for this region */ | |
672 | uint8_t user_priority_num; | |
673 | /* the packet's user priority for this region */ | |
674 | uint8_t user_priority[I40E_MAX_USER_PRIORITY]; | |
675 | /* the total number of flowtype for this region */ | |
676 | uint8_t flowtype_num; | |
677 | /** | |
678 | * the pctype or hardware flowtype of packet, | |
679 | * the specific index for each type has been defined | |
680 | * in file i40e_type.h as enum i40e_filter_pctype. | |
681 | */ | |
682 | uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; | |
683 | }; | |
684 | ||
685 | struct i40e_queue_regions { | |
686 | /* the total number of queue region for this port */ | |
687 | uint16_t queue_region_number; | |
688 | struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; | |
689 | }; | |
690 | ||
11fdf7f2 TL |
691 | /* Tunnel filter number HW supports */ |
692 | #define I40E_MAX_TUNNEL_FILTER_NUM 400 | |
693 | ||
694 | #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 | |
695 | #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 | |
9f95a23c TL |
696 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 |
697 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 | |
698 | #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 | |
699 | #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 | |
700 | #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 | |
701 | #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 | |
702 | #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 | |
703 | #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 | |
704 | #define I40E_AQC_NEW_TR_21 21 | |
705 | #define I40E_AQC_NEW_TR_22 22 | |
11fdf7f2 TL |
706 | |
707 | enum i40e_tunnel_iptype { | |
708 | I40E_TUNNEL_IPTYPE_IPV4, | |
709 | I40E_TUNNEL_IPTYPE_IPV6, | |
710 | }; | |
711 | ||
712 | /* Tunnel filter struct */ | |
713 | struct i40e_tunnel_filter_input { | |
714 | uint8_t outer_mac[6]; /* Outer mac address to match */ | |
715 | uint8_t inner_mac[6]; /* Inner mac address to match */ | |
716 | uint16_t inner_vlan; /* Inner vlan address to match */ | |
717 | enum i40e_tunnel_iptype ip_type; | |
718 | uint16_t flags; /* Filter type flag */ | |
719 | uint32_t tenant_id; /* Tenant id to match */ | |
720 | uint16_t general_fields[32]; /* Big buffer */ | |
721 | }; | |
722 | ||
723 | struct i40e_tunnel_filter { | |
724 | TAILQ_ENTRY(i40e_tunnel_filter) rules; | |
725 | struct i40e_tunnel_filter_input input; | |
726 | uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ | |
727 | uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ | |
728 | uint16_t queue; /* Queue assigned to when match */ | |
729 | }; | |
730 | ||
731 | TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); | |
732 | ||
733 | struct i40e_tunnel_rule { | |
734 | struct i40e_tunnel_filter_list tunnel_list; | |
735 | struct i40e_tunnel_filter **hash_map; | |
736 | struct rte_hash *hash_table; | |
737 | }; | |
738 | ||
739 | /** | |
740 | * Tunnel type. | |
741 | */ | |
742 | enum i40e_tunnel_type { | |
743 | I40E_TUNNEL_TYPE_NONE = 0, | |
744 | I40E_TUNNEL_TYPE_VXLAN, | |
745 | I40E_TUNNEL_TYPE_GENEVE, | |
746 | I40E_TUNNEL_TYPE_TEREDO, | |
747 | I40E_TUNNEL_TYPE_NVGRE, | |
748 | I40E_TUNNEL_TYPE_IP_IN_GRE, | |
749 | I40E_L2_TUNNEL_TYPE_E_TAG, | |
750 | I40E_TUNNEL_TYPE_MPLSoUDP, | |
751 | I40E_TUNNEL_TYPE_MPLSoGRE, | |
752 | I40E_TUNNEL_TYPE_QINQ, | |
9f95a23c TL |
753 | I40E_TUNNEL_TYPE_GTPC, |
754 | I40E_TUNNEL_TYPE_GTPU, | |
11fdf7f2 TL |
755 | I40E_TUNNEL_TYPE_MAX, |
756 | }; | |
757 | ||
758 | /** | |
759 | * Tunneling Packet filter configuration. | |
760 | */ | |
761 | struct i40e_tunnel_filter_conf { | |
762 | struct ether_addr outer_mac; /**< Outer MAC address to match. */ | |
763 | struct ether_addr inner_mac; /**< Inner MAC address to match. */ | |
764 | uint16_t inner_vlan; /**< Inner VLAN to match. */ | |
765 | uint32_t outer_vlan; /**< Outer VLAN to match */ | |
766 | enum i40e_tunnel_iptype ip_type; /**< IP address type. */ | |
767 | /** | |
768 | * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP | |
769 | * is set in filter_type, or inner destination IP address to match | |
770 | * if ETH_TUNNEL_FILTER_IIP is set in filter_type. | |
771 | */ | |
772 | union { | |
773 | uint32_t ipv4_addr; /**< IPv4 address in big endian. */ | |
774 | uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ | |
775 | } ip_addr; | |
776 | /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ | |
777 | uint16_t filter_type; | |
778 | enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ | |
779 | uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ | |
780 | uint16_t queue_id; /**< Queue assigned to if match. */ | |
781 | uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ | |
782 | uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ | |
7c673cae FG |
783 | }; |
784 | ||
785 | #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 | |
786 | #define I40E_MAX_MIRROR_RULES 64 | |
787 | /* | |
788 | * Mirror rule structure | |
789 | */ | |
790 | struct i40e_mirror_rule { | |
791 | TAILQ_ENTRY(i40e_mirror_rule) rules; | |
792 | uint8_t rule_type; | |
793 | uint16_t index; /* the sw index of mirror rule */ | |
794 | uint16_t id; /* the rule id assigned by firmware */ | |
795 | uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ | |
796 | uint16_t num_entries; | |
797 | /* the info stores depend on the rule type. | |
798 | If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. | |
799 | If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. | |
800 | */ | |
801 | uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; | |
802 | }; | |
803 | ||
804 | TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); | |
805 | ||
11fdf7f2 TL |
806 | /* |
807 | * Struct to store flow created. | |
808 | */ | |
809 | struct rte_flow { | |
810 | TAILQ_ENTRY(rte_flow) node; | |
811 | enum rte_filter_type filter_type; | |
812 | void *rule; | |
813 | }; | |
814 | ||
815 | TAILQ_HEAD(i40e_flow_list, rte_flow); | |
816 | ||
9f95a23c TL |
817 | /* Struct to store Traffic Manager shaper profile. */ |
818 | struct i40e_tm_shaper_profile { | |
819 | TAILQ_ENTRY(i40e_tm_shaper_profile) node; | |
820 | uint32_t shaper_profile_id; | |
821 | uint32_t reference_count; | |
822 | struct rte_tm_shaper_params profile; | |
823 | }; | |
824 | ||
825 | TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); | |
826 | ||
827 | /* node type of Traffic Manager */ | |
828 | enum i40e_tm_node_type { | |
829 | I40E_TM_NODE_TYPE_PORT, | |
830 | I40E_TM_NODE_TYPE_TC, | |
831 | I40E_TM_NODE_TYPE_QUEUE, | |
832 | I40E_TM_NODE_TYPE_MAX, | |
833 | }; | |
834 | ||
835 | /* Struct to store Traffic Manager node configuration. */ | |
836 | struct i40e_tm_node { | |
837 | TAILQ_ENTRY(i40e_tm_node) node; | |
838 | uint32_t id; | |
839 | uint32_t priority; | |
840 | uint32_t weight; | |
841 | uint32_t reference_count; | |
842 | struct i40e_tm_node *parent; | |
843 | struct i40e_tm_shaper_profile *shaper_profile; | |
844 | struct rte_tm_node_params params; | |
845 | }; | |
846 | ||
847 | TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); | |
848 | ||
849 | /* Struct to store all the Traffic Manager configuration. */ | |
850 | struct i40e_tm_conf { | |
851 | struct i40e_shaper_profile_list shaper_profile_list; | |
852 | struct i40e_tm_node *root; /* root node - port */ | |
853 | struct i40e_tm_node_list tc_list; /* node list for all the TCs */ | |
854 | struct i40e_tm_node_list queue_list; /* node list for all the queues */ | |
855 | /** | |
856 | * The number of added TC nodes. | |
857 | * It should be no more than the TC number of this port. | |
858 | */ | |
859 | uint32_t nb_tc_node; | |
860 | /** | |
861 | * The number of added queue nodes. | |
862 | * It should be no more than the queue number of this port. | |
863 | */ | |
864 | uint32_t nb_queue_node; | |
865 | /** | |
866 | * This flag is used to check if APP can change the TM node | |
867 | * configuration. | |
868 | * When it's true, means the configuration is applied to HW, | |
869 | * APP should not change the configuration. | |
870 | * As we don't support on-the-fly configuration, when starting | |
871 | * the port, APP should call the hierarchy_commit API to set this | |
872 | * flag to true. When stopping the port, this flag should be set | |
873 | * to false. | |
874 | */ | |
875 | bool committed; | |
876 | }; | |
877 | ||
878 | enum i40e_new_pctype { | |
879 | I40E_CUSTOMIZED_GTPC = 0, | |
880 | I40E_CUSTOMIZED_GTPU_IPV4, | |
881 | I40E_CUSTOMIZED_GTPU_IPV6, | |
882 | I40E_CUSTOMIZED_GTPU, | |
883 | I40E_CUSTOMIZED_MAX, | |
884 | }; | |
885 | ||
886 | #define I40E_FILTER_PCTYPE_INVALID 0 | |
887 | struct i40e_customized_pctype { | |
888 | enum i40e_new_pctype index; /* Indicate which customized pctype */ | |
889 | uint8_t pctype; /* New pctype value */ | |
890 | bool valid; /* Check if it's valid */ | |
891 | }; | |
892 | ||
893 | struct i40e_rte_flow_rss_conf { | |
894 | struct rte_flow_action_rss conf; /**< RSS parameters. */ | |
895 | uint16_t queue_region_conf; /**< Queue region config flag */ | |
896 | uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? | |
897 | I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * | |
898 | sizeof(uint32_t)]; /* Hash key. */ | |
899 | uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */ | |
900 | }; | |
901 | ||
7c673cae FG |
902 | /* |
903 | * Structure to store private data specific for PF instance. | |
904 | */ | |
905 | struct i40e_pf { | |
906 | struct i40e_adapter *adapter; /* The adapter this PF associate to */ | |
907 | struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ | |
908 | uint16_t mac_seid; /* The seid of the MAC of this PF */ | |
909 | uint16_t main_vsi_seid; /* The seid of the main VSI */ | |
910 | uint16_t max_num_vsi; | |
911 | struct i40e_res_pool_info qp_pool; /*Queue pair pool */ | |
912 | struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ | |
913 | ||
914 | struct i40e_hw_port_stats stats_offset; | |
915 | struct i40e_hw_port_stats stats; | |
9f95a23c TL |
916 | /* internal packet statistics, it should be excluded from the total */ |
917 | struct i40e_eth_stats internal_stats_offset; | |
918 | struct i40e_eth_stats internal_stats; | |
7c673cae FG |
919 | bool offset_loaded; |
920 | ||
921 | struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ | |
922 | struct ether_addr dev_addr; /* PF device mac address */ | |
923 | uint64_t flags; /* PF feature flags */ | |
924 | /* All kinds of queue pair setting for different VSIs */ | |
925 | struct i40e_pf_vf *vfs; | |
926 | uint16_t vf_num; | |
927 | /* Each of below queue pairs should be power of 2 since it's the | |
928 | precondition after TC configuration applied */ | |
929 | uint16_t lan_nb_qp_max; | |
930 | uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ | |
931 | uint16_t lan_qp_offset; | |
932 | uint16_t vmdq_nb_qp_max; | |
933 | uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ | |
934 | uint16_t vmdq_qp_offset; | |
935 | uint16_t vf_nb_qp_max; | |
936 | uint16_t vf_nb_qps; /* The number of queue pairs of VF */ | |
937 | uint16_t vf_qp_offset; | |
938 | uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ | |
939 | uint16_t fdir_qp_offset; | |
940 | ||
941 | uint16_t hash_lut_size; /* The size of hash lookup table */ | |
942 | /* input set bits for each pctype */ | |
943 | uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; | |
944 | /* store VXLAN UDP ports */ | |
945 | uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; | |
946 | uint16_t vxlan_bitmap; /* Vxlan bit mask */ | |
947 | ||
948 | /* VMDQ related info */ | |
949 | uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ | |
950 | uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ | |
951 | struct i40e_vmdq_info *vmdq; | |
952 | ||
953 | struct i40e_fdir_info fdir; /* flow director info */ | |
11fdf7f2 TL |
954 | struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ |
955 | struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ | |
9f95a23c TL |
956 | struct i40e_rte_flow_rss_conf rss_info; /* rss info */ |
957 | struct i40e_queue_regions queue_region; /* queue region info */ | |
7c673cae FG |
958 | struct i40e_fc_conf fc_conf; /* Flow control conf */ |
959 | struct i40e_mirror_rule_list mirror_list; | |
960 | uint16_t nb_mirror_rule; /* The number of mirror rules */ | |
961 | bool floating_veb; /* The flag to use the floating VEB */ | |
962 | /* The floating enable flag for the specific VF */ | |
963 | bool floating_veb_list[I40E_MAX_VF]; | |
11fdf7f2 TL |
964 | struct i40e_flow_list flow_list; |
965 | bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ | |
9f95a23c | 966 | bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ |
11fdf7f2 | 967 | bool qinq_replace_flag; /* QINQ filter replace is done */ |
9f95a23c TL |
968 | struct i40e_tm_conf tm_conf; |
969 | bool support_multi_driver; /* 1 - support multiple driver */ | |
970 | ||
971 | /* Dynamic Device Personalization */ | |
972 | bool gtp_support; /* 1 - support GTP-C and GTP-U */ | |
973 | /* customer customized pctype */ | |
974 | struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; | |
975 | /* Switch Domain Id */ | |
976 | uint16_t switch_domain_id; | |
7c673cae FG |
977 | }; |
978 | ||
979 | enum pending_msg { | |
980 | PFMSG_LINK_CHANGE = 0x1, | |
981 | PFMSG_RESET_IMPENDING = 0x2, | |
982 | PFMSG_DRIVER_CLOSE = 0x4, | |
983 | }; | |
984 | ||
985 | struct i40e_vsi_vlan_pvid_info { | |
986 | uint16_t on; /* Enable or disable pvid */ | |
987 | union { | |
988 | uint16_t pvid; /* Valid in case 'on' is set to set pvid */ | |
989 | struct { | |
990 | /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, | |
991 | * while 'untagged' will reject untagged packets. | |
992 | */ | |
993 | uint8_t tagged; | |
994 | uint8_t untagged; | |
995 | } reject; | |
996 | } config; | |
997 | }; | |
998 | ||
999 | struct i40e_vf_rx_queues { | |
1000 | uint64_t rx_dma_addr; | |
1001 | uint32_t rx_ring_len; | |
1002 | uint32_t buff_size; | |
1003 | }; | |
1004 | ||
1005 | struct i40e_vf_tx_queues { | |
1006 | uint64_t tx_dma_addr; | |
1007 | uint32_t tx_ring_len; | |
1008 | }; | |
1009 | ||
1010 | /* | |
1011 | * Structure to store private data specific for VF instance. | |
1012 | */ | |
1013 | struct i40e_vf { | |
1014 | struct i40e_adapter *adapter; /* The adapter this VF associate to */ | |
1015 | struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ | |
1016 | uint16_t num_queue_pairs; | |
1017 | uint16_t max_pkt_len; /* Maximum packet length */ | |
1018 | bool promisc_unicast_enabled; | |
1019 | bool promisc_multicast_enabled; | |
1020 | ||
1021 | uint32_t version_major; /* Major version number */ | |
1022 | uint32_t version_minor; /* Minor version number */ | |
1023 | uint16_t promisc_flags; /* Promiscuous setting */ | |
1024 | uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ | |
1025 | ||
9f95a23c TL |
1026 | struct ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; /* Multicast addrs */ |
1027 | uint16_t mc_addrs_num; /* Multicast mac addresses number */ | |
1028 | ||
7c673cae FG |
1029 | /* Event from pf */ |
1030 | bool dev_closed; | |
1031 | bool link_up; | |
9f95a23c | 1032 | enum virtchnl_link_speed link_speed; |
7c673cae FG |
1033 | bool vf_reset; |
1034 | volatile uint32_t pend_cmd; /* pending command not finished yet */ | |
11fdf7f2 | 1035 | int32_t cmd_retval; /* return value of the cmd response from PF */ |
7c673cae FG |
1036 | u16 pend_msg; /* flags indicates events from pf not handled yet */ |
1037 | uint8_t *aq_resp; /* buffer to store the adminq response from PF */ | |
1038 | ||
1039 | /* VSI info */ | |
9f95a23c TL |
1040 | struct virtchnl_vf_resource *vf_res; /* All VSIs */ |
1041 | struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ | |
7c673cae FG |
1042 | struct i40e_vsi vsi; |
1043 | uint64_t flags; | |
1044 | }; | |
1045 | ||
9f95a23c TL |
1046 | #define I40E_MAX_PKT_TYPE 256 |
1047 | #define I40E_FLOW_TYPE_MAX 64 | |
11fdf7f2 | 1048 | |
7c673cae FG |
1049 | /* |
1050 | * Structure to store private data for each PF/VF instance. | |
1051 | */ | |
1052 | struct i40e_adapter { | |
1053 | /* Common for both PF and VF */ | |
1054 | struct i40e_hw hw; | |
1055 | struct rte_eth_dev *eth_dev; | |
1056 | ||
1057 | /* Specific for PF or VF */ | |
1058 | union { | |
1059 | struct i40e_pf pf; | |
1060 | struct i40e_vf vf; | |
1061 | }; | |
1062 | ||
1063 | /* For vector PMD */ | |
1064 | bool rx_bulk_alloc_allowed; | |
1065 | bool rx_vec_allowed; | |
1066 | bool tx_simple_allowed; | |
1067 | bool tx_vec_allowed; | |
1068 | ||
1069 | /* For PTP */ | |
1070 | struct rte_timecounter systime_tc; | |
1071 | struct rte_timecounter rx_tstamp_tc; | |
1072 | struct rte_timecounter tx_tstamp_tc; | |
11fdf7f2 TL |
1073 | |
1074 | /* ptype mapping table */ | |
1075 | uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; | |
9f95a23c TL |
1076 | /* flow type to pctype mapping table */ |
1077 | uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; | |
1078 | uint64_t flow_types_mask; | |
1079 | uint64_t pctypes_mask; | |
1080 | ||
1081 | /* For devargs */ | |
1082 | uint8_t use_latest_vec; | |
1083 | ||
1084 | /* For RSS reta table update */ | |
1085 | uint8_t rss_reta_updated; | |
1086 | }; | |
1087 | ||
1088 | /** | |
1089 | * Strucute to store private data for each VF representor instance | |
1090 | */ | |
1091 | struct i40e_vf_representor { | |
1092 | uint16_t switch_domain_id; | |
1093 | /**< Virtual Function ID */ | |
1094 | uint16_t vf_id; | |
1095 | /**< Virtual Function ID */ | |
1096 | struct i40e_adapter *adapter; | |
1097 | /**< Private data store of assocaiated physical function */ | |
1098 | struct i40e_eth_stats stats_offset; | |
1099 | /**< Zero-point of VF statistics*/ | |
11fdf7f2 TL |
1100 | }; |
1101 | ||
1102 | extern const struct rte_flow_ops i40e_flow_ops; | |
1103 | ||
1104 | union i40e_filter_t { | |
1105 | struct rte_eth_ethertype_filter ethertype_filter; | |
9f95a23c | 1106 | struct i40e_fdir_filter_conf fdir_filter; |
11fdf7f2 TL |
1107 | struct rte_eth_tunnel_filter_conf tunnel_filter; |
1108 | struct i40e_tunnel_filter_conf consistent_tunnel_filter; | |
9f95a23c | 1109 | struct i40e_rte_flow_rss_conf rss_conf; |
11fdf7f2 TL |
1110 | }; |
1111 | ||
1112 | typedef int (*parse_filter_t)(struct rte_eth_dev *dev, | |
1113 | const struct rte_flow_attr *attr, | |
1114 | const struct rte_flow_item pattern[], | |
1115 | const struct rte_flow_action actions[], | |
1116 | struct rte_flow_error *error, | |
1117 | union i40e_filter_t *filter); | |
1118 | struct i40e_valid_pattern { | |
1119 | enum rte_flow_item_type *items; | |
1120 | parse_filter_t parse_filter; | |
7c673cae FG |
1121 | }; |
1122 | ||
1123 | int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); | |
1124 | int i40e_vsi_release(struct i40e_vsi *vsi); | |
1125 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, | |
1126 | enum i40e_vsi_type type, | |
1127 | struct i40e_vsi *uplink_vsi, | |
1128 | uint16_t user_param); | |
1129 | int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); | |
1130 | int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); | |
1131 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); | |
1132 | int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); | |
1133 | int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); | |
1134 | int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr); | |
1135 | void i40e_update_vsi_stats(struct i40e_vsi *vsi); | |
1136 | void i40e_pf_disable_irq0(struct i40e_hw *hw); | |
1137 | void i40e_pf_enable_irq0(struct i40e_hw *hw); | |
9f95a23c TL |
1138 | int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); |
1139 | void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); | |
7c673cae FG |
1140 | void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); |
1141 | int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, | |
1142 | struct i40e_vsi_vlan_pvid_info *info); | |
1143 | int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); | |
1144 | int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); | |
9f95a23c TL |
1145 | uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); |
1146 | uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); | |
7c673cae FG |
1147 | enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); |
1148 | enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); | |
1149 | int i40e_fdir_setup(struct i40e_pf *pf); | |
1150 | const struct rte_memzone *i40e_memzone_reserve(const char *name, | |
1151 | uint32_t len, | |
1152 | int socket_id); | |
1153 | int i40e_fdir_configure(struct rte_eth_dev *dev); | |
1154 | void i40e_fdir_teardown(struct i40e_pf *pf); | |
9f95a23c TL |
1155 | enum i40e_filter_pctype |
1156 | i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, | |
1157 | uint16_t flow_type); | |
1158 | uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, | |
1159 | enum i40e_filter_pctype pctype); | |
7c673cae FG |
1160 | int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, |
1161 | enum rte_filter_op filter_op, | |
1162 | void *arg); | |
1163 | int i40e_select_filter_input_set(struct i40e_hw *hw, | |
1164 | struct rte_eth_input_set_conf *conf, | |
1165 | enum rte_filter_type filter); | |
11fdf7f2 | 1166 | void i40e_fdir_filter_restore(struct i40e_pf *pf); |
7c673cae FG |
1167 | int i40e_hash_filter_inset_select(struct i40e_hw *hw, |
1168 | struct rte_eth_input_set_conf *conf); | |
1169 | int i40e_fdir_filter_inset_select(struct i40e_pf *pf, | |
1170 | struct rte_eth_input_set_conf *conf); | |
1171 | int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, | |
1172 | uint32_t retval, uint8_t *msg, | |
1173 | uint16_t msglen); | |
1174 | void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, | |
1175 | struct rte_eth_rxq_info *qinfo); | |
1176 | void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, | |
1177 | struct rte_eth_txq_info *qinfo); | |
11fdf7f2 TL |
1178 | struct i40e_ethertype_filter * |
1179 | i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, | |
1180 | const struct i40e_ethertype_filter_input *input); | |
1181 | int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, | |
1182 | struct i40e_ethertype_filter_input *input); | |
1183 | int i40e_sw_fdir_filter_del(struct i40e_pf *pf, | |
9f95a23c | 1184 | struct i40e_fdir_input *input); |
11fdf7f2 TL |
1185 | struct i40e_tunnel_filter * |
1186 | i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, | |
1187 | const struct i40e_tunnel_filter_input *input); | |
1188 | int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, | |
1189 | struct i40e_tunnel_filter_input *input); | |
1190 | uint64_t i40e_get_default_input_set(uint16_t pctype); | |
1191 | int i40e_ethertype_filter_set(struct i40e_pf *pf, | |
1192 | struct rte_eth_ethertype_filter *filter, | |
1193 | bool add); | |
1194 | int i40e_add_del_fdir_filter(struct rte_eth_dev *dev, | |
1195 | const struct rte_eth_fdir_filter *filter, | |
1196 | bool add); | |
9f95a23c TL |
1197 | int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, |
1198 | const struct i40e_fdir_filter_conf *filter, | |
1199 | bool add); | |
11fdf7f2 TL |
1200 | int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, |
1201 | struct rte_eth_tunnel_filter_conf *tunnel_filter, | |
1202 | uint8_t add); | |
1203 | int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, | |
1204 | struct i40e_tunnel_filter_conf *tunnel_filter, | |
1205 | uint8_t add); | |
1206 | int i40e_fdir_flush(struct rte_eth_dev *dev); | |
1207 | int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, | |
1208 | struct i40e_macvlan_filter *mv_f, | |
1209 | int num, struct ether_addr *addr); | |
1210 | int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, | |
1211 | struct i40e_macvlan_filter *filter, | |
1212 | int total); | |
1213 | void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); | |
1214 | int i40e_add_macvlan_filters(struct i40e_vsi *vsi, | |
1215 | struct i40e_macvlan_filter *filter, | |
1216 | int total); | |
1217 | bool is_i40e_supported(struct rte_eth_dev *dev); | |
1218 | ||
9f95a23c TL |
1219 | int i40e_validate_input_set(enum i40e_filter_pctype pctype, |
1220 | enum rte_filter_type filter, uint64_t inset); | |
1221 | int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, | |
1222 | uint8_t nb_elem); | |
1223 | uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); | |
1224 | void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); | |
1225 | void i40e_check_write_global_reg(struct i40e_hw *hw, | |
1226 | uint32_t addr, uint32_t val); | |
1227 | ||
1228 | int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); | |
1229 | void i40e_tm_conf_init(struct rte_eth_dev *dev); | |
1230 | void i40e_tm_conf_uninit(struct rte_eth_dev *dev); | |
1231 | struct i40e_customized_pctype* | |
1232 | i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); | |
1233 | void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, | |
1234 | uint32_t pkg_size, | |
1235 | enum rte_pmd_i40e_package_op op); | |
1236 | int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); | |
1237 | int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, | |
1238 | struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); | |
1239 | void i40e_init_queue_region_conf(struct rte_eth_dev *dev); | |
1240 | void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); | |
1241 | int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); | |
1242 | int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); | |
1243 | int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, | |
1244 | const struct rte_flow_action_rss *in); | |
1245 | int i40e_action_rss_same(const struct rte_flow_action_rss *comp, | |
1246 | const struct rte_flow_action_rss *with); | |
1247 | int i40e_config_rss_filter(struct i40e_pf *pf, | |
1248 | struct i40e_rte_flow_rss_conf *conf, bool add); | |
1249 | int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); | |
1250 | int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); | |
1251 | ||
11fdf7f2 TL |
1252 | #define I40E_DEV_TO_PCI(eth_dev) \ |
1253 | RTE_DEV_TO_PCI((eth_dev)->device) | |
7c673cae FG |
1254 | |
1255 | /* I40E_DEV_PRIVATE_TO */ | |
1256 | #define I40E_DEV_PRIVATE_TO_PF(adapter) \ | |
1257 | (&((struct i40e_adapter *)adapter)->pf) | |
1258 | #define I40E_DEV_PRIVATE_TO_HW(adapter) \ | |
1259 | (&((struct i40e_adapter *)adapter)->hw) | |
1260 | #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ | |
1261 | ((struct i40e_adapter *)adapter) | |
1262 | ||
1263 | /* I40EVF_DEV_PRIVATE_TO */ | |
1264 | #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ | |
1265 | (&((struct i40e_adapter *)adapter)->vf) | |
1266 | ||
1267 | static inline struct i40e_vsi * | |
1268 | i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) | |
1269 | { | |
1270 | struct i40e_hw *hw; | |
1271 | ||
1272 | if (!adapter) | |
1273 | return NULL; | |
1274 | ||
1275 | hw = I40E_DEV_PRIVATE_TO_HW(adapter); | |
1276 | if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { | |
1277 | struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); | |
1278 | return &vf->vsi; | |
1279 | } else { | |
1280 | struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); | |
1281 | return pf->main_vsi; | |
1282 | } | |
1283 | } | |
1284 | #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ | |
1285 | i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) | |
1286 | ||
1287 | /* I40E_VSI_TO */ | |
1288 | #define I40E_VSI_TO_HW(vsi) \ | |
1289 | (&(((struct i40e_vsi *)vsi)->adapter->hw)) | |
1290 | #define I40E_VSI_TO_PF(vsi) \ | |
1291 | (&(((struct i40e_vsi *)vsi)->adapter->pf)) | |
1292 | #define I40E_VSI_TO_VF(vsi) \ | |
1293 | (&(((struct i40e_vsi *)vsi)->adapter->vf)) | |
1294 | #define I40E_VSI_TO_DEV_DATA(vsi) \ | |
1295 | (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) | |
1296 | #define I40E_VSI_TO_ETH_DEV(vsi) \ | |
1297 | (((struct i40e_vsi *)vsi)->adapter->eth_dev) | |
1298 | ||
1299 | /* I40E_PF_TO */ | |
1300 | #define I40E_PF_TO_HW(pf) \ | |
1301 | (&(((struct i40e_pf *)pf)->adapter->hw)) | |
1302 | #define I40E_PF_TO_ADAPTER(pf) \ | |
1303 | ((struct i40e_adapter *)pf->adapter) | |
1304 | ||
1305 | /* I40E_VF_TO */ | |
1306 | #define I40E_VF_TO_HW(vf) \ | |
1307 | (&(((struct i40e_vf *)vf)->adapter->hw)) | |
1308 | ||
1309 | static inline void | |
1310 | i40e_init_adminq_parameter(struct i40e_hw *hw) | |
1311 | { | |
1312 | hw->aq.num_arq_entries = I40E_AQ_LEN; | |
1313 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
1314 | hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; | |
1315 | hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; | |
1316 | } | |
1317 | ||
1318 | static inline int | |
1319 | i40e_align_floor(int n) | |
1320 | { | |
1321 | if (n == 0) | |
1322 | return 0; | |
1323 | return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); | |
1324 | } | |
1325 | ||
1326 | static inline uint16_t | |
9f95a23c | 1327 | i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) |
7c673cae | 1328 | { |
9f95a23c TL |
1329 | uint16_t interval = 0; |
1330 | ||
1331 | if (is_multi_drv) { | |
1332 | interval = I40E_QUEUE_ITR_INTERVAL_MAX; | |
1333 | } else { | |
1334 | if (is_pf) | |
1335 | interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; | |
1336 | else | |
1337 | interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; | |
1338 | } | |
7c673cae FG |
1339 | |
1340 | /* Convert to hardware count, as writing each 1 represents 2 us */ | |
1341 | return interval / 2; | |
1342 | } | |
1343 | ||
1344 | #define I40E_VALID_FLOW(flow_type) \ | |
1345 | ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ | |
1346 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ | |
1347 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ | |
1348 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ | |
1349 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ | |
1350 | (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ | |
1351 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ | |
1352 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ | |
1353 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ | |
1354 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ | |
1355 | (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) | |
1356 | ||
1357 | #define I40E_VALID_PCTYPE_X722(pctype) \ | |
1358 | ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ | |
1359 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ | |
1360 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ | |
1361 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ | |
1362 | (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ | |
1363 | (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ | |
1364 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ | |
1365 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ | |
1366 | (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ | |
1367 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ | |
1368 | (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ | |
1369 | (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ | |
1370 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ | |
1371 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ | |
1372 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ | |
1373 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ | |
1374 | (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) | |
1375 | ||
1376 | #define I40E_VALID_PCTYPE(pctype) \ | |
1377 | ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ | |
1378 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ | |
1379 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ | |
1380 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ | |
1381 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ | |
1382 | (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ | |
1383 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ | |
1384 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ | |
1385 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ | |
1386 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ | |
1387 | (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) | |
1388 | ||
1389 | #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ | |
1390 | (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ | |
1391 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ | |
1392 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ | |
1393 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ | |
1394 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ | |
1395 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) | |
1396 | ||
1397 | #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ | |
1398 | (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ | |
1399 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ | |
1400 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ | |
9f95a23c TL |
1401 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ |
1402 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ | |
1403 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) | |
7c673cae FG |
1404 | |
1405 | #endif /* _I40E_ETHDEV_H_ */ |