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9f95a23c TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(c) 2010-2017 Intel Corporation | |
11fdf7f2 TL |
3 | */ |
4 | ||
9f95a23c | 5 | #include <rte_ethdev_driver.h> |
11fdf7f2 TL |
6 | |
7 | #include "base/ixgbe_api.h" | |
9f95a23c | 8 | #include "base/ixgbe_x550.h" |
11fdf7f2 TL |
9 | #include "ixgbe_ethdev.h" |
10 | #include "rte_pmd_ixgbe.h" | |
11 | ||
12 | int | |
9f95a23c | 13 | rte_pmd_ixgbe_set_vf_mac_addr(uint16_t port, uint16_t vf, |
11fdf7f2 TL |
14 | struct ether_addr *mac_addr) |
15 | { | |
16 | struct ixgbe_hw *hw; | |
17 | struct ixgbe_vf_info *vfinfo; | |
18 | int rar_entry; | |
19 | uint8_t *new_mac = (uint8_t *)(mac_addr); | |
20 | struct rte_eth_dev *dev; | |
21 | struct rte_pci_device *pci_dev; | |
22 | ||
23 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
24 | ||
25 | dev = &rte_eth_devices[port]; | |
9f95a23c | 26 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
27 | |
28 | if (!is_ixgbe_supported(dev)) | |
29 | return -ENOTSUP; | |
30 | ||
31 | if (vf >= pci_dev->max_vfs) | |
32 | return -EINVAL; | |
33 | ||
34 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
35 | vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); | |
36 | rar_entry = hw->mac.num_rar_entries - (vf + 1); | |
37 | ||
38 | if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) { | |
39 | rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, | |
40 | ETHER_ADDR_LEN); | |
41 | return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, | |
42 | IXGBE_RAH_AV); | |
43 | } | |
44 | return -EINVAL; | |
45 | } | |
46 | ||
47 | int | |
9f95a23c | 48 | rte_pmd_ixgbe_ping_vf(uint16_t port, uint16_t vf) |
11fdf7f2 TL |
49 | { |
50 | struct ixgbe_hw *hw; | |
51 | struct ixgbe_vf_info *vfinfo; | |
52 | struct rte_eth_dev *dev; | |
53 | struct rte_pci_device *pci_dev; | |
54 | uint32_t ctrl; | |
55 | ||
56 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
57 | ||
58 | dev = &rte_eth_devices[port]; | |
9f95a23c | 59 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
60 | |
61 | if (!is_ixgbe_supported(dev)) | |
62 | return -ENOTSUP; | |
63 | ||
64 | if (vf >= pci_dev->max_vfs) | |
65 | return -EINVAL; | |
66 | ||
67 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
68 | vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); | |
69 | ||
70 | ctrl = IXGBE_PF_CONTROL_MSG; | |
71 | if (vfinfo[vf].clear_to_send) | |
72 | ctrl |= IXGBE_VT_MSGTYPE_CTS; | |
73 | ||
74 | ixgbe_write_mbx(hw, &ctrl, 1, vf); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | int | |
9f95a23c | 80 | rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint16_t port, uint16_t vf, uint8_t on) |
11fdf7f2 TL |
81 | { |
82 | struct ixgbe_hw *hw; | |
83 | struct ixgbe_mac_info *mac; | |
84 | struct rte_eth_dev *dev; | |
85 | struct rte_pci_device *pci_dev; | |
86 | ||
87 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
88 | ||
89 | dev = &rte_eth_devices[port]; | |
9f95a23c | 90 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
91 | |
92 | if (!is_ixgbe_supported(dev)) | |
93 | return -ENOTSUP; | |
94 | ||
95 | if (vf >= pci_dev->max_vfs) | |
96 | return -EINVAL; | |
97 | ||
98 | if (on > 1) | |
99 | return -EINVAL; | |
100 | ||
101 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
102 | mac = &hw->mac; | |
103 | ||
104 | mac->ops.set_vlan_anti_spoofing(hw, on, vf); | |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
109 | int | |
9f95a23c | 110 | rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint16_t port, uint16_t vf, uint8_t on) |
11fdf7f2 TL |
111 | { |
112 | struct ixgbe_hw *hw; | |
113 | struct ixgbe_mac_info *mac; | |
114 | struct rte_eth_dev *dev; | |
115 | struct rte_pci_device *pci_dev; | |
116 | ||
117 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
118 | ||
119 | dev = &rte_eth_devices[port]; | |
9f95a23c | 120 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
121 | |
122 | if (!is_ixgbe_supported(dev)) | |
123 | return -ENOTSUP; | |
124 | ||
125 | if (vf >= pci_dev->max_vfs) | |
126 | return -EINVAL; | |
127 | ||
128 | if (on > 1) | |
129 | return -EINVAL; | |
130 | ||
131 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
132 | mac = &hw->mac; | |
133 | mac->ops.set_mac_anti_spoofing(hw, on, vf); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | int | |
9f95a23c | 139 | rte_pmd_ixgbe_set_vf_vlan_insert(uint16_t port, uint16_t vf, uint16_t vlan_id) |
11fdf7f2 TL |
140 | { |
141 | struct ixgbe_hw *hw; | |
142 | uint32_t ctrl; | |
143 | struct rte_eth_dev *dev; | |
144 | struct rte_pci_device *pci_dev; | |
145 | ||
146 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
147 | ||
148 | dev = &rte_eth_devices[port]; | |
9f95a23c | 149 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
150 | |
151 | if (!is_ixgbe_supported(dev)) | |
152 | return -ENOTSUP; | |
153 | ||
154 | if (vf >= pci_dev->max_vfs) | |
155 | return -EINVAL; | |
156 | ||
157 | if (vlan_id > ETHER_MAX_VLAN_ID) | |
158 | return -EINVAL; | |
159 | ||
160 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
161 | ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf)); | |
162 | if (vlan_id) { | |
163 | ctrl = vlan_id; | |
164 | ctrl |= IXGBE_VMVIR_VLANA_DEFAULT; | |
165 | } else { | |
166 | ctrl = 0; | |
167 | } | |
168 | ||
169 | IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | int | |
9f95a23c | 175 | rte_pmd_ixgbe_set_tx_loopback(uint16_t port, uint8_t on) |
11fdf7f2 TL |
176 | { |
177 | struct ixgbe_hw *hw; | |
178 | uint32_t ctrl; | |
179 | struct rte_eth_dev *dev; | |
180 | ||
181 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
182 | ||
183 | dev = &rte_eth_devices[port]; | |
184 | ||
185 | if (!is_ixgbe_supported(dev)) | |
186 | return -ENOTSUP; | |
187 | ||
188 | if (on > 1) | |
189 | return -EINVAL; | |
190 | ||
191 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
192 | ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); | |
193 | /* enable or disable VMDQ loopback */ | |
194 | if (on) | |
195 | ctrl |= IXGBE_PFDTXGSWC_VT_LBEN; | |
196 | else | |
197 | ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN; | |
198 | ||
199 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | int | |
9f95a23c | 205 | rte_pmd_ixgbe_set_all_queues_drop_en(uint16_t port, uint8_t on) |
11fdf7f2 TL |
206 | { |
207 | struct ixgbe_hw *hw; | |
208 | uint32_t reg_value; | |
209 | int i; | |
210 | int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT); | |
211 | struct rte_eth_dev *dev; | |
212 | ||
213 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
214 | ||
215 | dev = &rte_eth_devices[port]; | |
216 | ||
217 | if (!is_ixgbe_supported(dev)) | |
218 | return -ENOTSUP; | |
219 | ||
220 | if (on > 1) | |
221 | return -EINVAL; | |
222 | ||
223 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
224 | for (i = 0; i <= num_queues; i++) { | |
225 | reg_value = IXGBE_QDE_WRITE | | |
226 | (i << IXGBE_QDE_IDX_SHIFT) | | |
227 | (on & IXGBE_QDE_ENABLE); | |
228 | IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value); | |
229 | } | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | int | |
9f95a23c | 235 | rte_pmd_ixgbe_set_vf_split_drop_en(uint16_t port, uint16_t vf, uint8_t on) |
11fdf7f2 TL |
236 | { |
237 | struct ixgbe_hw *hw; | |
238 | uint32_t reg_value; | |
239 | struct rte_eth_dev *dev; | |
240 | struct rte_pci_device *pci_dev; | |
241 | ||
242 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
243 | ||
244 | dev = &rte_eth_devices[port]; | |
9f95a23c | 245 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
246 | |
247 | if (!is_ixgbe_supported(dev)) | |
248 | return -ENOTSUP; | |
249 | ||
250 | /* only support VF's 0 to 63 */ | |
251 | if ((vf >= pci_dev->max_vfs) || (vf > 63)) | |
252 | return -EINVAL; | |
253 | ||
254 | if (on > 1) | |
255 | return -EINVAL; | |
256 | ||
257 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
258 | reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf)); | |
259 | if (on) | |
260 | reg_value |= IXGBE_SRRCTL_DROP_EN; | |
261 | else | |
262 | reg_value &= ~IXGBE_SRRCTL_DROP_EN; | |
263 | ||
264 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | int | |
9f95a23c | 270 | rte_pmd_ixgbe_set_vf_vlan_stripq(uint16_t port, uint16_t vf, uint8_t on) |
11fdf7f2 TL |
271 | { |
272 | struct rte_eth_dev *dev; | |
273 | struct rte_pci_device *pci_dev; | |
274 | struct ixgbe_hw *hw; | |
275 | uint16_t queues_per_pool; | |
276 | uint32_t q; | |
277 | ||
278 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
279 | ||
280 | dev = &rte_eth_devices[port]; | |
9f95a23c | 281 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
282 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
283 | ||
284 | if (!is_ixgbe_supported(dev)) | |
285 | return -ENOTSUP; | |
286 | ||
287 | if (vf >= pci_dev->max_vfs) | |
288 | return -EINVAL; | |
289 | ||
290 | if (on > 1) | |
291 | return -EINVAL; | |
292 | ||
293 | RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP); | |
294 | ||
295 | /* The PF has 128 queue pairs and in SRIOV configuration | |
296 | * those queues will be assigned to VF's, so RXDCTL | |
297 | * registers will be dealing with queues which will be | |
298 | * assigned to VF's. | |
299 | * Let's say we have SRIOV configured with 31 VF's then the | |
300 | * first 124 queues 0-123 will be allocated to VF's and only | |
301 | * the last 4 queues 123-127 will be assigned to the PF. | |
302 | */ | |
303 | if (hw->mac.type == ixgbe_mac_82598EB) | |
304 | queues_per_pool = (uint16_t)hw->mac.max_rx_queues / | |
305 | ETH_16_POOLS; | |
306 | else | |
307 | queues_per_pool = (uint16_t)hw->mac.max_rx_queues / | |
308 | ETH_64_POOLS; | |
309 | ||
310 | for (q = 0; q < queues_per_pool; q++) | |
311 | (*dev->dev_ops->vlan_strip_queue_set)(dev, | |
312 | q + vf * queues_per_pool, on); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | int | |
9f95a23c | 317 | rte_pmd_ixgbe_set_vf_rxmode(uint16_t port, uint16_t vf, |
11fdf7f2 TL |
318 | uint16_t rx_mask, uint8_t on) |
319 | { | |
320 | int val = 0; | |
321 | struct rte_eth_dev *dev; | |
322 | struct rte_pci_device *pci_dev; | |
323 | struct ixgbe_hw *hw; | |
324 | uint32_t vmolr; | |
325 | ||
326 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
327 | ||
328 | dev = &rte_eth_devices[port]; | |
9f95a23c | 329 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
330 | |
331 | if (!is_ixgbe_supported(dev)) | |
332 | return -ENOTSUP; | |
333 | ||
334 | if (vf >= pci_dev->max_vfs) | |
335 | return -EINVAL; | |
336 | ||
337 | if (on > 1) | |
338 | return -EINVAL; | |
339 | ||
340 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
341 | vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); | |
342 | ||
343 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
344 | PMD_INIT_LOG(ERR, "setting VF receive mode set should be done" | |
345 | " on 82599 hardware and newer"); | |
346 | return -ENOTSUP; | |
347 | } | |
348 | if (ixgbe_vt_check(hw) < 0) | |
349 | return -ENOTSUP; | |
350 | ||
351 | val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val); | |
352 | ||
353 | if (on) | |
354 | vmolr |= val; | |
355 | else | |
356 | vmolr &= ~val; | |
357 | ||
358 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | int | |
9f95a23c | 364 | rte_pmd_ixgbe_set_vf_rx(uint16_t port, uint16_t vf, uint8_t on) |
11fdf7f2 TL |
365 | { |
366 | struct rte_eth_dev *dev; | |
367 | struct rte_pci_device *pci_dev; | |
368 | uint32_t reg, addr; | |
369 | uint32_t val; | |
370 | const uint8_t bit1 = 0x1; | |
371 | struct ixgbe_hw *hw; | |
372 | ||
373 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
374 | ||
375 | dev = &rte_eth_devices[port]; | |
9f95a23c | 376 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
377 | |
378 | if (!is_ixgbe_supported(dev)) | |
379 | return -ENOTSUP; | |
380 | ||
381 | if (vf >= pci_dev->max_vfs) | |
382 | return -EINVAL; | |
383 | ||
384 | if (on > 1) | |
385 | return -EINVAL; | |
386 | ||
387 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
388 | ||
389 | if (ixgbe_vt_check(hw) < 0) | |
390 | return -ENOTSUP; | |
391 | ||
392 | /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */ | |
393 | if (vf >= 32) { | |
394 | addr = IXGBE_VFRE(1); | |
395 | val = bit1 << (vf - 32); | |
396 | } else { | |
397 | addr = IXGBE_VFRE(0); | |
398 | val = bit1 << vf; | |
399 | } | |
400 | ||
401 | reg = IXGBE_READ_REG(hw, addr); | |
402 | ||
403 | if (on) | |
404 | reg |= val; | |
405 | else | |
406 | reg &= ~val; | |
407 | ||
408 | IXGBE_WRITE_REG(hw, addr, reg); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | int | |
9f95a23c | 414 | rte_pmd_ixgbe_set_vf_tx(uint16_t port, uint16_t vf, uint8_t on) |
11fdf7f2 TL |
415 | { |
416 | struct rte_eth_dev *dev; | |
417 | struct rte_pci_device *pci_dev; | |
418 | uint32_t reg, addr; | |
419 | uint32_t val; | |
420 | const uint8_t bit1 = 0x1; | |
421 | ||
422 | struct ixgbe_hw *hw; | |
423 | ||
424 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
425 | ||
426 | dev = &rte_eth_devices[port]; | |
9f95a23c | 427 | pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
11fdf7f2 TL |
428 | |
429 | if (!is_ixgbe_supported(dev)) | |
430 | return -ENOTSUP; | |
431 | ||
432 | if (vf >= pci_dev->max_vfs) | |
433 | return -EINVAL; | |
434 | ||
435 | if (on > 1) | |
436 | return -EINVAL; | |
437 | ||
438 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
439 | if (ixgbe_vt_check(hw) < 0) | |
440 | return -ENOTSUP; | |
441 | ||
442 | /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */ | |
443 | if (vf >= 32) { | |
444 | addr = IXGBE_VFTE(1); | |
445 | val = bit1 << (vf - 32); | |
446 | } else { | |
447 | addr = IXGBE_VFTE(0); | |
448 | val = bit1 << vf; | |
449 | } | |
450 | ||
451 | reg = IXGBE_READ_REG(hw, addr); | |
452 | ||
453 | if (on) | |
454 | reg |= val; | |
455 | else | |
456 | reg &= ~val; | |
457 | ||
458 | IXGBE_WRITE_REG(hw, addr, reg); | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | int | |
9f95a23c | 464 | rte_pmd_ixgbe_set_vf_vlan_filter(uint16_t port, uint16_t vlan, |
11fdf7f2 TL |
465 | uint64_t vf_mask, uint8_t vlan_on) |
466 | { | |
467 | struct rte_eth_dev *dev; | |
468 | int ret = 0; | |
469 | uint16_t vf_idx; | |
470 | struct ixgbe_hw *hw; | |
471 | ||
472 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
473 | ||
474 | dev = &rte_eth_devices[port]; | |
475 | ||
476 | if (!is_ixgbe_supported(dev)) | |
477 | return -ENOTSUP; | |
478 | ||
479 | if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0)) | |
480 | return -EINVAL; | |
481 | ||
482 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
483 | if (ixgbe_vt_check(hw) < 0) | |
484 | return -ENOTSUP; | |
485 | ||
486 | for (vf_idx = 0; vf_idx < 64; vf_idx++) { | |
487 | if (vf_mask & ((uint64_t)(1ULL << vf_idx))) { | |
488 | ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx, | |
489 | vlan_on, false); | |
490 | if (ret < 0) | |
491 | return ret; | |
492 | } | |
493 | } | |
494 | ||
495 | return ret; | |
496 | } | |
497 | ||
498 | int | |
9f95a23c | 499 | rte_pmd_ixgbe_set_vf_rate_limit(uint16_t port, uint16_t vf, |
11fdf7f2 TL |
500 | uint16_t tx_rate, uint64_t q_msk) |
501 | { | |
502 | struct rte_eth_dev *dev; | |
503 | ||
504 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
505 | ||
506 | dev = &rte_eth_devices[port]; | |
507 | ||
508 | if (!is_ixgbe_supported(dev)) | |
509 | return -ENOTSUP; | |
510 | ||
511 | return ixgbe_set_vf_rate_limit(dev, vf, tx_rate, q_msk); | |
512 | } | |
513 | ||
514 | int | |
9f95a23c | 515 | rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp) |
11fdf7f2 TL |
516 | { |
517 | struct ixgbe_hw *hw; | |
518 | struct rte_eth_dev *dev; | |
519 | uint32_t ctrl; | |
520 | ||
521 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
522 | ||
523 | dev = &rte_eth_devices[port]; | |
524 | ||
525 | if (!is_ixgbe_supported(dev)) | |
526 | return -ENOTSUP; | |
527 | ||
528 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
529 | ||
530 | /* Stop the data paths */ | |
531 | if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS) | |
532 | return -ENOTSUP; | |
533 | /** | |
534 | * Workaround: | |
535 | * As no ixgbe_disable_sec_rx_path equivalent is | |
536 | * implemented for tx in the base code, and we are | |
537 | * not allowed to modify the base code in DPDK, so | |
538 | * just call the hand-written one directly for now. | |
539 | * The hardware support has been checked by | |
540 | * ixgbe_disable_sec_rx_path(). | |
541 | */ | |
542 | ixgbe_disable_sec_tx_path_generic(hw); | |
543 | ||
544 | /* Enable Ethernet CRC (required by MACsec offload) */ | |
545 | ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
546 | ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; | |
547 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); | |
548 | ||
549 | /* Enable the TX and RX crypto engines */ | |
550 | ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); | |
551 | ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; | |
552 | IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); | |
553 | ||
554 | ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); | |
555 | ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; | |
556 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); | |
557 | ||
558 | ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
559 | ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; | |
560 | ctrl |= 0x3; | |
561 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); | |
562 | ||
563 | /* Enable SA lookup */ | |
564 | ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); | |
565 | ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; | |
566 | ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : | |
567 | IXGBE_LSECTXCTRL_AUTH; | |
568 | ctrl |= IXGBE_LSECTXCTRL_AISCI; | |
569 | ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; | |
570 | ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; | |
571 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); | |
572 | ||
573 | ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); | |
574 | ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; | |
575 | ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; | |
576 | ctrl &= ~IXGBE_LSECRXCTRL_PLSH; | |
577 | if (rp) | |
578 | ctrl |= IXGBE_LSECRXCTRL_RP; | |
579 | else | |
580 | ctrl &= ~IXGBE_LSECRXCTRL_RP; | |
581 | IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); | |
582 | ||
583 | /* Start the data paths */ | |
584 | ixgbe_enable_sec_rx_path(hw); | |
585 | /** | |
586 | * Workaround: | |
587 | * As no ixgbe_enable_sec_rx_path equivalent is | |
588 | * implemented for tx in the base code, and we are | |
589 | * not allowed to modify the base code in DPDK, so | |
590 | * just call the hand-written one directly for now. | |
591 | */ | |
592 | ixgbe_enable_sec_tx_path_generic(hw); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | int | |
9f95a23c | 598 | rte_pmd_ixgbe_macsec_disable(uint16_t port) |
11fdf7f2 TL |
599 | { |
600 | struct ixgbe_hw *hw; | |
601 | struct rte_eth_dev *dev; | |
602 | uint32_t ctrl; | |
603 | ||
604 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
605 | ||
606 | dev = &rte_eth_devices[port]; | |
607 | ||
608 | if (!is_ixgbe_supported(dev)) | |
609 | return -ENOTSUP; | |
610 | ||
611 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
612 | ||
613 | /* Stop the data paths */ | |
614 | if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS) | |
615 | return -ENOTSUP; | |
616 | /** | |
617 | * Workaround: | |
618 | * As no ixgbe_disable_sec_rx_path equivalent is | |
619 | * implemented for tx in the base code, and we are | |
620 | * not allowed to modify the base code in DPDK, so | |
621 | * just call the hand-written one directly for now. | |
622 | * The hardware support has been checked by | |
623 | * ixgbe_disable_sec_rx_path(). | |
624 | */ | |
625 | ixgbe_disable_sec_tx_path_generic(hw); | |
626 | ||
627 | /* Disable the TX and RX crypto engines */ | |
628 | ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); | |
629 | ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; | |
630 | IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); | |
631 | ||
632 | ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); | |
633 | ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; | |
634 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); | |
635 | ||
636 | /* Disable SA lookup */ | |
637 | ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); | |
638 | ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; | |
639 | ctrl |= IXGBE_LSECTXCTRL_DISABLE; | |
640 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); | |
641 | ||
642 | ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); | |
643 | ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; | |
644 | ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; | |
645 | IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); | |
646 | ||
647 | /* Start the data paths */ | |
648 | ixgbe_enable_sec_rx_path(hw); | |
649 | /** | |
650 | * Workaround: | |
651 | * As no ixgbe_enable_sec_rx_path equivalent is | |
652 | * implemented for tx in the base code, and we are | |
653 | * not allowed to modify the base code in DPDK, so | |
654 | * just call the hand-written one directly for now. | |
655 | */ | |
656 | ixgbe_enable_sec_tx_path_generic(hw); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | int | |
9f95a23c | 662 | rte_pmd_ixgbe_macsec_config_txsc(uint16_t port, uint8_t *mac) |
11fdf7f2 TL |
663 | { |
664 | struct ixgbe_hw *hw; | |
665 | struct rte_eth_dev *dev; | |
666 | uint32_t ctrl; | |
667 | ||
668 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
669 | ||
670 | dev = &rte_eth_devices[port]; | |
671 | ||
672 | if (!is_ixgbe_supported(dev)) | |
673 | return -ENOTSUP; | |
674 | ||
675 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
676 | ||
677 | ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24); | |
678 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl); | |
679 | ||
680 | ctrl = mac[4] | (mac[5] << 8); | |
681 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | int | |
9f95a23c | 687 | rte_pmd_ixgbe_macsec_config_rxsc(uint16_t port, uint8_t *mac, uint16_t pi) |
11fdf7f2 TL |
688 | { |
689 | struct ixgbe_hw *hw; | |
690 | struct rte_eth_dev *dev; | |
691 | uint32_t ctrl; | |
692 | ||
693 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
694 | ||
695 | dev = &rte_eth_devices[port]; | |
696 | ||
697 | if (!is_ixgbe_supported(dev)) | |
698 | return -ENOTSUP; | |
699 | ||
700 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
701 | ||
702 | ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24); | |
703 | IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl); | |
704 | ||
705 | pi = rte_cpu_to_be_16(pi); | |
706 | ctrl = mac[4] | (mac[5] << 8) | (pi << 16); | |
707 | IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl); | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | int | |
9f95a23c | 713 | rte_pmd_ixgbe_macsec_select_txsa(uint16_t port, uint8_t idx, uint8_t an, |
11fdf7f2 TL |
714 | uint32_t pn, uint8_t *key) |
715 | { | |
716 | struct ixgbe_hw *hw; | |
717 | struct rte_eth_dev *dev; | |
718 | uint32_t ctrl, i; | |
719 | ||
720 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
721 | ||
722 | dev = &rte_eth_devices[port]; | |
723 | ||
724 | if (!is_ixgbe_supported(dev)) | |
725 | return -ENOTSUP; | |
726 | ||
727 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
728 | ||
729 | if (idx != 0 && idx != 1) | |
730 | return -EINVAL; | |
731 | ||
732 | if (an >= 4) | |
733 | return -EINVAL; | |
734 | ||
735 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
736 | ||
737 | /* Set the PN and key */ | |
738 | pn = rte_cpu_to_be_32(pn); | |
739 | if (idx == 0) { | |
740 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn); | |
741 | ||
742 | for (i = 0; i < 4; i++) { | |
743 | ctrl = (key[i * 4 + 0] << 0) | | |
744 | (key[i * 4 + 1] << 8) | | |
745 | (key[i * 4 + 2] << 16) | | |
746 | (key[i * 4 + 3] << 24); | |
747 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl); | |
748 | } | |
749 | } else { | |
750 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn); | |
751 | ||
752 | for (i = 0; i < 4; i++) { | |
753 | ctrl = (key[i * 4 + 0] << 0) | | |
754 | (key[i * 4 + 1] << 8) | | |
755 | (key[i * 4 + 2] << 16) | | |
756 | (key[i * 4 + 3] << 24); | |
757 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl); | |
758 | } | |
759 | } | |
760 | ||
761 | /* Set AN and select the SA */ | |
762 | ctrl = (an << idx * 2) | (idx << 4); | |
763 | IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | int | |
9f95a23c | 769 | rte_pmd_ixgbe_macsec_select_rxsa(uint16_t port, uint8_t idx, uint8_t an, |
11fdf7f2 TL |
770 | uint32_t pn, uint8_t *key) |
771 | { | |
772 | struct ixgbe_hw *hw; | |
773 | struct rte_eth_dev *dev; | |
774 | uint32_t ctrl, i; | |
775 | ||
776 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
777 | ||
778 | dev = &rte_eth_devices[port]; | |
779 | ||
780 | if (!is_ixgbe_supported(dev)) | |
781 | return -ENOTSUP; | |
782 | ||
783 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
784 | ||
785 | if (idx != 0 && idx != 1) | |
786 | return -EINVAL; | |
787 | ||
788 | if (an >= 4) | |
789 | return -EINVAL; | |
790 | ||
791 | /* Set the PN */ | |
792 | pn = rte_cpu_to_be_32(pn); | |
793 | IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn); | |
794 | ||
795 | /* Set the key */ | |
796 | for (i = 0; i < 4; i++) { | |
797 | ctrl = (key[i * 4 + 0] << 0) | | |
798 | (key[i * 4 + 1] << 8) | | |
799 | (key[i * 4 + 2] << 16) | | |
800 | (key[i * 4 + 3] << 24); | |
801 | IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl); | |
802 | } | |
803 | ||
804 | /* Set the AN and validate the SA */ | |
805 | ctrl = an | (1 << 2); | |
806 | IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl); | |
807 | ||
808 | return 0; | |
809 | } | |
810 | ||
811 | int | |
9f95a23c | 812 | rte_pmd_ixgbe_set_tc_bw_alloc(uint16_t port, |
11fdf7f2 TL |
813 | uint8_t tc_num, |
814 | uint8_t *bw_weight) | |
815 | { | |
816 | struct rte_eth_dev *dev; | |
817 | struct ixgbe_dcb_config *dcb_config; | |
818 | struct ixgbe_dcb_tc_config *tc; | |
819 | struct rte_eth_conf *eth_conf; | |
820 | struct ixgbe_bw_conf *bw_conf; | |
821 | uint8_t i; | |
822 | uint8_t nb_tcs; | |
823 | uint16_t sum; | |
824 | ||
825 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
826 | ||
827 | dev = &rte_eth_devices[port]; | |
828 | ||
829 | if (!is_ixgbe_supported(dev)) | |
830 | return -ENOTSUP; | |
831 | ||
832 | if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) { | |
833 | PMD_DRV_LOG(ERR, "TCs should be no more than %d.", | |
834 | IXGBE_DCB_MAX_TRAFFIC_CLASS); | |
835 | return -EINVAL; | |
836 | } | |
837 | ||
838 | dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); | |
839 | bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private); | |
840 | eth_conf = &dev->data->dev_conf; | |
841 | ||
842 | if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { | |
843 | nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs; | |
844 | } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { | |
845 | if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools == | |
846 | ETH_32_POOLS) | |
847 | nb_tcs = ETH_4_TCS; | |
848 | else | |
849 | nb_tcs = ETH_8_TCS; | |
850 | } else { | |
851 | nb_tcs = 1; | |
852 | } | |
853 | ||
854 | if (nb_tcs != tc_num) { | |
855 | PMD_DRV_LOG(ERR, | |
856 | "Weight should be set for all %d enabled TCs.", | |
857 | nb_tcs); | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
861 | sum = 0; | |
862 | for (i = 0; i < nb_tcs; i++) | |
863 | sum += bw_weight[i]; | |
864 | if (sum != 100) { | |
865 | PMD_DRV_LOG(ERR, | |
866 | "The summary of the TC weight should be 100."); | |
867 | return -EINVAL; | |
868 | } | |
869 | ||
870 | for (i = 0; i < nb_tcs; i++) { | |
871 | tc = &dcb_config->tc_config[i]; | |
872 | tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i]; | |
873 | } | |
874 | for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { | |
875 | tc = &dcb_config->tc_config[i]; | |
876 | tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0; | |
877 | } | |
878 | ||
879 | bw_conf->tc_num = nb_tcs; | |
880 | ||
881 | return 0; | |
882 | } | |
9f95a23c TL |
883 | |
884 | int __rte_experimental | |
885 | rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable) | |
886 | { | |
887 | struct ixgbe_hw *hw; | |
888 | struct rte_eth_dev *dev; | |
889 | uint32_t fctrl; | |
890 | ||
891 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
892 | dev = &rte_eth_devices[port]; | |
893 | if (!is_ixgbe_supported(dev)) | |
894 | return -ENOTSUP; | |
895 | ||
896 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
897 | if (!hw) | |
898 | return -ENOTSUP; | |
899 | ||
900 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
901 | ||
902 | /* If 'enable' set the SBP bit else clear it */ | |
903 | if (enable) | |
904 | fctrl |= IXGBE_FCTRL_SBP; | |
905 | else | |
906 | fctrl &= ~(IXGBE_FCTRL_SBP); | |
907 | ||
908 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
909 | return 0; | |
910 | } | |
911 | ||
912 | #ifdef RTE_LIBRTE_IXGBE_BYPASS | |
913 | int | |
914 | rte_pmd_ixgbe_bypass_init(uint16_t port_id) | |
915 | { | |
916 | struct rte_eth_dev *dev; | |
917 | ||
918 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
919 | ||
920 | dev = &rte_eth_devices[port_id]; | |
921 | if (!is_ixgbe_supported(dev)) | |
922 | return -ENOTSUP; | |
923 | ||
924 | ixgbe_bypass_init(dev); | |
925 | return 0; | |
926 | } | |
927 | ||
928 | int | |
929 | rte_pmd_ixgbe_bypass_state_show(uint16_t port_id, uint32_t *state) | |
930 | { | |
931 | struct rte_eth_dev *dev; | |
932 | ||
933 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
934 | ||
935 | dev = &rte_eth_devices[port_id]; | |
936 | if (!is_ixgbe_supported(dev)) | |
937 | return -ENOTSUP; | |
938 | ||
939 | return ixgbe_bypass_state_show(dev, state); | |
940 | } | |
941 | ||
942 | int | |
943 | rte_pmd_ixgbe_bypass_state_set(uint16_t port_id, uint32_t *new_state) | |
944 | { | |
945 | struct rte_eth_dev *dev; | |
946 | ||
947 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
948 | ||
949 | dev = &rte_eth_devices[port_id]; | |
950 | if (!is_ixgbe_supported(dev)) | |
951 | return -ENOTSUP; | |
952 | ||
953 | return ixgbe_bypass_state_store(dev, new_state); | |
954 | } | |
955 | ||
956 | int | |
957 | rte_pmd_ixgbe_bypass_event_show(uint16_t port_id, | |
958 | uint32_t event, | |
959 | uint32_t *state) | |
960 | { | |
961 | struct rte_eth_dev *dev; | |
962 | ||
963 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
964 | ||
965 | dev = &rte_eth_devices[port_id]; | |
966 | if (!is_ixgbe_supported(dev)) | |
967 | return -ENOTSUP; | |
968 | ||
969 | return ixgbe_bypass_event_show(dev, event, state); | |
970 | } | |
971 | ||
972 | int | |
973 | rte_pmd_ixgbe_bypass_event_store(uint16_t port_id, | |
974 | uint32_t event, | |
975 | uint32_t state) | |
976 | { | |
977 | struct rte_eth_dev *dev; | |
978 | ||
979 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
980 | ||
981 | dev = &rte_eth_devices[port_id]; | |
982 | if (!is_ixgbe_supported(dev)) | |
983 | return -ENOTSUP; | |
984 | ||
985 | return ixgbe_bypass_event_store(dev, event, state); | |
986 | } | |
987 | ||
988 | int | |
989 | rte_pmd_ixgbe_bypass_wd_timeout_store(uint16_t port_id, uint32_t timeout) | |
990 | { | |
991 | struct rte_eth_dev *dev; | |
992 | ||
993 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
994 | ||
995 | dev = &rte_eth_devices[port_id]; | |
996 | if (!is_ixgbe_supported(dev)) | |
997 | return -ENOTSUP; | |
998 | ||
999 | return ixgbe_bypass_wd_timeout_store(dev, timeout); | |
1000 | } | |
1001 | ||
1002 | int | |
1003 | rte_pmd_ixgbe_bypass_ver_show(uint16_t port_id, uint32_t *ver) | |
1004 | { | |
1005 | struct rte_eth_dev *dev; | |
1006 | ||
1007 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
1008 | ||
1009 | dev = &rte_eth_devices[port_id]; | |
1010 | if (!is_ixgbe_supported(dev)) | |
1011 | return -ENOTSUP; | |
1012 | ||
1013 | return ixgbe_bypass_ver_show(dev, ver); | |
1014 | } | |
1015 | ||
1016 | int | |
1017 | rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port_id, uint32_t *wd_timeout) | |
1018 | { | |
1019 | struct rte_eth_dev *dev; | |
1020 | ||
1021 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
1022 | ||
1023 | dev = &rte_eth_devices[port_id]; | |
1024 | if (!is_ixgbe_supported(dev)) | |
1025 | return -ENOTSUP; | |
1026 | ||
1027 | return ixgbe_bypass_wd_timeout_show(dev, wd_timeout); | |
1028 | } | |
1029 | ||
1030 | int | |
1031 | rte_pmd_ixgbe_bypass_wd_reset(uint16_t port_id) | |
1032 | { | |
1033 | struct rte_eth_dev *dev; | |
1034 | ||
1035 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); | |
1036 | ||
1037 | dev = &rte_eth_devices[port_id]; | |
1038 | if (!is_ixgbe_supported(dev)) | |
1039 | return -ENOTSUP; | |
1040 | ||
1041 | return ixgbe_bypass_wd_reset(dev); | |
1042 | } | |
1043 | #endif | |
1044 | ||
1045 | /** | |
1046 | * rte_pmd_ixgbe_acquire_swfw - Acquire SWFW semaphore | |
1047 | * @hw: pointer to hardware structure | |
1048 | * @mask: Mask to specify which semaphore to acquire | |
1049 | * | |
1050 | * Acquires the SWFW semaphore and get the shared phy token as needed | |
1051 | */ | |
1052 | STATIC s32 rte_pmd_ixgbe_acquire_swfw(struct ixgbe_hw *hw, u32 mask) | |
1053 | { | |
1054 | int retries = FW_PHY_TOKEN_RETRIES; | |
1055 | s32 status = IXGBE_SUCCESS; | |
1056 | ||
1057 | while (--retries) { | |
1058 | status = ixgbe_acquire_swfw_semaphore(hw, mask); | |
1059 | if (status) { | |
1060 | PMD_DRV_LOG(ERR, "Get SWFW sem failed, Status = %d\n", | |
1061 | status); | |
1062 | return status; | |
1063 | } | |
1064 | status = ixgbe_get_phy_token(hw); | |
1065 | if (status == IXGBE_SUCCESS) | |
1066 | return IXGBE_SUCCESS; | |
1067 | ||
1068 | if (status == IXGBE_ERR_TOKEN_RETRY) | |
1069 | PMD_DRV_LOG(ERR, "Get PHY token failed, Status = %d\n", | |
1070 | status); | |
1071 | ||
1072 | ixgbe_release_swfw_semaphore(hw, mask); | |
1073 | if (status != IXGBE_ERR_TOKEN_RETRY) { | |
1074 | PMD_DRV_LOG(ERR, | |
1075 | "Retry get PHY token failed, Status=%d\n", | |
1076 | status); | |
1077 | return status; | |
1078 | } | |
1079 | } | |
1080 | PMD_DRV_LOG(ERR, "swfw acquisition retries failed!: PHY ID = 0x%08X\n", | |
1081 | hw->phy.id); | |
1082 | return status; | |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * rte_pmd_ixgbe_release_swfw_sync - Release SWFW semaphore | |
1087 | * @hw: pointer to hardware structure | |
1088 | * @mask: Mask to specify which semaphore to release | |
1089 | * | |
1090 | * Releases the SWFW semaphore and puts the shared phy token as needed | |
1091 | */ | |
1092 | STATIC void rte_pmd_ixgbe_release_swfw(struct ixgbe_hw *hw, u32 mask) | |
1093 | { | |
1094 | ixgbe_put_phy_token(hw); | |
1095 | ixgbe_release_swfw_semaphore(hw, mask); | |
1096 | } | |
1097 | ||
1098 | int __rte_experimental | |
1099 | rte_pmd_ixgbe_mdio_lock(uint16_t port) | |
1100 | { | |
1101 | struct ixgbe_hw *hw; | |
1102 | struct rte_eth_dev *dev; | |
1103 | u32 swfw_mask; | |
1104 | ||
1105 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
1106 | dev = &rte_eth_devices[port]; | |
1107 | if (!is_ixgbe_supported(dev)) | |
1108 | return -ENOTSUP; | |
1109 | ||
1110 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
1111 | if (!hw) | |
1112 | return -ENOTSUP; | |
1113 | ||
1114 | if (hw->bus.lan_id) | |
1115 | swfw_mask = IXGBE_GSSR_PHY1_SM; | |
1116 | else | |
1117 | swfw_mask = IXGBE_GSSR_PHY0_SM; | |
1118 | ||
1119 | if (rte_pmd_ixgbe_acquire_swfw(hw, swfw_mask)) | |
1120 | return IXGBE_ERR_SWFW_SYNC; | |
1121 | ||
1122 | return IXGBE_SUCCESS; | |
1123 | } | |
1124 | ||
1125 | int __rte_experimental | |
1126 | rte_pmd_ixgbe_mdio_unlock(uint16_t port) | |
1127 | { | |
1128 | struct rte_eth_dev *dev; | |
1129 | struct ixgbe_hw *hw; | |
1130 | u32 swfw_mask; | |
1131 | ||
1132 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
1133 | ||
1134 | dev = &rte_eth_devices[port]; | |
1135 | if (!is_ixgbe_supported(dev)) | |
1136 | return -ENOTSUP; | |
1137 | ||
1138 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
1139 | if (!hw) | |
1140 | return -ENOTSUP; | |
1141 | ||
1142 | if (hw->bus.lan_id) | |
1143 | swfw_mask = IXGBE_GSSR_PHY1_SM; | |
1144 | else | |
1145 | swfw_mask = IXGBE_GSSR_PHY0_SM; | |
1146 | ||
1147 | rte_pmd_ixgbe_release_swfw(hw, swfw_mask); | |
1148 | ||
1149 | return IXGBE_SUCCESS; | |
1150 | } | |
1151 | ||
1152 | int __rte_experimental | |
1153 | rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr, | |
1154 | uint32_t dev_type, uint16_t *phy_data) | |
1155 | { | |
1156 | struct ixgbe_hw *hw; | |
1157 | struct rte_eth_dev *dev; | |
1158 | u32 i, data, command; | |
1159 | ||
1160 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
1161 | dev = &rte_eth_devices[port]; | |
1162 | if (!is_ixgbe_supported(dev)) | |
1163 | return -ENOTSUP; | |
1164 | ||
1165 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
1166 | if (!hw) | |
1167 | return -ENOTSUP; | |
1168 | ||
1169 | /* Setup and write the read command */ | |
1170 | command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | | |
1171 | (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) | | |
1172 | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC | | |
1173 | IXGBE_MSCA_MDI_COMMAND; | |
1174 | ||
1175 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |
1176 | ||
1177 | /* Check every 10 usec to see if the access completed. | |
1178 | * The MDI Command bit will clear when the operation is | |
1179 | * complete | |
1180 | */ | |
1181 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { | |
1182 | usec_delay(10); | |
1183 | ||
1184 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
1185 | if (!(command & IXGBE_MSCA_MDI_COMMAND)) | |
1186 | break; | |
1187 | } | |
1188 | if (command & IXGBE_MSCA_MDI_COMMAND) | |
1189 | return IXGBE_ERR_PHY; | |
1190 | ||
1191 | /* Read operation is complete. Get the data from MSRWD */ | |
1192 | data = IXGBE_READ_REG(hw, IXGBE_MSRWD); | |
1193 | data >>= IXGBE_MSRWD_READ_DATA_SHIFT; | |
1194 | *phy_data = (u16)data; | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | int __rte_experimental | |
1200 | rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr, | |
1201 | uint32_t dev_type, uint16_t phy_data) | |
1202 | { | |
1203 | struct ixgbe_hw *hw; | |
1204 | u32 i, command; | |
1205 | struct rte_eth_dev *dev; | |
1206 | ||
1207 | RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); | |
1208 | dev = &rte_eth_devices[port]; | |
1209 | if (!is_ixgbe_supported(dev)) | |
1210 | return -ENOTSUP; | |
1211 | ||
1212 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); | |
1213 | if (!hw) | |
1214 | return -ENOTSUP; | |
1215 | ||
1216 | /* Put the data in the MDI single read and write data register*/ | |
1217 | IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); | |
1218 | ||
1219 | /* Setup and write the write command */ | |
1220 | command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | | |
1221 | (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) | | |
1222 | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | | |
1223 | IXGBE_MSCA_MDI_COMMAND; | |
1224 | ||
1225 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |
1226 | ||
1227 | /* Check every 10 usec to see if the access completed. | |
1228 | * The MDI Command bit will clear when the operation is | |
1229 | * complete | |
1230 | */ | |
1231 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { | |
1232 | usec_delay(10); | |
1233 | ||
1234 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
1235 | if (!(command & IXGBE_MSCA_MDI_COMMAND)) | |
1236 | break; | |
1237 | } | |
1238 | if (command & IXGBE_MSCA_MDI_COMMAND) { | |
1239 | ERROR_REPORT1(IXGBE_ERROR_POLLING, | |
1240 | "PHY write cmd didn't complete\n"); | |
1241 | return IXGBE_ERR_PHY; | |
1242 | } | |
1243 | return 0; | |
1244 | } |