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[ceph.git] / ceph / src / seastar / dpdk / drivers / net / qede / base / ecore_mcp_api.h
CommitLineData
9f95a23c
TL		 1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7c673cae 3 * All rights reserved.
9f95a23c 4 * www.cavium.com
7c673cae
FG		 5 */
6
7#ifndef __ECORE_MCP_API_H__
8#define __ECORE_MCP_API_H__
9
10#include "ecore_status.h"
11
12struct ecore_mcp_link_speed_params {
13 bool autoneg;
14 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */
15 u32 forced_speed; /* In Mb/s */
16};
17
18struct ecore_mcp_link_pause_params {
19 bool autoneg;
20 bool forced_rx;
21 bool forced_tx;
22};
23
9f95a23c
TL		 24enum ecore_mcp_eee_mode {
25 ECORE_MCP_EEE_DISABLED,
26 ECORE_MCP_EEE_ENABLED,
27 ECORE_MCP_EEE_UNSUPPORTED
28};
29
30struct ecore_link_eee_params {
31 u32 tx_lpi_timer;
32#define ECORE_EEE_1G_ADV (1 << 0)
33#define ECORE_EEE_10G_ADV (1 << 1)
34 /* Capabilities are represented using ECORE_EEE_*_ADV values */
35 u8 adv_caps;
36 u8 lp_adv_caps;
37 bool enable;
38 bool tx_lpi_enable;
39};
40
7c673cae
FG		 41struct ecore_mcp_link_params {
42 struct ecore_mcp_link_speed_params speed;
43 struct ecore_mcp_link_pause_params pause;
44 u32 loopback_mode; /* in PMM_LOOPBACK values */
9f95a23c 45 struct ecore_link_eee_params eee;
7c673cae
FG		 46};
47
48struct ecore_mcp_link_capabilities {
49 u32 speed_capabilities;
50 bool default_speed_autoneg; /* In Mb/s */
51 u32 default_speed; /* In Mb/s */
9f95a23c
TL		 52 enum ecore_mcp_eee_mode default_eee;
53 u32 eee_lpi_timer;
54 u8 eee_speed_caps;
7c673cae
FG		 55};
56
57struct ecore_mcp_link_state {
58 bool link_up;
59
7c673cae 60 u32 min_pf_rate; /* In Mb/s */
9f95a23c
TL		 61
62 /* Actual link speed in Mb/s */
63 u32 line_speed;
64
65 /* PF max speed in MB/s, deduced from line_speed
66 * according to PF max bandwidth configuration.
67 */
68 u32 speed;
7c673cae
FG		 69 bool full_duplex;
70
71 bool an;
72 bool an_complete;
73 bool parallel_detection;
74 bool pfc_enabled;
75
76#define ECORE_LINK_PARTNER_SPEED_1G_HD (1 << 0)
77#define ECORE_LINK_PARTNER_SPEED_1G_FD (1 << 1)
78#define ECORE_LINK_PARTNER_SPEED_10G (1 << 2)
79#define ECORE_LINK_PARTNER_SPEED_20G (1 << 3)
80#define ECORE_LINK_PARTNER_SPEED_25G (1 << 4)
81#define ECORE_LINK_PARTNER_SPEED_40G (1 << 5)
82#define ECORE_LINK_PARTNER_SPEED_50G (1 << 6)
83#define ECORE_LINK_PARTNER_SPEED_100G (1 << 7)
84 u32 partner_adv_speed;
85
86 bool partner_tx_flow_ctrl_en;
87 bool partner_rx_flow_ctrl_en;
88
89#define ECORE_LINK_PARTNER_SYMMETRIC_PAUSE (1)
90#define ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE (2)
91#define ECORE_LINK_PARTNER_BOTH_PAUSE (3)
92 u8 partner_adv_pause;
93
94 bool sfp_tx_fault;
9f95a23c
TL		 95
96 bool eee_active;
97 u8 eee_adv_caps;
98 u8 eee_lp_adv_caps;
7c673cae
FG		 99};
100
101struct ecore_mcp_function_info {
102 u8 pause_on_host;
103
104 enum ecore_pci_personality protocol;
105
106 u8 bandwidth_min;
107 u8 bandwidth_max;
108
109 u8 mac[ETH_ALEN];
110
111 u64 wwn_port;
112 u64 wwn_node;
113
114#define ECORE_MCP_VLAN_UNSET (0xffff)
115 u16 ovlan;
11fdf7f2
TL		 116
117 u16 mtu;
7c673cae
FG		 118};
119
7c673cae
FG		 120#ifndef __EXTRACT__LINUX__
121enum ecore_nvm_images {
122 ECORE_NVM_IMAGE_ISCSI_CFG,
123 ECORE_NVM_IMAGE_FCOE_CFG,
124};
125#endif
126
127struct ecore_mcp_drv_version {
128 u32 version;
129 u8 name[MCP_DRV_VER_STR_SIZE - 4];
130};
131
132struct ecore_mcp_lan_stats {
133 u64 ucast_rx_pkts;
134 u64 ucast_tx_pkts;
135 u32 fcs_err;
136};
137
138#ifndef ECORE_PROTO_STATS
139#define ECORE_PROTO_STATS
140struct ecore_mcp_fcoe_stats {
141 u64 rx_pkts;
142 u64 tx_pkts;
143 u32 fcs_err;
144 u32 login_failure;
145};
146
147struct ecore_mcp_iscsi_stats {
148 u64 rx_pdus;
149 u64 tx_pdus;
150 u64 rx_bytes;
151 u64 tx_bytes;
152};
153
154struct ecore_mcp_rdma_stats {
155 u64 rx_pkts;
156 u64 tx_pkts;
157 u64 rx_bytes;
158 u64 tx_byts;
159};
160
161enum ecore_mcp_protocol_type {
162 ECORE_MCP_LAN_STATS,
163 ECORE_MCP_FCOE_STATS,
164 ECORE_MCP_ISCSI_STATS,
165 ECORE_MCP_RDMA_STATS
166};
167
168union ecore_mcp_protocol_stats {
169 struct ecore_mcp_lan_stats lan_stats;
170 struct ecore_mcp_fcoe_stats fcoe_stats;
171 struct ecore_mcp_iscsi_stats iscsi_stats;
172 struct ecore_mcp_rdma_stats rdma_stats;
173};
174#endif
175
7c673cae
FG		 176enum ecore_ov_client {
177 ECORE_OV_CLIENT_DRV,
11fdf7f2
TL		 178 ECORE_OV_CLIENT_USER,
179 ECORE_OV_CLIENT_VENDOR_SPEC
7c673cae
FG		 180};
181
182enum ecore_ov_driver_state {
183 ECORE_OV_DRIVER_STATE_NOT_LOADED,
184 ECORE_OV_DRIVER_STATE_DISABLED,
185 ECORE_OV_DRIVER_STATE_ACTIVE
186};
187
9f95a23c
TL		 188enum ecore_ov_eswitch {
189 ECORE_OV_ESWITCH_NONE,
190 ECORE_OV_ESWITCH_VEB,
191 ECORE_OV_ESWITCH_VEPA
192};
193
7c673cae
FG		 194#define ECORE_MAX_NPIV_ENTRIES 128
195#define ECORE_WWN_SIZE 8
196struct ecore_fc_npiv_tbl {
197 u32 count;
198 u8 wwpn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE];
199 u8 wwnn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE];
200};
201
202#ifndef __EXTRACT__LINUX__
203enum ecore_led_mode {
204 ECORE_LED_MODE_OFF,
205 ECORE_LED_MODE_ON,
206 ECORE_LED_MODE_RESTORE
207};
208#endif
209
210struct ecore_temperature_sensor {
211 u8 sensor_location;
212 u8 threshold_high;
213 u8 critical;
214 u8 current_temp;
215};
216
217#define ECORE_MAX_NUM_OF_SENSORS 7
218struct ecore_temperature_info {
219 u32 num_sensors;
220 struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS];
221};
222
223enum ecore_mba_img_idx {
224 ECORE_MBA_LEGACY_IDX,
225 ECORE_MBA_PCI3CLP_IDX,
226 ECORE_MBA_PCI3_IDX,
227 ECORE_MBA_FCODE_IDX,
228 ECORE_EFI_X86_IDX,
229 ECORE_EFI_IPF_IDX,
230 ECORE_EFI_EBC_IDX,
231 ECORE_EFI_X64_IDX,
232 ECORE_MAX_NUM_OF_ROMIMG
233};
234
235struct ecore_mba_vers {
236 u32 mba_vers[ECORE_MAX_NUM_OF_ROMIMG];
237};
238
11fdf7f2
TL		 239enum ecore_mfw_tlv_type {
240 ECORE_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */
241 ECORE_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */
242 ECORE_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */
243 ECORE_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */
244 ECORE_MFW_TLV_MAX = 0x16,
245};
246
247struct ecore_mfw_tlv_generic {
248 u16 feat_flags;
249 bool feat_flags_set;
250 u64 local_mac;
251 bool local_mac_set;
252 u64 additional_mac1;
253 bool additional_mac1_set;
254 u64 additional_mac2;
255 bool additional_mac2_set;
256 u8 drv_state;
257 bool drv_state_set;
258 u8 pxe_progress;
259 bool pxe_progress_set;
260 u64 rx_frames;
261 bool rx_frames_set;
262 u64 rx_bytes;
263 bool rx_bytes_set;
264 u64 tx_frames;
265 bool tx_frames_set;
266 u64 tx_bytes;
267 bool tx_bytes_set;
268};
269
270struct ecore_mfw_tlv_eth {
271 u16 lso_maxoff_size;
272 bool lso_maxoff_size_set;
273 u16 lso_minseg_size;
274 bool lso_minseg_size_set;
275 u8 prom_mode;
276 bool prom_mode_set;
277 u16 tx_descr_size;
278 bool tx_descr_size_set;
279 u16 rx_descr_size;
280 bool rx_descr_size_set;
281 u16 netq_count;
282 bool netq_count_set;
283 u32 tcp4_offloads;
284 bool tcp4_offloads_set;
285 u32 tcp6_offloads;
286 bool tcp6_offloads_set;
287 u16 tx_descr_qdepth;
288 bool tx_descr_qdepth_set;
289 u16 rx_descr_qdepth;
290 bool rx_descr_qdepth_set;
291 u8 iov_offload;
292 bool iov_offload_set;
293 u8 txqs_empty;
294 bool txqs_empty_set;
295 u8 rxqs_empty;
296 bool rxqs_empty_set;
297 u8 num_txqs_full;
298 bool num_txqs_full_set;
299 u8 num_rxqs_full;
300 bool num_rxqs_full_set;
301};
302
303struct ecore_mfw_tlv_fcoe {
304 u8 scsi_timeout;
305 bool scsi_timeout_set;
306 u32 rt_tov;
307 bool rt_tov_set;
308 u32 ra_tov;
309 bool ra_tov_set;
310 u32 ed_tov;
311 bool ed_tov_set;
312 u32 cr_tov;
313 bool cr_tov_set;
314 u8 boot_type;
315 bool boot_type_set;
316 u8 npiv_state;
317 bool npiv_state_set;
318 u32 num_npiv_ids;
319 bool num_npiv_ids_set;
320 u8 switch_name[8];
321 bool switch_name_set;
322 u16 switch_portnum;
323 bool switch_portnum_set;
324 u8 switch_portid[3];
325 bool switch_portid_set;
326 u8 vendor_name[8];
327 bool vendor_name_set;
328 u8 switch_model[8];
329 bool switch_model_set;
330 u8 switch_fw_version[8];
331 bool switch_fw_version_set;
332 u8 qos_pri;
333 bool qos_pri_set;
334 u8 port_alias[3];
335 bool port_alias_set;
336 u8 port_state;
337 bool port_state_set;
338 u16 fip_tx_descr_size;
339 bool fip_tx_descr_size_set;
340 u16 fip_rx_descr_size;
341 bool fip_rx_descr_size_set;
342 u16 link_failures;
343 bool link_failures_set;
344 u8 fcoe_boot_progress;
345 bool fcoe_boot_progress_set;
346 u64 rx_bcast;
347 bool rx_bcast_set;
348 u64 tx_bcast;
349 bool tx_bcast_set;
350 u16 fcoe_txq_depth;
351 bool fcoe_txq_depth_set;
352 u16 fcoe_rxq_depth;
353 bool fcoe_rxq_depth_set;
354 u64 fcoe_rx_frames;
355 bool fcoe_rx_frames_set;
356 u64 fcoe_rx_bytes;
357 bool fcoe_rx_bytes_set;
358 u64 fcoe_tx_frames;
359 bool fcoe_tx_frames_set;
360 u64 fcoe_tx_bytes;
361 bool fcoe_tx_bytes_set;
362 u16 crc_count;
363 bool crc_count_set;
364 u32 crc_err_src_fcid[5];
365 bool crc_err_src_fcid_set[5];
366 u8 crc_err_tstamp[5][14];
367 bool crc_err_tstamp_set[5];
368 u16 losync_err;
369 bool losync_err_set;
370 u16 losig_err;
371 bool losig_err_set;
372 u16 primtive_err;
373 bool primtive_err_set;
374 u16 disparity_err;
375 bool disparity_err_set;
376 u16 code_violation_err;
377 bool code_violation_err_set;
378 u32 flogi_param[4];
379 bool flogi_param_set[4];
380 u8 flogi_tstamp[14];
381 bool flogi_tstamp_set;
382 u32 flogi_acc_param[4];
383 bool flogi_acc_param_set[4];
384 u8 flogi_acc_tstamp[14];
385 bool flogi_acc_tstamp_set;
386 u32 flogi_rjt;
387 bool flogi_rjt_set;
388 u8 flogi_rjt_tstamp[14];
389 bool flogi_rjt_tstamp_set;
390 u32 fdiscs;
391 bool fdiscs_set;
392 u8 fdisc_acc;
393 bool fdisc_acc_set;
394 u8 fdisc_rjt;
395 bool fdisc_rjt_set;
396 u8 plogi;
397 bool plogi_set;
398 u8 plogi_acc;
399 bool plogi_acc_set;
400 u8 plogi_rjt;
401 bool plogi_rjt_set;
402 u32 plogi_dst_fcid[5];
403 bool plogi_dst_fcid_set[5];
404 u8 plogi_tstamp[5][14];
405 bool plogi_tstamp_set[5];
406 u32 plogi_acc_src_fcid[5];
407 bool plogi_acc_src_fcid_set[5];
408 u8 plogi_acc_tstamp[5][14];
409 bool plogi_acc_tstamp_set[5];
410 u8 tx_plogos;
411 bool tx_plogos_set;
412 u8 plogo_acc;
413 bool plogo_acc_set;
414 u8 plogo_rjt;
415 bool plogo_rjt_set;
416 u32 plogo_src_fcid[5];
417 bool plogo_src_fcid_set[5];
418 u8 plogo_tstamp[5][14];
419 bool plogo_tstamp_set[5];
420 u8 rx_logos;
421 bool rx_logos_set;
422 u8 tx_accs;
423 bool tx_accs_set;
424 u8 tx_prlis;
425 bool tx_prlis_set;
426 u8 rx_accs;
427 bool rx_accs_set;
428 u8 tx_abts;
429 bool tx_abts_set;
430 u8 rx_abts_acc;
431 bool rx_abts_acc_set;
432 u8 rx_abts_rjt;
433 bool rx_abts_rjt_set;
434 u32 abts_dst_fcid[5];
435 bool abts_dst_fcid_set[5];
436 u8 abts_tstamp[5][14];
437 bool abts_tstamp_set[5];
438 u8 rx_rscn;
439 bool rx_rscn_set;
440 u32 rx_rscn_nport[4];
441 bool rx_rscn_nport_set[4];
442 u8 tx_lun_rst;
443 bool tx_lun_rst_set;
444 u8 abort_task_sets;
445 bool abort_task_sets_set;
446 u8 tx_tprlos;
447 bool tx_tprlos_set;
448 u8 tx_nos;
449 bool tx_nos_set;
450 u8 rx_nos;
451 bool rx_nos_set;
452 u8 ols;
453 bool ols_set;
454 u8 lr;
455 bool lr_set;
456 u8 lrr;
457 bool lrr_set;
458 u8 tx_lip;
459 bool tx_lip_set;
460 u8 rx_lip;
461 bool rx_lip_set;
462 u8 eofa;
463 bool eofa_set;
464 u8 eofni;
465 bool eofni_set;
466 u8 scsi_chks;
467 bool scsi_chks_set;
468 u8 scsi_cond_met;
469 bool scsi_cond_met_set;
470 u8 scsi_busy;
471 bool scsi_busy_set;
472 u8 scsi_inter;
473 bool scsi_inter_set;
474 u8 scsi_inter_cond_met;
475 bool scsi_inter_cond_met_set;
476 u8 scsi_rsv_conflicts;
477 bool scsi_rsv_conflicts_set;
478 u8 scsi_tsk_full;
479 bool scsi_tsk_full_set;
480 u8 scsi_aca_active;
481 bool scsi_aca_active_set;
482 u8 scsi_tsk_abort;
483 bool scsi_tsk_abort_set;
484 u32 scsi_rx_chk[5];
485 bool scsi_rx_chk_set[5];
486 u8 scsi_chk_tstamp[5][14];
487 bool scsi_chk_tstamp_set[5];
488};
489
490struct ecore_mfw_tlv_iscsi {
491 u8 target_llmnr;
492 bool target_llmnr_set;
493 u8 header_digest;
494 bool header_digest_set;
495 u8 data_digest;
496 bool data_digest_set;
497 u8 auth_method;
498 bool auth_method_set;
499 u16 boot_taget_portal;
500 bool boot_taget_portal_set;
501 u16 frame_size;
502 bool frame_size_set;
503 u16 tx_desc_size;
504 bool tx_desc_size_set;
505 u16 rx_desc_size;
506 bool rx_desc_size_set;
507 u8 boot_progress;
508 bool boot_progress_set;
509 u16 tx_desc_qdepth;
510 bool tx_desc_qdepth_set;
511 u16 rx_desc_qdepth;
512 bool rx_desc_qdepth_set;
513 u64 rx_frames;
514 bool rx_frames_set;
515 u64 rx_bytes;
516 bool rx_bytes_set;
517 u64 tx_frames;
518 bool tx_frames_set;
519 u64 tx_bytes;
520 bool tx_bytes_set;
521};
522
523union ecore_mfw_tlv_data {
524 struct ecore_mfw_tlv_generic generic;
525 struct ecore_mfw_tlv_eth eth;
526 struct ecore_mfw_tlv_fcoe fcoe;
527 struct ecore_mfw_tlv_iscsi iscsi;
528};
529
9f95a23c
TL		 530enum ecore_hw_info_change {
531 ECORE_HW_INFO_CHANGE_OVLAN,
532};
533
7c673cae
FG		 534/**
535 * @brief - returns the link params of the hw function
536 *
537 * @param p_hwfn
538 *
539 * @returns pointer to link params
540 */
541struct ecore_mcp_link_params *ecore_mcp_get_link_params(struct ecore_hwfn *);
542
543/**
544 * @brief - return the link state of the hw function
545 *
546 * @param p_hwfn
547 *
548 * @returns pointer to link state
549 */
550struct ecore_mcp_link_state *ecore_mcp_get_link_state(struct ecore_hwfn *);
551
552/**
553 * @brief - return the link capabilities of the hw function
554 *
555 * @param p_hwfn
556 *
557 * @returns pointer to link capabilities
558 */
559struct ecore_mcp_link_capabilities
560*ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn);
561
562/**
9f95a23c 563 * @brief Request the MFW to set the link according to 'link_input'.
7c673cae
FG		 564 *
565 * @param p_hwfn
566 * @param p_ptt
567 * @param b_up - raise link if `true'. Reset link if `false'.
568 *
569 * @return enum _ecore_status_t
570 */
571enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
572 struct ecore_ptt *p_ptt,
573 bool b_up);
574
575/**
576 * @brief Get the management firmware version value
577 *
578 * @param p_hwfn
579 * @param p_ptt
580 * @param p_mfw_ver - mfw version value
581 * @param p_running_bundle_id - image id in nvram; Optional.
582 *
583 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
584 */
585enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
586 struct ecore_ptt *p_ptt,
587 u32 *p_mfw_ver,
588 u32 *p_running_bundle_id);
589
590/**
591 * @brief Get media type value of the port.
592 *
593 * @param p_dev - ecore dev pointer
9f95a23c 594 * @param p_ptt
7c673cae
FG		 595 * @param mfw_ver - media type value
596 *
597 * @return enum _ecore_status_t -
598 * ECORE_SUCCESS - Operation was successful.
599 * ECORE_BUSY - Operation failed
600 */
9f95a23c
TL		 601enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
602 struct ecore_ptt *p_ptt,
603 u32 *media_type);
604
605/**
606 * @brief Get transceiver data of the port.
607 *
608 * @param p_dev - ecore dev pointer
609 * @param p_ptt
610 * @param p_transceiver_state - transceiver state.
611 * @param p_transceiver_type - media type value
612 *
613 * @return enum _ecore_status_t -
614 * ECORE_SUCCESS - Operation was successful.
615 * ECORE_BUSY - Operation failed
616 */
617enum _ecore_status_t ecore_mcp_get_transceiver_data(struct ecore_hwfn *p_hwfn,
618 struct ecore_ptt *p_ptt,
619 u32 *p_transceiver_state,
620 u32 *p_tranceiver_type);
621
622/**
623 * @brief Get transceiver supported speed mask.
624 *
625 * @param p_dev - ecore dev pointer
626 * @param p_ptt
627 * @param p_speed_mask - Bit mask of all supported speeds.
628 *
629 * @return enum _ecore_status_t -
630 * ECORE_SUCCESS - Operation was successful.
631 * ECORE_BUSY - Operation failed
632 */
633
634enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn,
635 struct ecore_ptt *p_ptt,
636 u32 *p_speed_mask);
637
638/**
639 * @brief Get board configuration.
640 *
641 * @param p_dev - ecore dev pointer
642 * @param p_ptt
643 * @param p_board_config - Board config.
644 *
645 * @return enum _ecore_status_t -
646 * ECORE_SUCCESS - Operation was successful.
647 * ECORE_BUSY - Operation failed
648 */
649enum _ecore_status_t ecore_mcp_get_board_config(struct ecore_hwfn *p_hwfn,
650 struct ecore_ptt *p_ptt,
651 u32 *p_board_config);
7c673cae
FG		 652
653/**
654 * @brief - Sends a command to the MCP mailbox.
655 *
656 * @param p_hwfn - hw function
657 * @param p_ptt - PTT required for register access
658 * @param cmd - command to be sent to the MCP
9f95a23c
TL		 659 * @param param - Optional param
660 * @param o_mcp_resp - The MCP response code (exclude sequence)
661 * @param o_mcp_param - Optional parameter provided by the MCP response
7c673cae
FG		 662 *
663 * @return enum _ecore_status_t -
664 * ECORE_SUCCESS - operation was successful
665 * ECORE_BUSY - operation failed
666 */
667enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
668 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
669 u32 *o_mcp_resp, u32 *o_mcp_param);
670
671/**
672 * @brief - drains the nig, allowing completion to pass in case of pauses.
673 * (Should be called only from sleepable context)
674 *
675 * @param p_hwfn
676 * @param p_ptt
677 */
678enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
679 struct ecore_ptt *p_ptt);
680
681#ifndef LINUX_REMOVE
682/**
683 * @brief - return the mcp function info of the hw function
684 *
685 * @param p_hwfn
686 *
687 * @returns pointer to mcp function info
688 */
689const struct ecore_mcp_function_info
690*ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn);
691#endif
692
7c673cae
FG		 693#ifndef LINUX_REMOVE
694/**
695 * @brief - count number of function with a matching personality on engine.
696 *
697 * @param p_hwfn
698 * @param p_ptt
699 * @param personalities - a bitmask of ecore_pci_personality values
700 *
701 * @returns the count of all devices on engine whose personality match one of
702 * the bitsmasks.
703 */
704int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
705 struct ecore_ptt *p_ptt,
706 u32 personalities);
707#endif
708
709/**
710 * @brief Get the flash size value
711 *
712 * @param p_hwfn
713 * @param p_ptt
714 * @param p_flash_size - flash size in bytes to be filled.
715 *
716 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
717 */
718enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
719 struct ecore_ptt *p_ptt,
720 u32 *p_flash_size);
721
722/**
723 * @brief Send driver version to MFW
724 *
725 * @param p_hwfn
726 * @param p_ptt
727 * @param version - Version value
728 * @param name - Protocol driver name
729 *
730 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
731 */
732enum _ecore_status_t
733ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
734 struct ecore_mcp_drv_version *p_ver);
735
736/**
737 * @brief Read the MFW process kill counter
738 *
739 * @param p_hwfn
740 * @param p_ptt
741 *
742 * @return u32
743 */
744u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
745 struct ecore_ptt *p_ptt);
746
747/**
748 * @brief Trigger a recovery process
749 *
750 * @param p_hwfn
751 * @param p_ptt
752 *
753 * @return enum _ecore_status_t
754 */
755enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
756 struct ecore_ptt *p_ptt);
757
9f95a23c
TL		 758/**
759 * @brief A recovery handler must call this function as its first step.
760 * It is assumed that the handler is not run from an interrupt context.
761 *
762 * @param p_dev
763 * @param p_ptt
764 *
765 * @return enum _ecore_status_t
766 */
767enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev);
768
7c673cae
FG		 769/**
770 * @brief Notify MFW about the change in base device properties
771 *
772 * @param p_hwfn
773 * @param p_ptt
7c673cae
FG		 774 * @param client - ecore client type
775 *
776 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
777 */
778enum _ecore_status_t
779ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
780 struct ecore_ptt *p_ptt,
7c673cae
FG		 781 enum ecore_ov_client client);
782
783/**
784 * @brief Notify MFW about the driver state
785 *
786 * @param p_hwfn
787 * @param p_ptt
788 * @param drv_state - Driver state
789 *
790 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
791 */
792enum _ecore_status_t
793ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
794 struct ecore_ptt *p_ptt,
795 enum ecore_ov_driver_state drv_state);
796
797/**
798 * @brief Read NPIV settings form the MFW
799 *
800 * @param p_hwfn
801 * @param p_ptt
802 * @param p_table - Array to hold the FC NPIV data. Client need allocate the
803 * required buffer. The field 'count' specifies number of NPIV
804 * entries. A value of 0 means the table was not populated.
805 *
806 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
807 */
808enum _ecore_status_t
809ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
810 struct ecore_fc_npiv_tbl *p_table);
811
812/**
813 * @brief Send MTU size to MFW
814 *
815 * @param p_hwfn
816 * @param p_ptt
817 * @param mtu - MTU size
818 *
819 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
820 */
821enum _ecore_status_t ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
822 struct ecore_ptt *p_ptt, u16 mtu);
823
9f95a23c
TL		 824/**
825 * @brief Send MAC address to MFW
826 *
827 * @param p_hwfn
828 * @param p_ptt
829 * @param mac - MAC address
830 *
831 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
832 */
833enum _ecore_status_t
834ecore_mcp_ov_update_mac(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
835 u8 *mac);
836
837/**
838 * @brief Send eswitch mode to MFW
839 *
840 * @param p_hwfn
841 * @param p_ptt
842 * @param eswitch - eswitch mode
843 *
844 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
845 */
846enum _ecore_status_t
847ecore_mcp_ov_update_eswitch(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
848 enum ecore_ov_eswitch eswitch);
849
7c673cae
FG		 850/**
851 * @brief Set LED status
852 *
853 * @param p_hwfn
854 * @param p_ptt
855 * @param mode - LED mode
856 *
857 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
858 */
859enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
860 struct ecore_ptt *p_ptt,
861 enum ecore_led_mode mode);
862
863/**
864 * @brief Set secure mode
865 *
866 * @param p_dev
867 * @param addr - nvm offset
868 *
869 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
870 */
871enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
872 u32 addr);
873
874/**
875 * @brief Write to phy
876 *
877 * @param p_dev
878 * @param addr - nvm offset
879 * @param cmd - nvm command
880 * @param p_buf - nvm write buffer
881 * @param len - buffer len
882 *
883 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
884 */
885enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
886 u32 addr, u8 *p_buf, u32 len);
887
888/**
889 * @brief Write to nvm
890 *
891 * @param p_dev
892 * @param addr - nvm offset
893 * @param cmd - nvm command
894 * @param p_buf - nvm write buffer
895 * @param len - buffer len
896 *
897 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
898 */
899enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
900 u32 addr, u8 *p_buf, u32 len);
901
902/**
903 * @brief Put file begin
904 *
905 * @param p_dev
906 * @param addr - nvm offset
907 *
908 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
909 */
910enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
911 u32 addr);
912
913/**
914 * @brief Delete file
915 *
916 * @param p_dev
917 * @param addr - nvm offset
918 *
919 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
920 */
921enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev,
922 u32 addr);
923
924/**
925 * @brief Check latest response
926 *
927 * @param p_dev
928 * @param p_buf - nvm write buffer
929 *
930 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
931 */
932enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf);
933
934/**
935 * @brief Read from phy
936 *
937 * @param p_dev
938 * @param addr - nvm offset
939 * @param cmd - nvm command
9f95a23c 940 * @param p_buf - nvm read buffer
7c673cae
FG		 941 * @param len - buffer len
942 *
943 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
944 */
945enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
9f95a23c 946 u32 addr, u8 *p_buf, u32 *p_len);
7c673cae
FG		 947
948/**
949 * @brief Read from nvm
950 *
951 * @param p_dev
952 * @param addr - nvm offset
9f95a23c 953 * @param p_buf - nvm read buffer
7c673cae
FG		 954 * @param len - buffer len
955 *
956 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
957 */
958enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
959 u8 *p_buf, u32 len);
960
9f95a23c
TL		 961/**
962 * @brief - Sends an NVM write command request to the MFW with
963 * payload.
964 *
965 * @param p_hwfn
966 * @param p_ptt
967 * @param cmd - Command: Either DRV_MSG_CODE_NVM_WRITE_NVRAM or
968 * DRV_MSG_CODE_NVM_PUT_FILE_DATA
969 * @param param - [0:23] - Offset [24:31] - Size
970 * @param o_mcp_resp - MCP response
971 * @param o_mcp_param - MCP response param
972 * @param i_txn_size - Buffer size
973 * @param i_buf - Pointer to the buffer
974 *
975 * @param return ECORE_SUCCESS upon success.
976 */
977enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
978 struct ecore_ptt *p_ptt,
979 u32 cmd,
980 u32 param,
981 u32 *o_mcp_resp,
982 u32 *o_mcp_param,
983 u32 i_txn_size,
984 u32 *i_buf);
985
986/**
987 * @brief - Sends an NVM read command request to the MFW to get
988 * a buffer.
989 *
990 * @param p_hwfn
991 * @param p_ptt
992 * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or
993 * DRV_MSG_CODE_NVM_READ_NVRAM commands
994 * @param param - [0:23] - Offset [24:31] - Size
995 * @param o_mcp_resp - MCP response
996 * @param o_mcp_param - MCP response param
997 * @param o_txn_size - Buffer size output
998 * @param o_buf - Pointer to the buffer returned by the MFW.
999 *
1000 * @param return ECORE_SUCCESS upon success.
1001 */
1002enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
1003 struct ecore_ptt *p_ptt,
1004 u32 cmd,
1005 u32 param,
1006 u32 *o_mcp_resp,
1007 u32 *o_mcp_param,
1008 u32 *o_txn_size,
1009 u32 *o_buf);
1010
7c673cae
FG		 1011/**
1012 * @brief Read from sfp
1013 *
1014 * @param p_hwfn - hw function
1015 * @param p_ptt - PTT required for register access
1016 * @param port - transceiver port
1017 * @param addr - I2C address
1018 * @param offset - offset in sfp
1019 * @param len - buffer length
1020 * @param p_buf - buffer to read into
1021 *
1022 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1023 */
1024enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
1025 struct ecore_ptt *p_ptt,
1026 u32 port, u32 addr, u32 offset,
1027 u32 len, u8 *p_buf);
1028
1029/**
1030 * @brief Write to sfp
1031 *
1032 * @param p_hwfn - hw function
1033 * @param p_ptt - PTT required for register access
1034 * @param port - transceiver port
1035 * @param addr - I2C address
1036 * @param offset - offset in sfp
1037 * @param len - buffer length
1038 * @param p_buf - buffer to write from
1039 *
1040 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1041 */
1042enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
1043 struct ecore_ptt *p_ptt,
1044 u32 port, u32 addr, u32 offset,
1045 u32 len, u8 *p_buf);
1046
1047/**
1048 * @brief Gpio read
1049 *
1050 * @param p_hwfn - hw function
1051 * @param p_ptt - PTT required for register access
1052 * @param gpio - gpio number
1053 * @param gpio_val - value read from gpio
1054 *
1055 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1056 */
1057enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
1058 struct ecore_ptt *p_ptt,
1059 u16 gpio, u32 *gpio_val);
1060
1061/**
1062 * @brief Gpio write
1063 *
1064 * @param p_hwfn - hw function
1065 * @param p_ptt - PTT required for register access
1066 * @param gpio - gpio number
1067 * @param gpio_val - value to write to gpio
1068 *
1069 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1070 */
1071enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
1072 struct ecore_ptt *p_ptt,
1073 u16 gpio, u16 gpio_val);
1074
1075/**
1076 * @brief Gpio get information
1077 *
1078 * @param p_hwfn - hw function
1079 * @param p_ptt - PTT required for register access
1080 * @param gpio - gpio number
1081 * @param gpio_direction - gpio is output (0) or input (1)
1082 * @param gpio_ctrl - gpio control is uninitialized (0),
1083 * path 0 (1), path 1 (2) or shared(3)
1084 *
1085 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1086 */
1087enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
1088 struct ecore_ptt *p_ptt,
1089 u16 gpio, u32 *gpio_direction,
1090 u32 *gpio_ctrl);
1091
1092/**
1093 * @brief Bist register test
1094 *
1095 * @param p_hwfn - hw function
1096 * @param p_ptt - PTT required for register access
1097 *
1098 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1099 */
1100enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
1101 struct ecore_ptt *p_ptt);
1102
1103/**
1104 * @brief Bist clock test
1105 *
1106 * @param p_hwfn - hw function
1107 * @param p_ptt - PTT required for register access
1108 *
1109 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1110 */
1111enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
1112 struct ecore_ptt *p_ptt);
1113
1114/**
1115 * @brief Bist nvm test - get number of images
1116 *
1117 * @param p_hwfn - hw function
1118 * @param p_ptt - PTT required for register access
1119 * @param num_images - number of images if operation was
1120 * successful. 0 if not.
1121 *
1122 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1123 */
1124enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
1125 struct ecore_hwfn *p_hwfn,
1126 struct ecore_ptt *p_ptt,
1127 u32 *num_images);
1128
1129/**
1130 * @brief Bist nvm test - get image attributes by index
1131 *
1132 * @param p_hwfn - hw function
1133 * @param p_ptt - PTT required for register access
1134 * @param p_image_att - Attributes of image
1135 * @param image_index - Index of image to get information for
1136 *
1137 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1138 */
1139enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
1140 struct ecore_hwfn *p_hwfn,
1141 struct ecore_ptt *p_ptt,
1142 struct bist_nvm_image_att *p_image_att,
1143 u32 image_index);
1144
1145/**
1146 * @brief ecore_mcp_get_temperature_info - get the status of the temperature
1147 * sensors
1148 *
1149 * @param p_hwfn - hw function
1150 * @param p_ptt - PTT required for register access
1151 * @param p_temp_status - A pointer to an ecore_temperature_info structure to
1152 * be filled with the temperature data
1153 *
1154 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1155 */
1156enum _ecore_status_t
1157ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
1158 struct ecore_ptt *p_ptt,
1159 struct ecore_temperature_info *p_temp_info);
1160
1161/**
1162 * @brief Get MBA versions - get MBA sub images versions
1163 *
1164 * @param p_hwfn - hw function
1165 * @param p_ptt - PTT required for register access
1166 * @param p_mba_vers - MBA versions array to fill
1167 *
1168 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1169 */
1170enum _ecore_status_t ecore_mcp_get_mba_versions(
1171 struct ecore_hwfn *p_hwfn,
1172 struct ecore_ptt *p_ptt,
1173 struct ecore_mba_vers *p_mba_vers);
1174
1175/**
1176 * @brief Count memory ecc events
1177 *
1178 * @param p_hwfn - hw function
1179 * @param p_ptt - PTT required for register access
1180 * @param num_events - number of memory ecc events
1181 *
1182 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1183 */
1184enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
1185 struct ecore_ptt *p_ptt,
1186 u64 *num_events);
1187
11fdf7f2
TL		 1188struct ecore_mdump_info {
1189 u32 reason;
1190 u32 version;
1191 u32 config;
1192 u32 epoch;
1193 u32 num_of_logs;
1194 u32 valid_logs;
1195};
1196
1197/**
1198 * @brief - Gets the MFW crash dump configuration and logs info.
1199 *
1200 * @param p_hwfn
1201 * @param p_ptt
1202 * @param p_mdump_info
1203 *
1204 * @param return ECORE_SUCCESS upon success.
1205 */
1206enum _ecore_status_t
1207ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1208 struct ecore_mdump_info *p_mdump_info);
1209
7c673cae 1210/**
11fdf7f2 1211 * @brief - Clears the MFW crash dump logs.
7c673cae 1212 *
11fdf7f2
TL		 1213 * @param p_hwfn
1214 * @param p_ptt
1215 *
1216 * @param return ECORE_SUCCESS upon success.
1217 */
1218enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1219 struct ecore_ptt *p_ptt);
1220
9f95a23c
TL		 1221/**
1222 * @brief - Clear the mdump retained data.
1223 *
1224 * @param p_hwfn
1225 * @param p_ptt
1226 *
1227 * @param return ECORE_SUCCESS upon success.
1228 */
1229enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1230 struct ecore_ptt *p_ptt);
1231
11fdf7f2
TL		 1232/**
1233 * @brief - Processes the TLV request from MFW i.e., get the required TLV info
1234 * from the ecore client and send it to the MFW.
1235 *
1236 * @param p_hwfn
1237 * @param p_ptt
7c673cae 1238 *
11fdf7f2 1239 * @param return ECORE_SUCCESS upon success.
7c673cae 1240 */
11fdf7f2
TL		 1241enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn,
1242 struct ecore_ptt *p_ptt);
7c673cae 1243
9f95a23c
TL		 1244
1245/**
1246 * @brief - Return whether management firmware support smart AN
1247 *
1248 * @param p_hwfn
1249 *
1250 * @return bool - true iff feature is supported.
1251 */
1252bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn);
7c673cae 1253#endif
Ceph