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[ceph.git] / ceph / src / seastar / dpdk / drivers / net / qede / base / ecore_sp_commands.c
CommitLineData
9f95a23c
TL		 1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7c673cae 3 * All rights reserved.
9f95a23c 4 * www.cavium.com
7c673cae
FG		 5 */
6
7#include "bcm_osal.h"
8
9#include "ecore.h"
10#include "ecore_status.h"
11#include "ecore_chain.h"
12#include "ecore_spq.h"
13#include "ecore_init_fw_funcs.h"
14#include "ecore_cxt.h"
15#include "ecore_sp_commands.h"
16#include "ecore_gtt_reg_addr.h"
17#include "ecore_iro.h"
18#include "reg_addr.h"
19#include "ecore_int.h"
20#include "ecore_hw.h"
21#include "ecore_dcbx.h"
22#include "ecore_sriov.h"
11fdf7f2 23#include "ecore_vf.h"
7c673cae
FG		 24
25enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
26 struct ecore_spq_entry **pp_ent,
27 u8 cmd,
28 u8 protocol,
29 struct ecore_sp_init_data *p_data)
30{
31 u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
32 struct ecore_spq_entry *p_ent = OSAL_NULL;
11fdf7f2 33 enum _ecore_status_t rc;
7c673cae
FG		 34
35 if (!pp_ent)
36 return ECORE_INVAL;
37
38 /* Get an SPQ entry */
39 rc = ecore_spq_get_entry(p_hwfn, pp_ent);
40 if (rc != ECORE_SUCCESS)
41 return rc;
42
43 /* Fill the SPQ entry */
44 p_ent = *pp_ent;
45 p_ent->elem.hdr.cid = OSAL_CPU_TO_LE32(opaque_cid);
46 p_ent->elem.hdr.cmd_id = cmd;
47 p_ent->elem.hdr.protocol_id = protocol;
48 p_ent->priority = ECORE_SPQ_PRIORITY_NORMAL;
49 p_ent->comp_mode = p_data->comp_mode;
50 p_ent->comp_done.done = 0;
51
52 switch (p_ent->comp_mode) {
53 case ECORE_SPQ_MODE_EBLOCK:
54 p_ent->comp_cb.cookie = &p_ent->comp_done;
55 break;
56
57 case ECORE_SPQ_MODE_BLOCK:
58 if (!p_data->p_comp_data)
59 return ECORE_INVAL;
60
61 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
62 break;
63
64 case ECORE_SPQ_MODE_CB:
65 if (!p_data->p_comp_data)
66 p_ent->comp_cb.function = OSAL_NULL;
67 else
68 p_ent->comp_cb = *p_data->p_comp_data;
69 break;
70
71 default:
72 DP_NOTICE(p_hwfn, true, "Unknown SPQE completion mode %d\n",
73 p_ent->comp_mode);
74 return ECORE_INVAL;
75 }
76
77 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
78 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
79 opaque_cid, cmd, protocol,
80 (unsigned long)&p_ent->ramrod,
81 D_TRINE(p_ent->comp_mode, ECORE_SPQ_MODE_EBLOCK,
82 ECORE_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
83 "MODE_CB"));
84
85 OSAL_MEMSET(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
86
87 return ECORE_SUCCESS;
88}
89
11fdf7f2 90static enum tunnel_clss ecore_tunn_clss_to_fw_clss(u8 type)
7c673cae
FG		 91{
92 switch (type) {
93 case ECORE_TUNN_CLSS_MAC_VLAN:
94 return TUNNEL_CLSS_MAC_VLAN;
95 case ECORE_TUNN_CLSS_MAC_VNI:
96 return TUNNEL_CLSS_MAC_VNI;
97 case ECORE_TUNN_CLSS_INNER_MAC_VLAN:
98 return TUNNEL_CLSS_INNER_MAC_VLAN;
99 case ECORE_TUNN_CLSS_INNER_MAC_VNI:
100 return TUNNEL_CLSS_INNER_MAC_VNI;
101 case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
102 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
103 default:
104 return TUNNEL_CLSS_MAC_VLAN;
105 }
106}
107
108static void
11fdf7f2
TL		 109ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info *p_tun,
110 struct ecore_tunnel_info *p_src,
111 bool b_pf_start)
7c673cae 112{
11fdf7f2
TL		 113 if (p_src->vxlan.b_update_mode || b_pf_start)
114 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
7c673cae 115
11fdf7f2
TL		 116 if (p_src->l2_gre.b_update_mode || b_pf_start)
117 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
7c673cae 118
11fdf7f2
TL		 119 if (p_src->ip_gre.b_update_mode || b_pf_start)
120 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
7c673cae 121
11fdf7f2
TL		 122 if (p_src->l2_geneve.b_update_mode || b_pf_start)
123 p_tun->l2_geneve.b_mode_enabled =
124 p_src->l2_geneve.b_mode_enabled;
7c673cae 125
11fdf7f2
TL		 126 if (p_src->ip_geneve.b_update_mode || b_pf_start)
127 p_tun->ip_geneve.b_mode_enabled =
128 p_src->ip_geneve.b_mode_enabled;
7c673cae
FG		 129}
130
11fdf7f2
TL		 131static void ecore_set_tunn_cls_info(struct ecore_tunnel_info *p_tun,
132 struct ecore_tunnel_info *p_src)
7c673cae 133{
7c673cae
FG		 134 enum tunnel_clss type;
135
11fdf7f2
TL		 136 p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
137 p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
138
139 /* @DPDK - typecast tunnul class */
140 type = ecore_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
141 p_tun->vxlan.tun_cls = (enum ecore_tunn_clss)type;
142 type = ecore_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
143 p_tun->l2_gre.tun_cls = (enum ecore_tunn_clss)type;
144 type = ecore_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
145 p_tun->ip_gre.tun_cls = (enum ecore_tunn_clss)type;
146 type = ecore_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
147 p_tun->l2_geneve.tun_cls = (enum ecore_tunn_clss)type;
148 type = ecore_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
149 p_tun->ip_geneve.tun_cls = (enum ecore_tunn_clss)type;
150}
7c673cae 151
11fdf7f2
TL		 152static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun,
153 struct ecore_tunnel_info *p_src)
154{
155 p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
156 p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
7c673cae 157
11fdf7f2
TL		 158 if (p_src->geneve_port.b_update_port)
159 p_tun->geneve_port.port = p_src->geneve_port.port;
7c673cae 160
11fdf7f2
TL		 161 if (p_src->vxlan_port.b_update_port)
162 p_tun->vxlan_port.port = p_src->vxlan_port.port;
163}
7c673cae 164
11fdf7f2 165static void
9f95a23c 166__ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
11fdf7f2
TL		 167 struct ecore_tunn_update_type *tun_type)
168{
169 *p_tunn_cls = tun_type->tun_cls;
11fdf7f2 170}
7c673cae 171
11fdf7f2 172static void
9f95a23c 173ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
11fdf7f2
TL		 174 struct ecore_tunn_update_type *tun_type,
175 u8 *p_update_port, __le16 *p_port,
176 struct ecore_tunn_update_udp_port *p_udp_port)
177{
9f95a23c 178 __ecore_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
11fdf7f2
TL		 179 if (p_udp_port->b_update_port) {
180 *p_update_port = 1;
181 *p_port = OSAL_CPU_TO_LE16(p_udp_port->port);
182 }
183}
7c673cae 184
11fdf7f2
TL		 185static void
186ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn,
187 struct ecore_tunnel_info *p_src,
188 struct pf_update_tunnel_config *p_tunn_cfg)
189{
190 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
191
192 ecore_set_pf_update_tunn_mode(p_tun, p_src, false);
193 ecore_set_tunn_cls_info(p_tun, p_src);
194 ecore_set_tunn_ports(p_tun, p_src);
195
196 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
11fdf7f2
TL		 197 &p_tun->vxlan,
198 &p_tunn_cfg->set_vxlan_udp_port_flg,
199 &p_tunn_cfg->vxlan_udp_port,
200 &p_tun->vxlan_port);
201
202 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
11fdf7f2
TL		 203 &p_tun->l2_geneve,
204 &p_tunn_cfg->set_geneve_udp_port_flg,
205 &p_tunn_cfg->geneve_udp_port,
206 &p_tun->geneve_port);
207
208 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
11fdf7f2
TL		 209 &p_tun->ip_geneve);
210
211 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
11fdf7f2
TL		 212 &p_tun->l2_gre);
213
214 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
11fdf7f2
TL		 215 &p_tun->ip_gre);
216
217 p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
7c673cae
FG		 218}
219
220static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn,
221 struct ecore_ptt *p_ptt,
11fdf7f2 222 struct ecore_tunnel_info *p_tun)
7c673cae 223{
11fdf7f2
TL		 224 ecore_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
225 p_tun->ip_gre.b_mode_enabled);
226 ecore_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
7c673cae 227
11fdf7f2
TL		 228 ecore_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
229 p_tun->ip_geneve.b_mode_enabled);
230}
7c673cae 231
11fdf7f2 232static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn *p_hwfn,
9f95a23c 233 struct ecore_ptt *p_ptt,
11fdf7f2
TL		 234 struct ecore_tunnel_info *p_tunn)
235{
236 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
237 DP_NOTICE(p_hwfn, true,
238 "A0 chip: tunnel hw config is not supported\n");
7c673cae 239 return;
11fdf7f2 240 }
7c673cae 241
11fdf7f2 242 if (p_tunn->vxlan_port.b_update_port)
9f95a23c 243 ecore_set_vxlan_dest_port(p_hwfn, p_ptt,
11fdf7f2 244 p_tunn->vxlan_port.port);
7c673cae 245
11fdf7f2 246 if (p_tunn->geneve_port.b_update_port)
9f95a23c 247 ecore_set_geneve_dest_port(p_hwfn, p_ptt,
11fdf7f2 248 p_tunn->geneve_port.port);
7c673cae 249
9f95a23c 250 ecore_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
7c673cae
FG		 251}
252
253static void
254ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,
11fdf7f2 255 struct ecore_tunnel_info *p_src,
7c673cae
FG		 256 struct pf_start_tunnel_config *p_tunn_cfg)
257{
11fdf7f2 258 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
7c673cae
FG		 259
260 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
11fdf7f2
TL		 261 DP_NOTICE(p_hwfn, true,
262 "A0 chip: tunnel pf start config is not supported\n");
7c673cae
FG		 263 return;
264 }
265
11fdf7f2
TL		 266 if (!p_src)
267 return;
7c673cae 268
11fdf7f2
TL		 269 ecore_set_pf_update_tunn_mode(p_tun, p_src, true);
270 ecore_set_tunn_cls_info(p_tun, p_src);
271 ecore_set_tunn_ports(p_tun, p_src);
272
273 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
11fdf7f2
TL		 274 &p_tun->vxlan,
275 &p_tunn_cfg->set_vxlan_udp_port_flg,
276 &p_tunn_cfg->vxlan_udp_port,
277 &p_tun->vxlan_port);
278
279 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
11fdf7f2
TL		 280 &p_tun->l2_geneve,
281 &p_tunn_cfg->set_geneve_udp_port_flg,
282 &p_tunn_cfg->geneve_udp_port,
283 &p_tun->geneve_port);
284
285 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
11fdf7f2
TL		 286 &p_tun->ip_geneve);
287
288 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
11fdf7f2
TL		 289 &p_tun->l2_gre);
290
291 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
11fdf7f2 292 &p_tun->ip_gre);
7c673cae
FG		 293}
294
9f95a23c
TL		 295#define ETH_P_8021Q 0x8100
296#define ETH_P_8021AD 0x88A8 /* 802.1ad Service VLAN */
297
7c673cae 298enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
9f95a23c 299 struct ecore_ptt *p_ptt,
11fdf7f2 300 struct ecore_tunnel_info *p_tunn,
7c673cae
FG		 301 bool allow_npar_tx_switch)
302{
303 struct pf_start_ramrod_data *p_ramrod = OSAL_NULL;
304 u16 sb = ecore_int_get_sp_sb_id(p_hwfn);
305 u8 sb_index = p_hwfn->p_eq->eq_sb_index;
306 struct ecore_spq_entry *p_ent = OSAL_NULL;
307 struct ecore_sp_init_data init_data;
308 enum _ecore_status_t rc = ECORE_NOTIMPL;
309 u8 page_cnt;
9f95a23c 310 u8 i;
7c673cae
FG		 311
312 /* update initial eq producer */
313 ecore_eq_prod_update(p_hwfn,
314 ecore_chain_get_prod_idx(&p_hwfn->p_eq->chain));
315
316 /* Initialize the SPQ entry for the ramrod */
317 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
318 init_data.cid = ecore_spq_get_cid(p_hwfn);
319 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
320 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
321
322 rc = ecore_sp_init_request(p_hwfn, &p_ent,
323 COMMON_RAMROD_PF_START,
324 PROTOCOLID_COMMON, &init_data);
325 if (rc != ECORE_SUCCESS)
326 return rc;
327
328 /* Fill the ramrod data */
329 p_ramrod = &p_ent->ramrod.pf_start;
330 p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb);
331 p_ramrod->event_ring_sb_index = sb_index;
332 p_ramrod->path_id = ECORE_PATH_ID(p_hwfn);
333
334 /* For easier debugging */
335 p_ramrod->dont_log_ramrods = 0;
9f95a23c 336 p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f);
7c673cae 337
9f95a23c 338 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
7c673cae 339 p_ramrod->mf_mode = MF_OVLAN;
9f95a23c 340 else
7c673cae 341 p_ramrod->mf_mode = MF_NPAR;
9f95a23c
TL		 342
343 p_ramrod->outer_tag_config.outer_tag.tci =
344 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
345 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {
346 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;
347 } else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
348 &p_hwfn->p_dev->mf_bits)) {
349 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;
350 p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
351 }
352
353 p_ramrod->outer_tag_config.pri_map_valid = 1;
354 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
355 p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i;
356
357 /* enable_stag_pri_change should be set if port is in BD mode or,
358 * UFP with Host Control mode or, UFP with DCB over base interface.
359 */
360 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {
361 if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
362 (p_hwfn->p_dcbx_info->results.dcbx_enabled))
363 p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
364 else
365 p_ramrod->outer_tag_config.enable_stag_pri_change = 0;
7c673cae 366 }
7c673cae
FG		 367
368 /* Place EQ address in RAMROD */
369 DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
11fdf7f2 370 p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
7c673cae
FG		 371 page_cnt = (u8)ecore_chain_get_page_cnt(&p_hwfn->p_eq->chain);
372 p_ramrod->event_ring_num_pages = page_cnt;
373 DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
11fdf7f2 374 p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
7c673cae
FG		 375
376 ecore_tunn_set_pf_start_params(p_hwfn, p_tunn,
377 &p_ramrod->tunnel_config);
378
9f95a23c
TL		 379 if (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH,
380 &p_hwfn->p_dev->mf_bits))
7c673cae
FG		 381 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
382
383 switch (p_hwfn->hw_info.personality) {
384 case ECORE_PCI_ETH:
385 p_ramrod->personality = PERSONALITY_ETH;
386 break;
387 default:
388 DP_NOTICE(p_hwfn, true, "Unknown personality %d\n",
389 p_hwfn->hw_info.personality);
390 p_ramrod->personality = PERSONALITY_ETH;
391 }
392
393 if (p_hwfn->p_dev->p_iov_info) {
394 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
395
396 p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
397 p_ramrod->num_vfs = (u8)p_iov->total_vfs;
398 }
399 /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
400 * version is available.
401 */
402 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
403 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
404
405 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
9f95a23c
TL		 406 "Setting event_ring_sb [id %04x index %02x], outer_tag.tpid [%d], outer_tag.tci [%d]\n",
407 sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tpid,
408 p_ramrod->outer_tag_config.outer_tag.tci);
7c673cae
FG		 409
410 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
411
11fdf7f2 412 if (p_tunn)
9f95a23c
TL		 413 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt,
414 &p_hwfn->p_dev->tunnel);
7c673cae
FG		 415
416 return rc;
417}
418
9f95a23c 419enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn)
7c673cae
FG		 420{
421 struct ecore_spq_entry *p_ent = OSAL_NULL;
422 struct ecore_sp_init_data init_data;
423 enum _ecore_status_t rc = ECORE_NOTIMPL;
424
425 /* Get SPQ entry */
426 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
427 init_data.cid = ecore_spq_get_cid(p_hwfn);
428 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
429 init_data.comp_mode = ECORE_SPQ_MODE_CB;
430
431 rc = ecore_sp_init_request(p_hwfn, &p_ent,
432 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
433 &init_data);
434 if (rc != ECORE_SUCCESS)
435 return rc;
436
437 ecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
438 &p_ent->ramrod.pf_update);
439
440 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
441}
442
9f95a23c
TL		 443enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn)
444{
445 struct ecore_spq_entry *p_ent = OSAL_NULL;
446 struct ecore_sp_init_data init_data;
447 enum _ecore_status_t rc = ECORE_NOTIMPL;
448
449 /* Get SPQ entry */
450 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
451 init_data.cid = ecore_spq_get_cid(p_hwfn);
452 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
453 init_data.comp_mode = ECORE_SPQ_MODE_CB;
454
455 rc = ecore_sp_init_request(p_hwfn, &p_ent,
456 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
457 &init_data);
458 if (rc != ECORE_SUCCESS)
459 return rc;
460
461 p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
462 if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
463 (p_hwfn->p_dcbx_info->results.dcbx_enabled))
464 p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
465 else
466 p_ent->ramrod.pf_update.enable_stag_pri_change = 0;
467
468 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
469}
470
471
472/* QM rate limiter resolution is 1.6Mbps */
473#define QM_RL_RESOLUTION(mb_val) ((mb_val) * 10 / 16)
474
475/* FW uses 1/64k to express gd */
476#define FW_GD_RESOLUTION(gd) (64 * 1024 / (gd))
477
478u16 ecore_sp_rl_mb_to_qm(u32 mb_val)
479{
480 return (u16)OSAL_MIN_T(u32, (u16)(~0U), QM_RL_RESOLUTION(mb_val));
481}
482
483u16 ecore_sp_rl_gd_denom(u32 gd)
484{
485 return gd ? (u16)OSAL_MIN_T(u32, (u16)(~0U), FW_GD_RESOLUTION(gd)) : 0;
486}
487
7c673cae
FG		 488enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
489 struct ecore_rl_update_params *params)
490{
491 struct ecore_spq_entry *p_ent = OSAL_NULL;
492 enum _ecore_status_t rc = ECORE_NOTIMPL;
493 struct rl_update_ramrod_data *rl_update;
494 struct ecore_sp_init_data init_data;
495
496 /* Get SPQ entry */
497 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
498 init_data.cid = ecore_spq_get_cid(p_hwfn);
499 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
500 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
501
502 rc = ecore_sp_init_request(p_hwfn, &p_ent,
503 COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON,
504 &init_data);
505 if (rc != ECORE_SUCCESS)
506 return rc;
507
508 rl_update = &p_ent->ramrod.rl_update;
509
510 rl_update->qcn_update_param_flg = params->qcn_update_param_flg;
511 rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg;
512 rl_update->rl_init_flg = params->rl_init_flg;
513 rl_update->rl_start_flg = params->rl_start_flg;
514 rl_update->rl_stop_flg = params->rl_stop_flg;
515 rl_update->rl_id_first = params->rl_id_first;
516 rl_update->rl_id_last = params->rl_id_last;
517 rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
9f95a23c
TL		 518 rl_update->dcqcn_reset_alpha_on_idle =
519 params->dcqcn_reset_alpha_on_idle;
520 rl_update->rl_bc_stage_th = params->rl_bc_stage_th;
521 rl_update->rl_timer_stage_th = params->rl_timer_stage_th;
7c673cae 522 rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
9f95a23c
TL		 523 rl_update->rl_max_rate =
524 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_max_rate));
525 rl_update->rl_r_ai =
526 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_ai));
527 rl_update->rl_r_hai =
528 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_hai));
529 rl_update->dcqcn_g =
530 OSAL_CPU_TO_LE16(ecore_sp_rl_gd_denom(params->dcqcn_gd));
7c673cae 531 rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us);
9f95a23c
TL		 532 rl_update->dcqcn_timeuot_us =
533 OSAL_CPU_TO_LE32(params->dcqcn_timeuot_us);
7c673cae
FG		 534 rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
535
9f95a23c
TL		 536 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x,dcqcn_reset_alpha_on_idle %x, rl_bc_stage_th %x, rl_timer_stage_th %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n",
537 rl_update->qcn_update_param_flg,
538 rl_update->dcqcn_update_param_flg,
539 rl_update->rl_init_flg, rl_update->rl_start_flg,
540 rl_update->rl_stop_flg, rl_update->rl_id_first,
541 rl_update->rl_id_last, rl_update->rl_dc_qcn_flg,
542 rl_update->dcqcn_reset_alpha_on_idle,
543 rl_update->rl_bc_stage_th, rl_update->rl_timer_stage_th,
544 rl_update->rl_bc_rate, rl_update->rl_max_rate,
545 rl_update->rl_r_ai, rl_update->rl_r_hai,
546 rl_update->dcqcn_g, rl_update->dcqcn_k_us,
547 rl_update->dcqcn_timeuot_us, rl_update->qcn_timeuot_us);
548
7c673cae
FG		 549 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
550}
551
552/* Set pf update ramrod command params */
553enum _ecore_status_t
554ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
9f95a23c 555 struct ecore_ptt *p_ptt,
11fdf7f2 556 struct ecore_tunnel_info *p_tunn,
7c673cae
FG		 557 enum spq_mode comp_mode,
558 struct ecore_spq_comp_cb *p_comp_data)
559{
560 struct ecore_spq_entry *p_ent = OSAL_NULL;
561 struct ecore_sp_init_data init_data;
562 enum _ecore_status_t rc = ECORE_NOTIMPL;
563
11fdf7f2
TL		 564 if (IS_VF(p_hwfn->p_dev))
565 return ecore_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
566
567 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
568 DP_NOTICE(p_hwfn, true,
569 "A0 chip: tunnel pf update config is not supported\n");
570 return rc;
571 }
572
573 if (!p_tunn)
574 return ECORE_INVAL;
575
7c673cae
FG		 576 /* Get SPQ entry */
577 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
578 init_data.cid = ecore_spq_get_cid(p_hwfn);
579 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
580 init_data.comp_mode = comp_mode;
581 init_data.p_comp_data = p_comp_data;
582
583 rc = ecore_sp_init_request(p_hwfn, &p_ent,
584 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
585 &init_data);
586 if (rc != ECORE_SUCCESS)
587 return rc;
588
589 ecore_tunn_set_pf_update_params(p_hwfn, p_tunn,
590 &p_ent->ramrod.pf_update.tunnel_config);
591
592 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
593 if (rc != ECORE_SUCCESS)
594 return rc;
595
9f95a23c 596 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->p_dev->tunnel);
7c673cae
FG		 597
598 return rc;
599}
600
601enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn)
602{
603 struct ecore_spq_entry *p_ent = OSAL_NULL;
604 struct ecore_sp_init_data init_data;
605 enum _ecore_status_t rc = ECORE_NOTIMPL;
606
607 /* Get SPQ entry */
608 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
609 init_data.cid = ecore_spq_get_cid(p_hwfn);
610 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
611 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
612
613 rc = ecore_sp_init_request(p_hwfn, &p_ent,
614 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
615 &init_data);
616 if (rc != ECORE_SUCCESS)
617 return rc;
618
619 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
620}
621
622enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
623{
624 struct ecore_spq_entry *p_ent = OSAL_NULL;
625 struct ecore_sp_init_data init_data;
11fdf7f2 626 enum _ecore_status_t rc;
7c673cae
FG		 627
628 /* Get SPQ entry */
629 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
630 init_data.cid = ecore_spq_get_cid(p_hwfn);
631 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
632 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
633
634 rc = ecore_sp_init_request(p_hwfn, &p_ent,
635 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
636 &init_data);
637 if (rc != ECORE_SUCCESS)
638 return rc;
639
640 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
641}
9f95a23c
TL		 642
643enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn)
644{
645 struct ecore_spq_entry *p_ent = OSAL_NULL;
646 struct ecore_sp_init_data init_data;
647 enum _ecore_status_t rc = ECORE_NOTIMPL;
648
649 /* Get SPQ entry */
650 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
651 init_data.cid = ecore_spq_get_cid(p_hwfn);
652 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
653 init_data.comp_mode = ECORE_SPQ_MODE_CB;
654
655 rc = ecore_sp_init_request(p_hwfn, &p_ent,
656 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
657 &init_data);
658 if (rc != ECORE_SUCCESS)
659 return rc;
660
661 p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
662 p_ent->ramrod.pf_update.mf_vlan =
663 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
664
665 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
666}
Ceph