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9f95a23c TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright (c) 2016 - 2018 Cavium Inc. | |
7c673cae | 3 | * All rights reserved. |
9f95a23c | 4 | * www.cavium.com |
7c673cae FG |
5 | */ |
6 | ||
7 | /**************************************************************************** | |
8 | * | |
9 | * Name: mcp_public.h | |
10 | * | |
11 | * Description: MCP public data | |
12 | * | |
13 | * Created: 13/01/2013 yanivr | |
14 | * | |
15 | ****************************************************************************/ | |
16 | ||
17 | #ifndef MCP_PUBLIC_H | |
18 | #define MCP_PUBLIC_H | |
19 | ||
20 | #define VF_MAX_STATIC 192 /* In case of AH */ | |
21 | ||
22 | #define MCP_GLOB_PATH_MAX 2 | |
23 | #define MCP_PORT_MAX 2 /* Global */ | |
24 | #define MCP_GLOB_PORT_MAX 4 /* Global */ | |
25 | #define MCP_GLOB_FUNC_MAX 16 /* Global */ | |
26 | ||
27 | typedef u32 offsize_t; /* In DWORDS !!! */ | |
28 | /* Offset from the beginning of the MCP scratchpad */ | |
9f95a23c | 29 | #define OFFSIZE_OFFSET_OFFSET 0 |
7c673cae FG |
30 | #define OFFSIZE_OFFSET_MASK 0x0000ffff |
31 | /* Size of specific element (not the whole array if any) */ | |
9f95a23c | 32 | #define OFFSIZE_SIZE_OFFSET 16 |
7c673cae FG |
33 | #define OFFSIZE_SIZE_MASK 0xffff0000 |
34 | ||
35 | /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ | |
36 | #define SECTION_OFFSET(_offsize) \ | |
9f95a23c | 37 | ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2)) |
7c673cae FG |
38 | |
39 | /* SECTION_SIZE is calculating the size in bytes out of offsize */ | |
40 | #define SECTION_SIZE(_offsize) \ | |
9f95a23c | 41 | (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2) |
7c673cae FG |
42 | |
43 | /* SECTION_ADDR returns the GRC addr of a section, given offsize and index | |
44 | * within section | |
45 | */ | |
46 | #define SECTION_ADDR(_offsize, idx) \ | |
47 | (MCP_REG_SCRATCH + \ | |
48 | SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) | |
49 | ||
50 | /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use | |
51 | * offsetof, since the OFFSETUP collide with the firmware definition | |
52 | */ | |
53 | #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ | |
54 | (_pub_base + offsetof(struct mcp_public_data, sections[_section])) | |
55 | /* PHY configuration */ | |
56 | struct eth_phy_cfg { | |
57 | /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ | |
58 | u32 speed; | |
59 | #define ETH_SPEED_AUTONEG 0 | |
9f95a23c | 60 | #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */ |
7c673cae FG |
61 | |
62 | u32 pause; /* bitmask */ | |
63 | #define ETH_PAUSE_NONE 0x0 | |
64 | #define ETH_PAUSE_AUTONEG 0x1 | |
65 | #define ETH_PAUSE_RX 0x2 | |
66 | #define ETH_PAUSE_TX 0x4 | |
67 | ||
68 | u32 adv_speed; /* Default should be the speed_cap_mask */ | |
69 | u32 loopback_mode; | |
70 | #define ETH_LOOPBACK_NONE (0) | |
71 | /* Serdes loopback. In AH, it refers to Near End */ | |
72 | #define ETH_LOOPBACK_INT_PHY (1) | |
73 | #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ | |
74 | /* External Loopback (Require loopback plug) */ | |
75 | #define ETH_LOOPBACK_EXT (3) | |
76 | #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ | |
77 | #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ | |
78 | #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ | |
79 | #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ | |
80 | /* Loop RX packet from PCS to TX */ | |
81 | #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) | |
82 | /* Remote Serdes Loopback (RX to TX) */ | |
83 | #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) | |
84 | ||
9f95a23c TL |
85 | u32 eee_cfg; |
86 | /* EEE is enabled (configuration). Refer to eee_status->active for negotiated | |
87 | * status | |
11fdf7f2 | 88 | */ |
9f95a23c TL |
89 | #define EEE_CFG_EEE_ENABLED (1 << 0) |
90 | #define EEE_CFG_TX_LPI (1 << 1) | |
91 | #define EEE_CFG_ADV_SPEED_1G (1 << 2) | |
92 | #define EEE_CFG_ADV_SPEED_10G (1 << 3) | |
93 | #define EEE_TX_TIMER_USEC_MASK (0xfffffff0) | |
94 | #define EEE_TX_TIMER_USEC_OFFSET 4 | |
95 | #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) | |
96 | #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) | |
97 | #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) | |
98 | ||
99 | u32 link_modes; /* Additional link modes */ | |
100 | #define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */ | |
7c673cae FG |
101 | }; |
102 | ||
103 | struct port_mf_cfg { | |
104 | u32 dynamic_cfg; /* device control channel */ | |
105 | #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff | |
9f95a23c | 106 | #define PORT_MF_CFG_OV_TAG_OFFSET 0 |
7c673cae FG |
107 | #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK |
108 | ||
109 | u32 reserved[1]; | |
110 | }; | |
111 | ||
112 | /* DO NOT add new fields in the middle | |
113 | * MUST be synced with struct pmm_stats_map | |
114 | */ | |
115 | struct eth_stats { | |
116 | u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ | |
117 | u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ | |
118 | u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ | |
119 | u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ | |
120 | u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ | |
121 | /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ | |
122 | u64 r1518; | |
9f95a23c TL |
123 | union { |
124 | struct { /* bb */ | |
7c673cae | 125 | /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ |
9f95a23c TL |
126 | u64 r1522; |
127 | /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ | |
128 | u64 r2047; | |
129 | /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ | |
130 | u64 r4095; | |
131 | /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ | |
132 | u64 r9216; | |
7c673cae | 133 | /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ |
9f95a23c TL |
134 | u64 r16383; |
135 | } bb0; | |
136 | struct { /* ah */ | |
137 | u64 unused1; | |
138 | /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/ | |
139 | u64 r1519_to_max; | |
140 | u64 unused2; | |
141 | u64 unused3; | |
142 | u64 unused4; | |
143 | } ah0; | |
144 | } u0; | |
7c673cae FG |
145 | u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ |
146 | u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ | |
147 | u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ | |
148 | u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ | |
149 | u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ | |
150 | u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ | |
151 | u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ | |
152 | u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ | |
153 | u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ | |
154 | u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ | |
155 | u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ | |
156 | u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ | |
157 | u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ | |
158 | u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ | |
159 | u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ | |
160 | /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ | |
161 | u64 t1518; | |
9f95a23c TL |
162 | union { |
163 | struct { /* bb */ | |
7c673cae | 164 | /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ |
9f95a23c | 165 | u64 t2047; |
7c673cae | 166 | /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ |
9f95a23c | 167 | u64 t4095; |
7c673cae | 168 | /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ |
9f95a23c | 169 | u64 t9216; |
7c673cae | 170 | /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ |
9f95a23c TL |
171 | u64 t16383; |
172 | } bb1; | |
173 | struct { /* ah */ | |
174 | /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */ | |
175 | u64 t1519_to_max; | |
176 | u64 unused6; | |
177 | u64 unused7; | |
178 | u64 unused8; | |
179 | } ah1; | |
180 | } u1; | |
7c673cae FG |
181 | u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ |
182 | u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ | |
183 | /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ | |
9f95a23c TL |
184 | union { |
185 | struct { /* bb */ | |
186 | /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ | |
187 | u64 tlpiec; | |
188 | /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ | |
189 | u64 tncl; | |
190 | } bb2; | |
191 | struct { /* ah */ | |
192 | u64 unused9; | |
193 | u64 unused10; | |
194 | } ah2; | |
195 | } u2; | |
7c673cae FG |
196 | u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ |
197 | u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ | |
198 | u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ | |
199 | u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ | |
200 | /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ | |
201 | u64 rxpok; | |
202 | u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ | |
203 | u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ | |
204 | u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ | |
205 | u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ | |
206 | u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ | |
207 | /* HSI - Cannot add more stats to this struct. If needed, then need to open new | |
208 | * struct | |
209 | */ | |
210 | ||
211 | }; | |
212 | ||
213 | struct brb_stats { | |
214 | u64 brb_truncate[8]; | |
215 | u64 brb_discard[8]; | |
216 | }; | |
217 | ||
218 | struct port_stats { | |
219 | struct brb_stats brb; | |
220 | struct eth_stats eth; | |
221 | }; | |
222 | ||
223 | /*----+------------------------------------------------------------------------ | |
224 | * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines | |
225 | * h | rate of | team #1 | team #2 |are used|per path | (paths) | |
226 | * i | physical | | | | | enabled | |
227 | * p | ports | | | | | | |
228 | *====+============+=========+=========+========+==========+=================== | |
229 | * BB | 1x100G | This is special mode, where there are actually 2 HW func | |
230 | * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1 | |
231 | * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 | |
232 | * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 | |
233 | * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) | |
234 | * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) | |
235 | * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) | |
236 | * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 | |
237 | * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA | |
238 | * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA | |
239 | * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA | |
240 | * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA | |
241 | * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA | |
242 | *====+============+=========+=========+========+==========+=================== | |
243 | */ | |
244 | ||
245 | #define CMT_TEAM0 0 | |
246 | #define CMT_TEAM1 1 | |
247 | #define CMT_TEAM_MAX 2 | |
248 | ||
249 | struct couple_mode_teaming { | |
250 | u8 port_cmt[MCP_GLOB_PORT_MAX]; | |
251 | #define PORT_CMT_IN_TEAM (1 << 0) | |
252 | ||
253 | #define PORT_CMT_PORT_ROLE (1 << 1) | |
254 | #define PORT_CMT_PORT_INACTIVE (0 << 1) | |
255 | #define PORT_CMT_PORT_ACTIVE (1 << 1) | |
256 | ||
257 | #define PORT_CMT_TEAM_MASK (1 << 2) | |
258 | #define PORT_CMT_TEAM0 (0 << 2) | |
259 | #define PORT_CMT_TEAM1 (1 << 2) | |
260 | }; | |
261 | ||
262 | /************************************** | |
263 | * LLDP and DCBX HSI structures | |
264 | **************************************/ | |
9f95a23c TL |
265 | #define LLDP_CHASSIS_ID_STAT_LEN 4 |
266 | #define LLDP_PORT_ID_STAT_LEN 4 | |
7c673cae | 267 | #define DCBX_MAX_APP_PROTOCOL 32 |
9f95a23c TL |
268 | #define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/ |
269 | #define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ | |
7c673cae FG |
270 | typedef enum _lldp_agent_e { |
271 | LLDP_NEAREST_BRIDGE = 0, | |
272 | LLDP_NEAREST_NON_TPMR_BRIDGE, | |
273 | LLDP_NEAREST_CUSTOMER_BRIDGE, | |
274 | LLDP_MAX_LLDP_AGENTS | |
275 | } lldp_agent_e; | |
276 | ||
277 | struct lldp_config_params_s { | |
278 | u32 config; | |
279 | #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff | |
9f95a23c | 280 | #define LLDP_CONFIG_TX_INTERVAL_OFFSET 0 |
7c673cae | 281 | #define LLDP_CONFIG_HOLD_MASK 0x00000f00 |
9f95a23c | 282 | #define LLDP_CONFIG_HOLD_OFFSET 8 |
7c673cae | 283 | #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 |
9f95a23c | 284 | #define LLDP_CONFIG_MAX_CREDIT_OFFSET 12 |
7c673cae | 285 | #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 |
9f95a23c | 286 | #define LLDP_CONFIG_ENABLE_RX_OFFSET 30 |
7c673cae | 287 | #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 |
9f95a23c | 288 | #define LLDP_CONFIG_ENABLE_TX_OFFSET 31 |
7c673cae FG |
289 | /* Holds local Chassis ID TLV header, subtype and 9B of payload. |
290 | * If firtst byte is 0, then we will use default chassis ID | |
291 | */ | |
292 | u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; | |
293 | /* Holds local Port ID TLV header, subtype and 9B of payload. | |
294 | * If firtst byte is 0, then we will use default port ID | |
295 | */ | |
296 | u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; | |
297 | }; | |
298 | ||
299 | struct lldp_status_params_s { | |
300 | u32 prefix_seq_num; | |
301 | u32 status; /* TBD */ | |
302 | /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ | |
303 | u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; | |
304 | /* Holds remote Port ID TLV header, subtype and 9B of payload. */ | |
305 | u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; | |
306 | u32 suffix_seq_num; | |
307 | }; | |
308 | ||
309 | struct dcbx_ets_feature { | |
310 | u32 flags; | |
311 | #define DCBX_ETS_ENABLED_MASK 0x00000001 | |
9f95a23c | 312 | #define DCBX_ETS_ENABLED_OFFSET 0 |
7c673cae | 313 | #define DCBX_ETS_WILLING_MASK 0x00000002 |
9f95a23c | 314 | #define DCBX_ETS_WILLING_OFFSET 1 |
7c673cae | 315 | #define DCBX_ETS_ERROR_MASK 0x00000004 |
9f95a23c | 316 | #define DCBX_ETS_ERROR_OFFSET 2 |
7c673cae | 317 | #define DCBX_ETS_CBS_MASK 0x00000008 |
9f95a23c | 318 | #define DCBX_ETS_CBS_OFFSET 3 |
7c673cae | 319 | #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 |
9f95a23c | 320 | #define DCBX_ETS_MAX_TCS_OFFSET 4 |
11fdf7f2 | 321 | #define DCBX_OOO_TC_MASK 0x00000f00 |
9f95a23c | 322 | #define DCBX_OOO_TC_OFFSET 8 |
7c673cae FG |
323 | /* Entries in tc table are orginized that the left most is pri 0, right most is |
324 | * prio 7 | |
325 | */ | |
326 | ||
327 | u32 pri_tc_tbl[1]; | |
11fdf7f2 TL |
328 | /* Fixed TCP OOO TC usage is deprecated and used only for driver backward |
329 | * compatibility | |
330 | */ | |
331 | #define DCBX_TCP_OOO_TC (4) | |
332 | #define DCBX_TCP_OOO_K2_4PORT_TC (3) | |
7c673cae | 333 | |
11fdf7f2 | 334 | #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) |
7c673cae FG |
335 | #define DCBX_CEE_STRICT_PRIORITY 0xf |
336 | /* Entries in tc table are orginized that the left most is pri 0, right most is | |
337 | * prio 7 | |
338 | */ | |
339 | ||
340 | u32 tc_bw_tbl[2]; | |
341 | /* Entries in tc table are orginized that the left most is pri 0, right most is | |
342 | * prio 7 | |
343 | */ | |
344 | ||
345 | u32 tc_tsa_tbl[2]; | |
346 | #define DCBX_ETS_TSA_STRICT 0 | |
347 | #define DCBX_ETS_TSA_CBS 1 | |
348 | #define DCBX_ETS_TSA_ETS 2 | |
349 | }; | |
350 | ||
351 | struct dcbx_app_priority_entry { | |
352 | u32 entry; | |
353 | #define DCBX_APP_PRI_MAP_MASK 0x000000ff | |
9f95a23c | 354 | #define DCBX_APP_PRI_MAP_OFFSET 0 |
7c673cae FG |
355 | #define DCBX_APP_PRI_0 0x01 |
356 | #define DCBX_APP_PRI_1 0x02 | |
357 | #define DCBX_APP_PRI_2 0x04 | |
358 | #define DCBX_APP_PRI_3 0x08 | |
359 | #define DCBX_APP_PRI_4 0x10 | |
360 | #define DCBX_APP_PRI_5 0x20 | |
361 | #define DCBX_APP_PRI_6 0x40 | |
362 | #define DCBX_APP_PRI_7 0x80 | |
363 | #define DCBX_APP_SF_MASK 0x00000300 | |
9f95a23c | 364 | #define DCBX_APP_SF_OFFSET 8 |
7c673cae FG |
365 | #define DCBX_APP_SF_ETHTYPE 0 |
366 | #define DCBX_APP_SF_PORT 1 | |
367 | #define DCBX_APP_SF_IEEE_MASK 0x0000f000 | |
9f95a23c | 368 | #define DCBX_APP_SF_IEEE_OFFSET 12 |
7c673cae FG |
369 | #define DCBX_APP_SF_IEEE_RESERVED 0 |
370 | #define DCBX_APP_SF_IEEE_ETHTYPE 1 | |
371 | #define DCBX_APP_SF_IEEE_TCP_PORT 2 | |
372 | #define DCBX_APP_SF_IEEE_UDP_PORT 3 | |
373 | #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 | |
374 | ||
375 | #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 | |
9f95a23c | 376 | #define DCBX_APP_PROTOCOL_ID_OFFSET 16 |
7c673cae FG |
377 | }; |
378 | ||
379 | ||
380 | /* FW structure in BE */ | |
381 | struct dcbx_app_priority_feature { | |
382 | u32 flags; | |
383 | #define DCBX_APP_ENABLED_MASK 0x00000001 | |
9f95a23c | 384 | #define DCBX_APP_ENABLED_OFFSET 0 |
7c673cae | 385 | #define DCBX_APP_WILLING_MASK 0x00000002 |
9f95a23c | 386 | #define DCBX_APP_WILLING_OFFSET 1 |
7c673cae | 387 | #define DCBX_APP_ERROR_MASK 0x00000004 |
9f95a23c | 388 | #define DCBX_APP_ERROR_OFFSET 2 |
7c673cae FG |
389 | /* Not in use |
390 | #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 | |
9f95a23c | 391 | #define DCBX_APP_DEFAULT_PRI_OFFSET 8 |
7c673cae FG |
392 | */ |
393 | #define DCBX_APP_MAX_TCS_MASK 0x0000f000 | |
9f95a23c | 394 | #define DCBX_APP_MAX_TCS_OFFSET 12 |
7c673cae | 395 | #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 |
9f95a23c | 396 | #define DCBX_APP_NUM_ENTRIES_OFFSET 16 |
7c673cae FG |
397 | struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; |
398 | }; | |
399 | ||
400 | /* FW structure in BE */ | |
401 | struct dcbx_features { | |
402 | /* PG feature */ | |
403 | struct dcbx_ets_feature ets; | |
404 | /* PFC feature */ | |
405 | u32 pfc; | |
406 | #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff | |
9f95a23c | 407 | #define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0 |
7c673cae FG |
408 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 |
409 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 | |
410 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 | |
411 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 | |
412 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 | |
413 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 | |
414 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 | |
415 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 | |
416 | ||
417 | #define DCBX_PFC_FLAGS_MASK 0x0000ff00 | |
9f95a23c | 418 | #define DCBX_PFC_FLAGS_OFFSET 8 |
7c673cae | 419 | #define DCBX_PFC_CAPS_MASK 0x00000f00 |
9f95a23c | 420 | #define DCBX_PFC_CAPS_OFFSET 8 |
7c673cae | 421 | #define DCBX_PFC_MBC_MASK 0x00004000 |
9f95a23c | 422 | #define DCBX_PFC_MBC_OFFSET 14 |
7c673cae | 423 | #define DCBX_PFC_WILLING_MASK 0x00008000 |
9f95a23c | 424 | #define DCBX_PFC_WILLING_OFFSET 15 |
7c673cae | 425 | #define DCBX_PFC_ENABLED_MASK 0x00010000 |
9f95a23c | 426 | #define DCBX_PFC_ENABLED_OFFSET 16 |
7c673cae | 427 | #define DCBX_PFC_ERROR_MASK 0x00020000 |
9f95a23c | 428 | #define DCBX_PFC_ERROR_OFFSET 17 |
7c673cae FG |
429 | |
430 | /* APP feature */ | |
431 | struct dcbx_app_priority_feature app; | |
432 | }; | |
433 | ||
434 | struct dcbx_local_params { | |
435 | u32 config; | |
436 | #define DCBX_CONFIG_VERSION_MASK 0x00000007 | |
9f95a23c | 437 | #define DCBX_CONFIG_VERSION_OFFSET 0 |
7c673cae FG |
438 | #define DCBX_CONFIG_VERSION_DISABLED 0 |
439 | #define DCBX_CONFIG_VERSION_IEEE 1 | |
440 | #define DCBX_CONFIG_VERSION_CEE 2 | |
9f95a23c TL |
441 | #define DCBX_CONFIG_VERSION_DYNAMIC \ |
442 | (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE) | |
7c673cae FG |
443 | #define DCBX_CONFIG_VERSION_STATIC 4 |
444 | ||
445 | u32 flags; | |
446 | struct dcbx_features features; | |
447 | }; | |
448 | ||
449 | struct dcbx_mib { | |
450 | u32 prefix_seq_num; | |
451 | u32 flags; | |
452 | /* | |
453 | #define DCBX_CONFIG_VERSION_MASK 0x00000007 | |
9f95a23c | 454 | #define DCBX_CONFIG_VERSION_OFFSET 0 |
7c673cae FG |
455 | #define DCBX_CONFIG_VERSION_DISABLED 0 |
456 | #define DCBX_CONFIG_VERSION_IEEE 1 | |
457 | #define DCBX_CONFIG_VERSION_CEE 2 | |
458 | #define DCBX_CONFIG_VERSION_STATIC 4 | |
459 | */ | |
460 | struct dcbx_features features; | |
461 | u32 suffix_seq_num; | |
462 | }; | |
463 | ||
464 | struct lldp_system_tlvs_buffer_s { | |
9f95a23c TL |
465 | u32 flags; |
466 | #define LLDP_SYSTEM_TLV_VALID_MASK 0x1 | |
467 | #define LLDP_SYSTEM_TLV_VALID_OFFSET 0 | |
468 | /* This bit defines if system TLVs are instead of mandatory TLVS or in | |
469 | * addition to them. Set 1 for replacing mandatory TLVs | |
470 | */ | |
471 | #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 | |
472 | #define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1 | |
473 | #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 | |
474 | #define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16 | |
7c673cae FG |
475 | u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; |
476 | }; | |
477 | ||
9f95a23c TL |
478 | /* Since this struct is written by MFW and read by driver need to add |
479 | * sequence guards (as in case of DCBX MIB) | |
480 | */ | |
481 | struct lldp_received_tlvs_s { | |
482 | u32 prefix_seq_num; | |
483 | u32 length; | |
484 | u32 tlvs_buffer[MAX_TLV_BUFFER]; | |
485 | u32 suffix_seq_num; | |
486 | }; | |
487 | ||
7c673cae FG |
488 | struct dcb_dscp_map { |
489 | u32 flags; | |
490 | #define DCB_DSCP_ENABLE_MASK 0x1 | |
9f95a23c | 491 | #define DCB_DSCP_ENABLE_OFFSET 0 |
7c673cae FG |
492 | #define DCB_DSCP_ENABLE 1 |
493 | u32 dscp_pri_map[8]; | |
494 | }; | |
495 | ||
9f95a23c TL |
496 | /************************************** |
497 | * Attributes commands | |
498 | **************************************/ | |
499 | ||
500 | enum _attribute_commands_e { | |
501 | ATTRIBUTE_CMD_READ = 0, | |
502 | ATTRIBUTE_CMD_WRITE, | |
503 | ATTRIBUTE_CMD_READ_CLEAR, | |
504 | ATTRIBUTE_CMD_CLEAR, | |
505 | ATTRIBUTE_NUM_OF_COMMANDS | |
506 | }; | |
507 | ||
7c673cae FG |
508 | /**************************************/ |
509 | /* */ | |
510 | /* P U B L I C G L O B A L */ | |
511 | /* */ | |
512 | /**************************************/ | |
513 | struct public_global { | |
514 | u32 max_path; /* 32bit is wasty, but this will be used often */ | |
515 | /* (Global) 32bit is wasty, but this will be used often */ | |
516 | u32 max_ports; | |
517 | #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ | |
518 | #define MODE_2P 2 | |
519 | #define MODE_3P 3 | |
520 | #define MODE_4P 4 | |
521 | u32 debug_mb_offset; | |
522 | u32 phymod_dbg_mb_offset; | |
523 | struct couple_mode_teaming cmt; | |
524 | /* Temperature in Celcius (-255C / +255C), measured every second. */ | |
525 | s32 internal_temperature; | |
526 | u32 mfw_ver; | |
527 | u32 running_bundle_id; | |
528 | s32 external_temperature; | |
529 | u32 mdump_reason; | |
530 | #define MDUMP_REASON_INTERNAL_ERROR (1 << 0) | |
531 | #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) | |
532 | #define MDUMP_REASON_DUMP_AGED (1 << 2) | |
11fdf7f2 TL |
533 | u32 ext_phy_upgrade_fw; |
534 | #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) | |
9f95a23c | 535 | #define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0) |
11fdf7f2 TL |
536 | #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) |
537 | #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) | |
538 | #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) | |
539 | #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) | |
9f95a23c | 540 | #define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16) |
7c673cae FG |
541 | }; |
542 | ||
543 | /**************************************/ | |
544 | /* */ | |
545 | /* P U B L I C P A T H */ | |
546 | /* */ | |
547 | /**************************************/ | |
548 | ||
549 | /**************************************************************************** | |
550 | * Shared Memory 2 Region * | |
551 | ****************************************************************************/ | |
552 | /* The fw_flr_ack is actually built in the following way: */ | |
553 | /* 8 bit: PF ack */ | |
554 | /* 128 bit: VF ack */ | |
555 | /* 8 bit: ios_dis_ack */ | |
556 | /* In order to maintain endianity in the mailbox hsi, we want to keep using */ | |
557 | /* u32. The fw must have the VF right after the PF since this is how it */ | |
558 | /* access arrays(it expects always the VF to reside after the PF, and that */ | |
559 | /* makes the calculation much easier for it. ) */ | |
560 | /* In order to answer both limitations, and keep the struct small, the code */ | |
561 | /* will abuse the structure defined here to achieve the actual partition */ | |
562 | /* above */ | |
563 | /****************************************************************************/ | |
564 | struct fw_flr_mb { | |
565 | u32 aggint; | |
566 | u32 opgen_addr; | |
567 | u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ | |
568 | #define ACCUM_ACK_PF_BASE 0 | |
569 | #define ACCUM_ACK_PF_SHIFT 0 | |
570 | ||
571 | #define ACCUM_ACK_VF_BASE 8 | |
572 | #define ACCUM_ACK_VF_SHIFT 3 | |
573 | ||
574 | #define ACCUM_ACK_IOV_DIS_BASE 256 | |
575 | #define ACCUM_ACK_IOV_DIS_SHIFT 8 | |
576 | ||
577 | }; | |
578 | ||
579 | struct public_path { | |
580 | struct fw_flr_mb flr_mb; | |
581 | /* | |
582 | * mcp_vf_disabled is set by the MCP to indicate the driver about VFs | |
583 | * which were disabled/flred | |
584 | */ | |
585 | u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ | |
586 | ||
587 | /* Reset on mcp reset, and incremented for eveny process kill event. */ | |
588 | u32 process_kill; | |
589 | #define PROCESS_KILL_COUNTER_MASK 0x0000ffff | |
9f95a23c | 590 | #define PROCESS_KILL_COUNTER_OFFSET 0 |
7c673cae | 591 | #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 |
9f95a23c | 592 | #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 |
7c673cae FG |
593 | #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) |
594 | }; | |
595 | ||
596 | /**************************************/ | |
597 | /* */ | |
598 | /* P U B L I C P O R T */ | |
599 | /* */ | |
600 | /**************************************/ | |
601 | #define FC_NPIV_WWPN_SIZE 8 | |
602 | #define FC_NPIV_WWNN_SIZE 8 | |
603 | struct dci_npiv_settings { | |
604 | u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; | |
605 | u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; | |
606 | }; | |
607 | ||
608 | struct dci_fc_npiv_cfg { | |
609 | /* hdr used internally by the MFW */ | |
610 | u32 hdr; | |
611 | u32 num_of_npiv; | |
612 | }; | |
613 | ||
614 | #define MAX_NUMBER_NPIV 64 | |
615 | struct dci_fc_npiv_tbl { | |
616 | struct dci_fc_npiv_cfg fc_npiv_cfg; | |
617 | struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; | |
618 | }; | |
619 | ||
620 | /**************************************************************************** | |
621 | * Driver <-> FW Mailbox * | |
622 | ****************************************************************************/ | |
623 | ||
624 | struct public_port { | |
625 | u32 validity_map; /* 0x0 (4*2 = 0x8) */ | |
626 | ||
627 | /* validity bits */ | |
628 | #define MCP_VALIDITY_PCI_CFG 0x00100000 | |
629 | #define MCP_VALIDITY_MB 0x00200000 | |
630 | #define MCP_VALIDITY_DEV_INFO 0x00400000 | |
631 | #define MCP_VALIDITY_RESERVED 0x00000007 | |
632 | ||
633 | /* One licensing bit should be set */ | |
634 | /* yaniv - tbd ? license */ | |
635 | #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 | |
636 | #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 | |
637 | #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 | |
638 | #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 | |
639 | ||
640 | /* Active MFW */ | |
641 | #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 | |
642 | #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 | |
643 | #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 | |
644 | #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 | |
645 | ||
646 | u32 link_status; | |
11fdf7f2 TL |
647 | #define LINK_STATUS_LINK_UP 0x00000001 |
648 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e | |
7c673cae FG |
649 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) |
650 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) | |
11fdf7f2 TL |
651 | #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) |
652 | #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) | |
653 | #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) | |
654 | #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) | |
655 | #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) | |
656 | #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) | |
657 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
658 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | |
659 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
660 | #define LINK_STATUS_PFC_ENABLED 0x00000100 | |
7c673cae FG |
661 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 |
662 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
663 | #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 | |
664 | #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 | |
665 | #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 | |
666 | #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 | |
667 | #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 | |
668 | #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 | |
7c673cae FG |
669 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 |
670 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) | |
671 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) | |
672 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) | |
11fdf7f2 TL |
673 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) |
674 | #define LINK_STATUS_SFP_TX_FAULT 0x00100000 | |
675 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 | |
676 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 | |
677 | #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 | |
678 | #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 | |
679 | #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 | |
680 | #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 | |
681 | #define LINK_STATUS_FEC_MODE_MASK 0x38000000 | |
682 | #define LINK_STATUS_FEC_MODE_NONE (0 << 27) | |
683 | #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27) | |
684 | #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27) | |
685 | #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 | |
7c673cae FG |
686 | |
687 | u32 link_status1; | |
688 | u32 ext_phy_fw_version; | |
689 | /* Points to struct eth_phy_cfg (For READ-ONLY) */ | |
690 | u32 drv_phy_cfg_addr; | |
691 | ||
692 | u32 port_stx; | |
693 | ||
694 | u32 stat_nig_timer; | |
695 | ||
696 | struct port_mf_cfg port_mf_config; | |
697 | struct port_stats stats; | |
698 | ||
699 | u32 media_type; | |
700 | #define MEDIA_UNSPECIFIED 0x0 | |
701 | #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ | |
702 | #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ | |
703 | #define MEDIA_DA_TWINAX 0x3 | |
704 | #define MEDIA_BASE_T 0x4 | |
705 | #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ | |
706 | #define MEDIA_MODULE_FIBER 0x6 | |
707 | #define MEDIA_KR 0xf0 | |
708 | #define MEDIA_NOT_PRESENT 0xff | |
709 | ||
710 | u32 lfa_status; | |
711 | #define LFA_LINK_FLAP_REASON_OFFSET 0 | |
712 | #define LFA_LINK_FLAP_REASON_MASK 0x000000ff | |
713 | #define LFA_NO_REASON (0 << 0) | |
714 | #define LFA_LINK_DOWN (1 << 0) | |
715 | #define LFA_FORCE_INIT (1 << 1) | |
716 | #define LFA_LOOPBACK_MISMATCH (1 << 2) | |
717 | #define LFA_SPEED_MISMATCH (1 << 3) | |
718 | #define LFA_FLOW_CTRL_MISMATCH (1 << 4) | |
719 | #define LFA_ADV_SPEED_MISMATCH (1 << 5) | |
9f95a23c TL |
720 | #define LFA_EEE_MISMATCH (1 << 6) |
721 | #define LFA_LINK_MODES_MISMATCH (1 << 7) | |
7c673cae FG |
722 | #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 |
723 | #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 | |
724 | #define LINK_FLAP_COUNT_OFFSET 16 | |
725 | #define LINK_FLAP_COUNT_MASK 0x00ff0000 | |
726 | ||
727 | u32 link_change_count; | |
728 | ||
729 | /* LLDP params */ | |
730 | /* offset: 536 bytes? */ | |
731 | struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; | |
732 | struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; | |
733 | struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; | |
734 | ||
735 | /* DCBX related MIB */ | |
736 | struct dcbx_local_params local_admin_dcbx_mib; | |
737 | struct dcbx_mib remote_dcbx_mib; | |
738 | struct dcbx_mib operational_dcbx_mib; | |
739 | ||
740 | /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ | |
741 | ||
742 | u32 fc_npiv_nvram_tbl_addr; | |
743 | u32 fc_npiv_nvram_tbl_size; | |
744 | u32 transceiver_data; | |
11fdf7f2 | 745 | #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF |
9f95a23c | 746 | #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000 |
11fdf7f2 TL |
747 | #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 |
748 | #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 | |
749 | #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 | |
750 | #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 | |
751 | #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 | |
9f95a23c | 752 | #define ETH_TRANSCEIVER_TYPE_OFFSET 0x00000008 |
11fdf7f2 TL |
753 | #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000 |
754 | #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF | |
7c673cae | 755 | /* 1G Passive copper cable */ |
11fdf7f2 | 756 | #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 |
7c673cae | 757 | /* 1G Active copper cable */ |
11fdf7f2 TL |
758 | #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 |
759 | #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 | |
760 | #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 | |
761 | #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 | |
762 | #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 | |
763 | #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 | |
764 | #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 | |
7c673cae | 765 | /* 10G Passive copper cable */ |
11fdf7f2 | 766 | #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 |
7c673cae | 767 | /* 10G Active copper cable */ |
11fdf7f2 TL |
768 | #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a |
769 | #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b | |
770 | #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c | |
771 | #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d | |
772 | #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e | |
773 | /* Active optical cable */ | |
774 | #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f | |
775 | #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 | |
776 | #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 | |
777 | #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 | |
778 | /* Active copper cable */ | |
779 | #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 | |
780 | #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 | |
781 | #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 | |
7c673cae | 782 | /* 25G Passive copper cable - short */ |
11fdf7f2 | 783 | #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 |
7c673cae | 784 | /* 25G Active copper cable - short */ |
11fdf7f2 | 785 | #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 |
7c673cae FG |
786 | /* 25G Passive copper cable - medium */ |
787 | #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 | |
788 | /* 25G Active copper cable - medium */ | |
789 | #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 | |
790 | /* 25G Passive copper cable - long */ | |
791 | #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a | |
792 | /* 25G Active copper cable - long */ | |
793 | #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b | |
794 | #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c | |
795 | #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d | |
796 | #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e | |
797 | ||
798 | #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f | |
799 | #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 | |
9f95a23c TL |
800 | #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 |
801 | #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 | |
7c673cae FG |
802 | #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 |
803 | #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 | |
804 | #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 | |
805 | #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 | |
806 | #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 | |
807 | #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 | |
808 | #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 | |
809 | u32 wol_info; | |
810 | u32 wol_pkt_len; | |
811 | u32 wol_pkt_details; | |
812 | struct dcb_dscp_map dcb_dscp_map; | |
11fdf7f2 | 813 | |
11fdf7f2 | 814 | u32 eee_status; |
9f95a23c TL |
815 | /* Set when EEE negotiation is complete. */ |
816 | #define EEE_ACTIVE_BIT (1 << 0) | |
817 | ||
818 | /* Shows the Local Device EEE capabilities */ | |
819 | #define EEE_LD_ADV_STATUS_MASK 0x000000f0 | |
820 | #define EEE_LD_ADV_STATUS_OFFSET 4 | |
821 | #define EEE_1G_ADV (1 << 1) | |
822 | #define EEE_10G_ADV (1 << 2) | |
823 | /* Same values as in EEE_LD_ADV, but for Link Parter */ | |
824 | #define EEE_LP_ADV_STATUS_MASK 0x00000f00 | |
825 | #define EEE_LP_ADV_STATUS_OFFSET 8 | |
826 | ||
827 | /* Supported speeds for EEE */ | |
828 | #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 | |
829 | #define EEE_SUPPORTED_SPEED_OFFSET 12 | |
830 | #define EEE_1G_SUPPORTED (1 << 1) | |
831 | #define EEE_10G_SUPPORTED (1 << 2) | |
11fdf7f2 TL |
832 | |
833 | u32 eee_remote; /* Used for EEE in LLDP */ | |
834 | #define EEE_REMOTE_TW_TX_MASK 0x0000ffff | |
9f95a23c | 835 | #define EEE_REMOTE_TW_TX_OFFSET 0 |
11fdf7f2 | 836 | #define EEE_REMOTE_TW_RX_MASK 0xffff0000 |
9f95a23c TL |
837 | #define EEE_REMOTE_TW_RX_OFFSET 16 |
838 | ||
839 | u32 module_info; | |
840 | #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF | |
841 | #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0 | |
842 | #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2) | |
843 | #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3) | |
844 | #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4) | |
845 | #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5) | |
846 | #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) | |
847 | #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 | |
848 | #define ETH_TRANSCEIVER_IDENT_OFFSET 8 | |
849 | ||
850 | u32 oem_cfg_port; | |
851 | #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 | |
852 | #define OEM_CFG_CHANNEL_TYPE_OFFSET 0 | |
853 | #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 | |
854 | #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 | |
855 | ||
856 | #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C | |
857 | #define OEM_CFG_SCHED_TYPE_OFFSET 2 | |
858 | #define OEM_CFG_SCHED_TYPE_ETS 0x1 | |
859 | #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 | |
860 | ||
861 | struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; | |
862 | u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; | |
7c673cae FG |
863 | }; |
864 | ||
865 | /**************************************/ | |
866 | /* */ | |
867 | /* P U B L I C F U N C */ | |
868 | /* */ | |
869 | /**************************************/ | |
870 | ||
871 | struct public_func { | |
872 | u32 iscsi_boot_signature; | |
873 | u32 iscsi_boot_block_offset; | |
874 | ||
875 | /* MTU size per funciton is needed for the OV feature */ | |
876 | u32 mtu_size; | |
877 | /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ | |
878 | ||
879 | /* For PCP values 0-3 use the map lower */ | |
880 | /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, | |
881 | * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 | |
882 | */ | |
883 | u32 c2s_pcp_map_lower; | |
884 | /* For PCP values 4-7 use the map upper */ | |
885 | /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, | |
886 | * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 | |
887 | */ | |
888 | u32 c2s_pcp_map_upper; | |
889 | ||
890 | /* For PCP default value get the MSB byte of the map default */ | |
891 | u32 c2s_pcp_map_default; | |
892 | ||
893 | u32 reserved[4]; | |
894 | ||
895 | /* replace old mf_cfg */ | |
896 | u32 config; | |
897 | /* E/R/I/D */ | |
898 | /* function 0 of each port cannot be hidden */ | |
899 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 | |
900 | #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 | |
9f95a23c | 901 | #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001 |
7c673cae FG |
902 | |
903 | ||
904 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 | |
9f95a23c | 905 | #define FUNC_MF_CFG_PROTOCOL_OFFSET 4 |
7c673cae FG |
906 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 |
907 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 | |
908 | #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 | |
909 | #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 | |
910 | #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 | |
911 | ||
912 | /* MINBW, MAXBW */ | |
913 | /* value range - 0..100, increments in 1 % */ | |
914 | #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 | |
9f95a23c | 915 | #define FUNC_MF_CFG_MIN_BW_OFFSET 8 |
7c673cae FG |
916 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 |
917 | #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 | |
9f95a23c | 918 | #define FUNC_MF_CFG_MAX_BW_OFFSET 16 |
7c673cae FG |
919 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 |
920 | ||
921 | u32 status; | |
9f95a23c TL |
922 | #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 |
923 | #define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002 | |
924 | #define FUNC_STATUS_FORCED_LINK 0x00000004 | |
7c673cae FG |
925 | |
926 | u32 mac_upper; /* MAC */ | |
927 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff | |
9f95a23c | 928 | #define FUNC_MF_CFG_UPPERMAC_OFFSET 0 |
7c673cae FG |
929 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK |
930 | u32 mac_lower; | |
931 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff | |
932 | ||
933 | u32 fcoe_wwn_port_name_upper; | |
934 | u32 fcoe_wwn_port_name_lower; | |
935 | ||
936 | u32 fcoe_wwn_node_name_upper; | |
937 | u32 fcoe_wwn_node_name_lower; | |
938 | ||
939 | u32 ovlan_stag; /* tags */ | |
940 | #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff | |
9f95a23c | 941 | #define FUNC_MF_CFG_OV_STAG_OFFSET 0 |
7c673cae FG |
942 | #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK |
943 | ||
944 | u32 pf_allocation; /* vf per pf */ | |
945 | ||
946 | u32 preserve_data; /* Will be used bt CCM */ | |
947 | ||
948 | u32 driver_last_activity_ts; | |
949 | ||
950 | /* | |
951 | * drv_ack_vf_disabled is set by the PF driver to ack handled disabled | |
952 | * VFs | |
953 | */ | |
954 | u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ | |
955 | ||
956 | u32 drv_id; | |
957 | #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff | |
9f95a23c | 958 | #define DRV_ID_PDA_COMP_VER_OFFSET 0 |
7c673cae | 959 | |
11fdf7f2 | 960 | #define LOAD_REQ_HSI_VERSION 2 |
7c673cae | 961 | #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 |
9f95a23c | 962 | #define DRV_ID_MCP_HSI_VER_OFFSET 16 |
11fdf7f2 | 963 | #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ |
9f95a23c | 964 | DRV_ID_MCP_HSI_VER_OFFSET) |
7c673cae FG |
965 | |
966 | #define DRV_ID_DRV_TYPE_MASK 0x7f000000 | |
9f95a23c TL |
967 | #define DRV_ID_DRV_TYPE_OFFSET 24 |
968 | #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET) | |
969 | #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET) | |
970 | #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET) | |
971 | #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET) | |
972 | #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET) | |
973 | #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET) | |
974 | #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET) | |
975 | #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET) | |
976 | #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET) | |
7c673cae FG |
977 | |
978 | #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 | |
9f95a23c TL |
979 | #define DRV_ID_DRV_INIT_HW_OFFSET 31 |
980 | #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET) | |
981 | ||
982 | u32 oem_cfg_func; | |
983 | #define OEM_CFG_FUNC_TC_MASK 0x0000000F | |
984 | #define OEM_CFG_FUNC_TC_OFFSET 0 | |
985 | #define OEM_CFG_FUNC_TC_0 0x0 | |
986 | #define OEM_CFG_FUNC_TC_1 0x1 | |
987 | #define OEM_CFG_FUNC_TC_2 0x2 | |
988 | #define OEM_CFG_FUNC_TC_3 0x3 | |
989 | #define OEM_CFG_FUNC_TC_4 0x4 | |
990 | #define OEM_CFG_FUNC_TC_5 0x5 | |
991 | #define OEM_CFG_FUNC_TC_6 0x6 | |
992 | #define OEM_CFG_FUNC_TC_7 0x7 | |
993 | ||
994 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 | |
995 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 | |
996 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 | |
997 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 | |
7c673cae FG |
998 | }; |
999 | ||
1000 | /**************************************/ | |
1001 | /* */ | |
1002 | /* P U B L I C M B */ | |
1003 | /* */ | |
1004 | /**************************************/ | |
1005 | /* This is the only section that the driver can write to, and each */ | |
1006 | /* Basically each driver request to set feature parameters, | |
1007 | * will be done using a different command, which will be linked | |
1008 | * to a specific data structure from the union below. | |
1009 | * For huge strucuture, the common blank structure should be used. | |
1010 | */ | |
1011 | ||
1012 | struct mcp_mac { | |
1013 | u32 mac_upper; /* Upper 16 bits are always zeroes */ | |
1014 | u32 mac_lower; | |
1015 | }; | |
1016 | ||
1017 | struct mcp_val64 { | |
1018 | u32 lo; | |
1019 | u32 hi; | |
1020 | }; | |
1021 | ||
1022 | struct mcp_file_att { | |
1023 | u32 nvm_start_addr; | |
1024 | u32 len; | |
1025 | }; | |
1026 | ||
1027 | struct bist_nvm_image_att { | |
1028 | u32 return_code; | |
1029 | u32 image_type; /* Image type */ | |
1030 | u32 nvm_start_addr; /* NVM address of the image */ | |
1031 | u32 len; /* Include CRC */ | |
1032 | }; | |
1033 | ||
1034 | #define MCP_DRV_VER_STR_SIZE 16 | |
1035 | #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) | |
1036 | #define MCP_DRV_NVM_BUF_LEN 32 | |
1037 | struct drv_version_stc { | |
1038 | u32 version; | |
1039 | u8 name[MCP_DRV_VER_STR_SIZE - 4]; | |
1040 | }; | |
1041 | ||
1042 | /* statistics for ncsi */ | |
1043 | struct lan_stats_stc { | |
1044 | u64 ucast_rx_pkts; | |
1045 | u64 ucast_tx_pkts; | |
1046 | u32 fcs_err; | |
1047 | u32 rserved; | |
1048 | }; | |
1049 | ||
1050 | struct fcoe_stats_stc { | |
1051 | u64 rx_pkts; | |
1052 | u64 tx_pkts; | |
1053 | u32 fcs_err; | |
1054 | u32 login_failure; | |
1055 | }; | |
1056 | ||
1057 | struct iscsi_stats_stc { | |
1058 | u64 rx_pdus; | |
1059 | u64 tx_pdus; | |
1060 | u64 rx_bytes; | |
1061 | u64 tx_bytes; | |
1062 | }; | |
1063 | ||
1064 | struct rdma_stats_stc { | |
1065 | u64 rx_pkts; | |
1066 | u64 tx_pkts; | |
1067 | u64 rx_bytes; | |
1068 | u64 tx_bytes; | |
1069 | }; | |
1070 | ||
1071 | struct ocbb_data_stc { | |
1072 | u32 ocbb_host_addr; | |
1073 | u32 ocsd_host_addr; | |
1074 | u32 ocsd_req_update_interval; | |
1075 | }; | |
1076 | ||
1077 | #define MAX_NUM_OF_SENSORS 7 | |
1078 | #define MFW_SENSOR_LOCATION_INTERNAL 1 | |
1079 | #define MFW_SENSOR_LOCATION_EXTERNAL 2 | |
1080 | #define MFW_SENSOR_LOCATION_SFP 3 | |
1081 | ||
9f95a23c | 1082 | #define SENSOR_LOCATION_OFFSET 0 |
7c673cae | 1083 | #define SENSOR_LOCATION_MASK 0x000000ff |
9f95a23c | 1084 | #define THRESHOLD_HIGH_OFFSET 8 |
7c673cae | 1085 | #define THRESHOLD_HIGH_MASK 0x0000ff00 |
9f95a23c | 1086 | #define CRITICAL_TEMPERATURE_OFFSET 16 |
7c673cae | 1087 | #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 |
9f95a23c | 1088 | #define CURRENT_TEMP_OFFSET 24 |
7c673cae FG |
1089 | #define CURRENT_TEMP_MASK 0xff000000 |
1090 | struct temperature_status_stc { | |
1091 | u32 num_of_sensors; | |
1092 | u32 sensor[MAX_NUM_OF_SENSORS]; | |
1093 | }; | |
1094 | ||
1095 | /* crash dump configuration header */ | |
1096 | struct mdump_config_stc { | |
1097 | u32 version; | |
1098 | u32 config; | |
1099 | u32 epoc; | |
1100 | u32 num_of_logs; | |
1101 | u32 valid_logs; | |
1102 | }; | |
1103 | ||
1104 | enum resource_id_enum { | |
1105 | RESOURCE_NUM_SB_E = 0, | |
1106 | RESOURCE_NUM_L2_QUEUE_E = 1, | |
1107 | RESOURCE_NUM_VPORT_E = 2, | |
1108 | RESOURCE_NUM_VMQ_E = 3, | |
1109 | /* Not a real resource!! it's a factor used to calculate others */ | |
1110 | RESOURCE_FACTOR_NUM_RSS_PF_E = 4, | |
1111 | /* Not a real resource!! it's a factor used to calculate others */ | |
1112 | RESOURCE_FACTOR_RSS_PER_VF_E = 5, | |
1113 | RESOURCE_NUM_RL_E = 6, | |
1114 | RESOURCE_NUM_PQ_E = 7, | |
1115 | RESOURCE_NUM_VF_E = 8, | |
1116 | RESOURCE_VFC_FILTER_E = 9, | |
1117 | RESOURCE_ILT_E = 10, | |
1118 | RESOURCE_CQS_E = 11, | |
1119 | RESOURCE_GFT_PROFILES_E = 12, | |
1120 | RESOURCE_NUM_TC_E = 13, | |
1121 | RESOURCE_NUM_RSS_ENGINES_E = 14, | |
1122 | RESOURCE_LL2_QUEUE_E = 15, | |
1123 | RESOURCE_RDMA_STATS_QUEUE_E = 16, | |
11fdf7f2 | 1124 | RESOURCE_BDQ_E = 17, |
7c673cae FG |
1125 | RESOURCE_MAX_NUM, |
1126 | RESOURCE_NUM_INVALID = 0xFFFFFFFF | |
1127 | }; | |
1128 | ||
1129 | /* Resource ID is to be filled by the driver in the MB request | |
1130 | * Size, offset & flags to be filled by the MFW in the MB response | |
1131 | */ | |
1132 | struct resource_info { | |
1133 | enum resource_id_enum res_id; | |
1134 | u32 size; /* number of allocated resources */ | |
1135 | u32 offset; /* Offset of the 1st resource */ | |
1136 | u32 vf_size; | |
1137 | u32 vf_offset; | |
1138 | u32 flags; | |
1139 | #define RESOURCE_ELEMENT_STRICT (1 << 0) | |
1140 | }; | |
1141 | ||
11fdf7f2 TL |
1142 | #define DRV_ROLE_NONE 0 |
1143 | #define DRV_ROLE_PREBOOT 1 | |
1144 | #define DRV_ROLE_OS 2 | |
1145 | #define DRV_ROLE_KDUMP 3 | |
1146 | ||
1147 | struct load_req_stc { | |
1148 | u32 drv_ver_0; | |
1149 | u32 drv_ver_1; | |
1150 | u32 fw_ver; | |
1151 | u32 misc0; | |
1152 | #define LOAD_REQ_ROLE_MASK 0x000000FF | |
9f95a23c | 1153 | #define LOAD_REQ_ROLE_OFFSET 0 |
11fdf7f2 | 1154 | #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 |
9f95a23c | 1155 | #define LOAD_REQ_LOCK_TO_OFFSET 8 |
11fdf7f2 TL |
1156 | #define LOAD_REQ_LOCK_TO_DEFAULT 0 |
1157 | #define LOAD_REQ_LOCK_TO_NONE 255 | |
1158 | #define LOAD_REQ_FORCE_MASK 0x000F0000 | |
9f95a23c | 1159 | #define LOAD_REQ_FORCE_OFFSET 16 |
11fdf7f2 TL |
1160 | #define LOAD_REQ_FORCE_NONE 0 |
1161 | #define LOAD_REQ_FORCE_PF 1 | |
1162 | #define LOAD_REQ_FORCE_ALL 2 | |
1163 | #define LOAD_REQ_FLAGS0_MASK 0x00F00000 | |
9f95a23c | 1164 | #define LOAD_REQ_FLAGS0_OFFSET 20 |
11fdf7f2 TL |
1165 | #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) |
1166 | }; | |
1167 | ||
1168 | struct load_rsp_stc { | |
1169 | u32 drv_ver_0; | |
1170 | u32 drv_ver_1; | |
1171 | u32 fw_ver; | |
1172 | u32 misc0; | |
1173 | #define LOAD_RSP_ROLE_MASK 0x000000FF | |
9f95a23c | 1174 | #define LOAD_RSP_ROLE_OFFSET 0 |
11fdf7f2 | 1175 | #define LOAD_RSP_HSI_MASK 0x0000FF00 |
9f95a23c | 1176 | #define LOAD_RSP_HSI_OFFSET 8 |
11fdf7f2 | 1177 | #define LOAD_RSP_FLAGS0_MASK 0x000F0000 |
9f95a23c | 1178 | #define LOAD_RSP_FLAGS0_OFFSET 16 |
11fdf7f2 TL |
1179 | #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) |
1180 | }; | |
1181 | ||
9f95a23c TL |
1182 | struct mdump_retain_data_stc { |
1183 | u32 valid; | |
1184 | u32 epoch; | |
1185 | u32 pf; | |
1186 | u32 status; | |
1187 | }; | |
1188 | ||
1189 | struct attribute_cmd_write_stc { | |
1190 | u32 val; | |
1191 | u32 mask; | |
1192 | u32 offset; | |
1193 | }; | |
1194 | ||
7c673cae | 1195 | union drv_union_data { |
7c673cae FG |
1196 | struct mcp_mac wol_mac; /* UNLOAD_DONE */ |
1197 | ||
1198 | /* This configuration should be set by the driver for the LINK_SET command. */ | |
1199 | ||
1200 | struct eth_phy_cfg drv_phy_cfg; | |
1201 | ||
1202 | struct mcp_val64 val64; /* For PHY / AVS commands */ | |
1203 | ||
1204 | u8 raw_data[MCP_DRV_NVM_BUF_LEN]; | |
1205 | ||
1206 | struct mcp_file_att file_att; | |
1207 | ||
1208 | u32 ack_vf_disabled[VF_MAX_STATIC / 32]; | |
1209 | ||
1210 | struct drv_version_stc drv_version; | |
1211 | ||
1212 | struct lan_stats_stc lan_stats; | |
1213 | struct fcoe_stats_stc fcoe_stats; | |
11fdf7f2 | 1214 | struct iscsi_stats_stc iscsi_stats; |
7c673cae FG |
1215 | struct rdma_stats_stc rdma_stats; |
1216 | struct ocbb_data_stc ocbb_info; | |
1217 | struct temperature_status_stc temp_info; | |
1218 | struct resource_info resource; | |
1219 | struct bist_nvm_image_att nvm_image_att; | |
1220 | struct mdump_config_stc mdump_config; | |
11fdf7f2 TL |
1221 | u32 dword; |
1222 | ||
1223 | struct load_req_stc load_req; | |
1224 | struct load_rsp_stc load_rsp; | |
9f95a23c TL |
1225 | struct mdump_retain_data_stc mdump_retain; |
1226 | struct attribute_cmd_write_stc attribute_cmd_write; | |
7c673cae FG |
1227 | /* ... */ |
1228 | }; | |
1229 | ||
1230 | struct public_drv_mb { | |
1231 | u32 drv_mb_header; | |
1232 | #define DRV_MSG_CODE_MASK 0xffff0000 | |
1233 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
1234 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
1235 | #define DRV_MSG_CODE_INIT_HW 0x12000000 | |
11fdf7f2 | 1236 | #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 |
7c673cae FG |
1237 | #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 |
1238 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
1239 | #define DRV_MSG_CODE_INIT_PHY 0x22000000 | |
1240 | /* Params - FORCE - Reinitialize the link regardless of LFA */ | |
1241 | /* - DONT_CARE - Don't flap the link if up */ | |
1242 | #define DRV_MSG_CODE_LINK_RESET 0x23000000 | |
1243 | ||
7c673cae | 1244 | #define DRV_MSG_CODE_SET_LLDP 0x24000000 |
9f95a23c | 1245 | #define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000 |
7c673cae FG |
1246 | #define DRV_MSG_CODE_SET_DCBX 0x25000000 |
1247 | /* OneView feature driver HSI*/ | |
1248 | #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 | |
1249 | #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 | |
1250 | #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 | |
1251 | #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 | |
11fdf7f2 | 1252 | #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 |
7c673cae FG |
1253 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 |
1254 | #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 | |
1255 | #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 | |
7c673cae FG |
1256 | /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, |
1257 | * data: struct resource_info | |
1258 | */ | |
1259 | #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 | |
11fdf7f2 | 1260 | #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 |
9f95a23c TL |
1261 | #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 |
1262 | #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 | |
1263 | #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 | |
1264 | #define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000 | |
1265 | #define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000 | |
1266 | #define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000 | |
1267 | #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000 | |
1268 | #define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000 | |
1269 | #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000 | |
1270 | /* params [31:8] - reserved, [7:0] - bitmap */ | |
1271 | #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 | |
7c673cae FG |
1272 | |
1273 | /*deprecated don't use*/ | |
1274 | #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 | |
1275 | #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 | |
1276 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 | |
1277 | #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 | |
9f95a23c | 1278 | #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 |
7c673cae FG |
1279 | /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ |
1280 | #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 | |
1281 | /* Param should be set to the transaction size (up to 64 bytes) */ | |
1282 | #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 | |
1283 | /* MFW will place the file offset and len in file_att struct */ | |
1284 | #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 | |
9f95a23c TL |
1285 | /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] - |
1286 | * ??? Len in Bytes | |
7c673cae FG |
1287 | */ |
1288 | #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 | |
9f95a23c TL |
1289 | /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] |
1290 | * ??? Len in Bytes. In case this address is in the range of secured file in | |
7c673cae FG |
1291 | * secured mode, the operation will fail |
1292 | */ | |
1293 | #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 | |
1294 | /* Delete a file from nvram. Param is image_type. */ | |
1295 | #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 | |
1296 | /* Reset MCP when no NVM operation is going on, and no drivers are loaded. | |
1297 | * In case operation succeed, MCP will not ack back. | |
1298 | */ | |
1299 | #define DRV_MSG_CODE_MCP_RESET 0x00090000 | |
1300 | /* Temporary command to set secure mode, where the param is 0 (None secure) / | |
1301 | * 1 (Secure) / 2 (Full-Secure) | |
1302 | */ | |
1303 | #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 | |
1304 | /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, | |
1305 | * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, | |
1306 | * [30:31] - port | |
1307 | */ | |
1308 | #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 | |
1309 | /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, | |
1310 | * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, | |
1311 | * [30:31] - port | |
1312 | */ | |
1313 | #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 | |
1314 | /* Param: [0:15] - Address, [30:31] - port */ | |
1315 | #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 | |
1316 | /* Param: [0:15] - Address, [30:31] - port */ | |
1317 | #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 | |
1318 | /* Param: [0:3] - version, [4:15] - name (null terminated) */ | |
1319 | #define DRV_MSG_CODE_SET_VERSION 0x000f0000 | |
1320 | /* Halts the MCP. To resume MCP, user will need to use | |
1321 | * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. | |
1322 | */ | |
1323 | #define DRV_MSG_CODE_MCP_HALT 0x00100000 | |
7c673cae FG |
1324 | /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, |
1325 | * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN | |
1326 | */ | |
1327 | #define DRV_MSG_CODE_SET_VMAC 0x00110000 | |
1328 | /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, | |
1329 | * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN | |
1330 | */ | |
1331 | #define DRV_MSG_CODE_GET_VMAC 0x00120000 | |
9f95a23c | 1332 | #define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4 |
11fdf7f2 | 1333 | #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 |
7c673cae FG |
1334 | #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 |
1335 | #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 | |
1336 | #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 | |
7c673cae FG |
1337 | /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ |
1338 | #define DRV_MSG_CODE_GET_STATS 0x00130000 | |
1339 | #define DRV_MSG_CODE_STATS_TYPE_LAN 1 | |
1340 | #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 | |
1341 | #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 | |
11fdf7f2 TL |
1342 | #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 |
1343 | /* Host shall provide buffer and size for MFW */ | |
1344 | #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 | |
1345 | /* Host shall provide buffer and size for MFW */ | |
1346 | #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 | |
1347 | /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, | |
1348 | * [16:31] - offset | |
1349 | */ | |
1350 | #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 | |
1351 | /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, | |
1352 | * [16:31] - offset | |
1353 | */ | |
1354 | #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 | |
7c673cae FG |
1355 | /* indicate OCBB related information */ |
1356 | #define DRV_MSG_CODE_OCBB_DATA 0x00180000 | |
7c673cae FG |
1357 | /* Set function BW, params[15:8] - min, params[7:0] - max */ |
1358 | #define DRV_MSG_CODE_SET_BW 0x00190000 | |
1359 | #define BW_MAX_MASK 0x000000ff | |
9f95a23c | 1360 | #define BW_MAX_OFFSET 0 |
7c673cae | 1361 | #define BW_MIN_MASK 0x0000ff00 |
9f95a23c | 1362 | #define BW_MIN_OFFSET 8 |
7c673cae FG |
1363 | |
1364 | /* When param is set to 1, all parities will be masked(disabled). When params | |
1365 | * are set to 0, parities will be unmasked again. | |
1366 | */ | |
1367 | #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 | |
1368 | /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ | |
1369 | #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 | |
1370 | #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) | |
1371 | #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) | |
7c673cae FG |
1372 | /* Param: [0:15] - gpio number */ |
1373 | #define DRV_MSG_CODE_GPIO_READ 0x001c0000 | |
1374 | /* Param: [0:15] - gpio number, [16:31] - gpio value */ | |
1375 | #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 | |
7c673cae FG |
1376 | /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ |
1377 | #define DRV_MSG_CODE_BIST_TEST 0x001e0000 | |
1378 | #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 | |
1379 | ||
1380 | /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ | |
1381 | #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 | |
1382 | /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - | |
1383 | * driver version (MAJ MIN BUILD SUB) | |
1384 | */ | |
1385 | #define DRV_MSG_CODE_TIMESTAMP 0x00210000 | |
1386 | /* This is an empty mailbox just return OK*/ | |
1387 | #define DRV_MSG_CODE_EMPTY_MB 0x00220000 | |
11fdf7f2 | 1388 | |
7c673cae FG |
1389 | /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, |
1390 | * param[15:8] - age | |
1391 | */ | |
1392 | #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 | |
1393 | ||
11fdf7f2 | 1394 | #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F |
9f95a23c | 1395 | #define RESOURCE_CMD_REQ_RESC_OFFSET 0 |
11fdf7f2 | 1396 | #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 |
9f95a23c | 1397 | #define RESOURCE_CMD_REQ_OPCODE_OFFSET 5 |
7c673cae FG |
1398 | /* request resource ownership with default aging */ |
1399 | #define RESOURCE_OPCODE_REQ 1 | |
1400 | /* request resource ownership without aging */ | |
1401 | #define RESOURCE_OPCODE_REQ_WO_AGING 2 | |
1402 | /* request resource ownership with specific aging timer (in seconds) */ | |
1403 | #define RESOURCE_OPCODE_REQ_W_AGING 3 | |
1404 | #define RESOURCE_OPCODE_RELEASE 4 /* release resource */ | |
11fdf7f2 TL |
1405 | /* force resource release */ |
1406 | #define RESOURCE_OPCODE_FORCE_RELEASE 5 | |
1407 | #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 | |
9f95a23c | 1408 | #define RESOURCE_CMD_REQ_AGE_OFFSET 8 |
11fdf7f2 TL |
1409 | |
1410 | #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF | |
9f95a23c | 1411 | #define RESOURCE_CMD_RSP_OWNER_OFFSET 0 |
11fdf7f2 | 1412 | #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 |
9f95a23c | 1413 | #define RESOURCE_CMD_RSP_OPCODE_OFFSET 8 |
7c673cae FG |
1414 | /* resource is free and granted to requester */ |
1415 | #define RESOURCE_OPCODE_GNT 1 | |
1416 | /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, | |
1417 | * 16 = MFW, 17 = diag over serial | |
1418 | */ | |
1419 | #define RESOURCE_OPCODE_BUSY 2 | |
1420 | /* indicate release request was acknowledged */ | |
1421 | #define RESOURCE_OPCODE_RELEASED 3 | |
1422 | /* indicate release request was previously received by other owner */ | |
1423 | #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 | |
1424 | /* indicate wrong owner during release */ | |
1425 | #define RESOURCE_OPCODE_WRONG_OWNER 5 | |
1426 | #define RESOURCE_OPCODE_UNKNOWN_CMD 255 | |
11fdf7f2 | 1427 | |
7c673cae | 1428 | /* dedicate resource 0 for dump */ |
11fdf7f2 | 1429 | #define RESOURCE_DUMP 0 |
7c673cae FG |
1430 | |
1431 | #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ | |
7c673cae FG |
1432 | /* Send crash dump commands with param[3:0] - opcode */ |
1433 | #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 | |
1434 | #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f | |
1435 | /* acknowledge reception of error indication */ | |
1436 | #define DRV_MSG_CODE_MDUMP_ACK 0x01 | |
1437 | /* set epoc and personality as follow: drv_data[3:0] - epoch, | |
1438 | * drv_data[7:4] - personality | |
1439 | */ | |
1440 | #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 | |
1441 | /* trigger crash dump procedure */ | |
1442 | #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 | |
1443 | /* Request valid logs and config words */ | |
1444 | #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 | |
11fdf7f2 TL |
1445 | /* Set triggers mask. drv_mb_param should indicate (bitwise) which |
1446 | * trigger enabled | |
7c673cae FG |
1447 | */ |
1448 | #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 | |
11fdf7f2 TL |
1449 | /* Clear all logs */ |
1450 | #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 | |
9f95a23c TL |
1451 | #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */ |
1452 | #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */ | |
7c673cae | 1453 | #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ |
11fdf7f2 TL |
1454 | /* Param: [0:15] - gpio number */ |
1455 | #define DRV_MSG_CODE_GPIO_INFO 0x00270000 | |
1456 | /* Value will be placed in union */ | |
1457 | #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 | |
1458 | /* Value should be placed in union */ | |
1459 | #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 | |
9f95a23c | 1460 | #define DRV_MB_PARAM_ADDR_OFFSET 0 |
11fdf7f2 | 1461 | #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF |
9f95a23c | 1462 | #define DRV_MB_PARAM_DEVAD_OFFSET 16 |
11fdf7f2 | 1463 | #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 |
9f95a23c | 1464 | #define DRV_MB_PARAM_PORT_OFFSET 21 |
11fdf7f2 TL |
1465 | #define DRV_MB_PARAM_PORT_MASK 0x00600000 |
1466 | #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 | |
7c673cae | 1467 | |
9f95a23c TL |
1468 | #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ |
1469 | /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ | |
1470 | #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 | |
1471 | /* return FW_MB_PARAM_FEATURE_SUPPORT_* */ | |
1472 | #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 | |
1473 | #define DRV_MSG_CODE_READ_WOL_REG 0X00320000 | |
1474 | #define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 | |
1475 | #define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 | |
1476 | /* Param: [0:23] Attribute key, [24:31] Attribute sub command */ | |
1477 | #define DRV_MSG_CODE_ATTRIBUTE 0x00350000 | |
1478 | ||
1479 | /* Param: Password len. Union: Plain Password */ | |
1480 | #define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 | |
1481 | #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */ | |
1482 | ||
7c673cae FG |
1483 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff |
1484 | ||
1485 | u32 drv_mb_param; | |
1486 | /* UNLOAD_REQ params */ | |
1487 | #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 | |
1488 | #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 | |
1489 | #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 | |
1490 | #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 | |
1491 | ||
1492 | /* UNLOAD_DONE_params */ | |
1493 | #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 | |
1494 | ||
1495 | /* INIT_PHY params */ | |
1496 | #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 | |
1497 | #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 | |
1498 | ||
1499 | /* LLDP / DCBX params*/ | |
9f95a23c | 1500 | /* To be used with SET_LLDP command */ |
7c673cae | 1501 | #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 |
9f95a23c TL |
1502 | #define DRV_MB_PARAM_LLDP_SEND_OFFSET 0 |
1503 | /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */ | |
7c673cae | 1504 | #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 |
9f95a23c TL |
1505 | #define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1 |
1506 | /* To be used with REGISTER_LLDP_TLVS_RX command */ | |
1507 | #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 | |
1508 | #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0 | |
1509 | #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 | |
1510 | #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4 | |
1511 | /* To be used with SET_DCBX command */ | |
7c673cae | 1512 | #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 |
9f95a23c | 1513 | #define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3 |
7c673cae FG |
1514 | |
1515 | #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF | |
9f95a23c | 1516 | #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0 |
7c673cae FG |
1517 | |
1518 | #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 | |
1519 | #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 | |
1520 | ||
9f95a23c | 1521 | #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 |
7c673cae | 1522 | #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF |
9f95a23c | 1523 | #define DRV_MB_PARAM_NVM_LEN_OFFSET 24 |
7c673cae FG |
1524 | #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 |
1525 | ||
9f95a23c | 1526 | #define DRV_MB_PARAM_PHY_ADDR_OFFSET 0 |
7c673cae | 1527 | #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF |
9f95a23c | 1528 | #define DRV_MB_PARAM_PHY_LANE_OFFSET 16 |
7c673cae | 1529 | #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 |
9f95a23c | 1530 | #define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29 |
7c673cae | 1531 | #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 |
9f95a23c | 1532 | #define DRV_MB_PARAM_PHY_PORT_OFFSET 30 |
7c673cae FG |
1533 | #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 |
1534 | ||
9f95a23c | 1535 | #define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0 |
7c673cae | 1536 | #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF |
9f95a23c | 1537 | #define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8 |
7c673cae | 1538 | #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 |
9f95a23c TL |
1539 | /* configure vf MSIX params BB */ |
1540 | #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0 | |
7c673cae | 1541 | #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF |
9f95a23c | 1542 | #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8 |
7c673cae | 1543 | #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 |
9f95a23c TL |
1544 | /* configure vf MSIX for PF params AH*/ |
1545 | #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0 | |
1546 | #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF | |
7c673cae FG |
1547 | |
1548 | /* OneView configuration parametres */ | |
9f95a23c | 1549 | #define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0 |
7c673cae FG |
1550 | #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F |
1551 | #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 | |
1552 | #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 | |
1553 | #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 | |
1554 | #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 | |
1555 | #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 | |
1556 | #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 | |
1557 | #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 | |
1558 | #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 | |
1559 | ||
9f95a23c | 1560 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0 |
7c673cae FG |
1561 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF |
1562 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) | |
1563 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) | |
1564 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) | |
1565 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) | |
1566 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) | |
1567 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) | |
1568 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) | |
1569 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) | |
1570 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) | |
1571 | #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 | |
1572 | ||
9f95a23c | 1573 | #define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0 |
7c673cae FG |
1574 | #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF |
1575 | ||
9f95a23c | 1576 | #define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0 |
7c673cae FG |
1577 | #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF |
1578 | #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 | |
1579 | #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 | |
1580 | #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 | |
1581 | #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF | |
1582 | ||
9f95a23c | 1583 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0 |
7c673cae FG |
1584 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF |
1585 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 | |
1586 | /* Not Installed*/ | |
1587 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 | |
1588 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 | |
1589 | /* installed but disabled by user/admin/OS */ | |
1590 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 | |
1591 | /* installed and active */ | |
1592 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 | |
1593 | ||
9f95a23c | 1594 | #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0 |
7c673cae FG |
1595 | #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF |
1596 | ||
9f95a23c TL |
1597 | #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ |
1598 | DRV_MB_PARAM_ESWITCH_MODE_VEB | \ | |
1599 | DRV_MB_PARAM_ESWITCH_MODE_VEPA) | |
1600 | #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 | |
1601 | #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 | |
1602 | #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 | |
1603 | ||
1604 | #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1 | |
1605 | #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0 | |
1606 | ||
7c673cae FG |
1607 | #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 |
1608 | #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 | |
1609 | #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 | |
1610 | ||
9f95a23c | 1611 | #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 |
7c673cae | 1612 | #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 |
9f95a23c | 1613 | #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 |
7c673cae | 1614 | #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC |
9f95a23c | 1615 | #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 |
7c673cae | 1616 | #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 |
9f95a23c | 1617 | #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 |
7c673cae FG |
1618 | #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 |
1619 | ||
9f95a23c | 1620 | #define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0 |
7c673cae | 1621 | #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF |
9f95a23c | 1622 | #define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16 |
7c673cae | 1623 | #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 |
9f95a23c | 1624 | #define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16 |
7c673cae | 1625 | #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 |
9f95a23c | 1626 | #define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24 |
7c673cae FG |
1627 | #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 |
1628 | ||
1629 | /* Resource Allocation params - Driver version support*/ | |
1630 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 | |
9f95a23c | 1631 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 |
7c673cae | 1632 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF |
9f95a23c | 1633 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 |
7c673cae FG |
1634 | |
1635 | #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 | |
1636 | #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 | |
1637 | #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 | |
1638 | #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 | |
1639 | #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 | |
1640 | ||
1641 | #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 | |
1642 | #define DRV_MB_PARAM_BIST_RC_PASSED 1 | |
1643 | #define DRV_MB_PARAM_BIST_RC_FAILED 2 | |
1644 | #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 | |
1645 | ||
9f95a23c | 1646 | #define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0 |
7c673cae | 1647 | #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF |
9f95a23c | 1648 | #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8 |
7c673cae FG |
1649 | #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 |
1650 | ||
9f95a23c TL |
1651 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF |
1652 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 | |
1653 | /* driver supports SmartLinQ parameter */ | |
1654 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 | |
1655 | /* driver supports EEE parameter */ | |
1656 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 | |
1657 | #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 | |
1658 | #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16 | |
1659 | /* driver supports virtual link parameter */ | |
1660 | #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 | |
1661 | /* Driver attributes params */ | |
1662 | #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 | |
1663 | #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF | |
1664 | #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 | |
1665 | #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 | |
1666 | ||
7c673cae FG |
1667 | u32 fw_mb_header; |
1668 | #define FW_MSG_CODE_MASK 0xffff0000 | |
11fdf7f2 | 1669 | #define FW_MSG_CODE_UNSUPPORTED 0x00000000 |
7c673cae FG |
1670 | #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 |
1671 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
1672 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
1673 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 | |
11fdf7f2 | 1674 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 |
7c673cae | 1675 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 |
11fdf7f2 TL |
1676 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 |
1677 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 | |
1678 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 | |
7c673cae FG |
1679 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 |
1680 | #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 | |
1681 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 | |
1682 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 | |
1683 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
1684 | #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 | |
1685 | #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 | |
1686 | #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 | |
1687 | #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 | |
1688 | #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 | |
9f95a23c | 1689 | #define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000 |
7c673cae FG |
1690 | #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 |
1691 | #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 | |
1692 | #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 | |
1693 | #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 | |
1694 | #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 | |
1695 | #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 | |
1696 | #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 | |
1697 | #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 | |
1698 | #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 | |
1699 | #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 | |
1700 | #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 | |
1701 | #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 | |
9f95a23c TL |
1702 | #define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000 |
1703 | ||
7c673cae FG |
1704 | #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 |
1705 | #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 | |
1706 | #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 | |
1707 | #define FW_MSG_CODE_FLR_ACK 0x02000000 | |
1708 | #define FW_MSG_CODE_FLR_NACK 0x02100000 | |
1709 | #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 | |
1710 | #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 | |
1711 | #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 | |
1712 | ||
1713 | #define FW_MSG_CODE_NVM_OK 0x00010000 | |
1714 | #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 | |
1715 | #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 | |
1716 | #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 | |
1717 | #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 | |
1718 | #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 | |
1719 | #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 | |
1720 | #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 | |
1721 | #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 | |
1722 | #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 | |
1723 | #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 | |
1724 | #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 | |
1725 | #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 | |
1726 | #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 | |
1727 | #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 | |
1728 | #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 | |
1729 | #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 | |
1730 | #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 | |
1731 | #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 | |
1732 | /* MFW reject "mcp reset" command if one of the drivers is up */ | |
1733 | #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 | |
11fdf7f2 TL |
1734 | #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000 |
1735 | #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000 | |
1736 | #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000 | |
1737 | ||
7c673cae FG |
1738 | #define FW_MSG_CODE_PHY_OK 0x00110000 |
1739 | #define FW_MSG_CODE_PHY_ERROR 0x00120000 | |
1740 | #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 | |
1741 | #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 | |
1742 | #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 | |
1743 | #define FW_MSG_CODE_OK 0x00160000 | |
9f95a23c | 1744 | #define FW_MSG_CODE_ERROR 0x00170000 |
7c673cae | 1745 | #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 |
11fdf7f2 TL |
1746 | #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 |
1747 | #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 | |
7c673cae FG |
1748 | #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 |
1749 | #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 | |
1750 | #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 | |
1751 | #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 | |
1752 | #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 | |
11fdf7f2 TL |
1753 | #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 |
1754 | #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 | |
7c673cae | 1755 | #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 |
11fdf7f2 TL |
1756 | #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 |
1757 | #define FW_MSG_CODE_GPIO_OK 0x00160000 | |
1758 | #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 | |
7c673cae FG |
1759 | #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 |
1760 | #define FW_MSG_CODE_GPIO_INVALID 0x000f0000 | |
11fdf7f2 | 1761 | #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 |
7c673cae | 1762 | #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 |
11fdf7f2 TL |
1763 | #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 |
1764 | #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 | |
1765 | #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 | |
1766 | #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 | |
1767 | #define FW_MSG_CODE_RECOVERY_MODE 0x00740000 | |
7c673cae | 1768 | |
11fdf7f2 | 1769 | /* mdump related response codes */ |
7c673cae FG |
1770 | #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 |
1771 | #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 | |
1772 | #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 | |
1773 | #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 | |
1774 | #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 | |
1775 | ||
9f95a23c TL |
1776 | |
1777 | #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 | |
1778 | #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 | |
1779 | ||
1780 | #define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 | |
1781 | #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 | |
1782 | #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 | |
1783 | #define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 | |
1784 | #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 | |
1785 | ||
7c673cae FG |
1786 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff |
1787 | ||
9f95a23c TL |
1788 | #define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 |
1789 | #define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 | |
7c673cae FG |
1790 | |
1791 | u32 fw_mb_param; | |
11fdf7f2 | 1792 | /* Resource Allocation params - MFW version support */ |
7c673cae | 1793 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 |
9f95a23c | 1794 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 |
7c673cae | 1795 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF |
9f95a23c TL |
1796 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 |
1797 | ||
1798 | /* get MFW feature support response */ | |
1799 | /* MFW supports SmartLinQ */ | |
1800 | #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 | |
1801 | /* MFW supports EEE */ | |
1802 | #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 | |
1803 | /* MFW supports DRV_LOAD Timeout */ | |
1804 | #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 | |
1805 | /* MFW support complete IGU cleanup upon FLR */ | |
1806 | #define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP 0x00000080 | |
1807 | /* MFW supports virtual link */ | |
1808 | #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 | |
1809 | ||
1810 | #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) | |
1811 | ||
1812 | #define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF | |
1813 | #define FW_MB_PARAM_OEM_UPDATE_OFFSET 0 | |
1814 | #define FW_MB_PARAM_OEM_UPDATE_BW 0x01 | |
1815 | #define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02 | |
1816 | #define FW_MB_PARAM_OEM_UPDATE_CFG 0x04 | |
1817 | ||
1818 | #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001 | |
1819 | #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0 | |
1820 | #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002 | |
1821 | #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1 | |
1822 | #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004 | |
1823 | #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET 2 | |
1824 | #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008 | |
1825 | #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET 3 | |
1826 | ||
1827 | #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF | |
1828 | #define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0 | |
7c673cae FG |
1829 | |
1830 | u32 drv_pulse_mb; | |
1831 | #define DRV_PULSE_SEQ_MASK 0x00007fff | |
1832 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
1833 | /* | |
1834 | * The system time is in the format of | |
1835 | * (year-2001)*12*32 + month*32 + day. | |
1836 | */ | |
1837 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
1838 | /* | |
1839 | * Indicate to the firmware not to go into the | |
1840 | * OS-absent when it is not getting driver pulse. | |
1841 | * This is used for debugging as well for PXE(MBA). | |
1842 | */ | |
1843 | ||
1844 | u32 mcp_pulse_mb; | |
1845 | #define MCP_PULSE_SEQ_MASK 0x00007fff | |
1846 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
1847 | /* Indicates to the driver not to assert due to lack | |
1848 | * of MCP response | |
1849 | */ | |
1850 | #define MCP_EVENT_MASK 0xffff0000 | |
1851 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
1852 | ||
1853 | /* The union data is used by the driver to pass parameters to the scratchpad. */ | |
1854 | ||
1855 | union drv_union_data union_data; | |
1856 | ||
1857 | }; | |
1858 | ||
1859 | /* MFW - DRV MB */ | |
1860 | /********************************************************************** | |
1861 | * Description | |
1862 | * Incremental Aggregative | |
1863 | * 8-bit MFW counter per message | |
1864 | * 8-bit ack-counter per message | |
1865 | * Capabilities | |
1866 | * Provides up to 256 aggregative message per type | |
1867 | * Provides 4 message types in dword | |
1868 | * Message type pointers to byte offset | |
1869 | * Backward Compatibility by using sizeof for the counters. | |
1870 | * No lock requires for 32bit messages | |
1871 | * Limitations: | |
1872 | * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) | |
1873 | * is required to prevent data corruption. | |
1874 | **********************************************************************/ | |
1875 | enum MFW_DRV_MSG_TYPE { | |
1876 | MFW_DRV_MSG_LINK_CHANGE, | |
1877 | MFW_DRV_MSG_FLR_FW_ACK_FAILED, | |
1878 | MFW_DRV_MSG_VF_DISABLED, | |
1879 | MFW_DRV_MSG_LLDP_DATA_UPDATED, | |
1880 | MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, | |
1881 | MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, | |
1882 | MFW_DRV_MSG_ERROR_RECOVERY, | |
1883 | MFW_DRV_MSG_BW_UPDATE, | |
1884 | MFW_DRV_MSG_S_TAG_UPDATE, | |
1885 | MFW_DRV_MSG_GET_LAN_STATS, | |
1886 | MFW_DRV_MSG_GET_FCOE_STATS, | |
1887 | MFW_DRV_MSG_GET_ISCSI_STATS, | |
1888 | MFW_DRV_MSG_GET_RDMA_STATS, | |
1889 | MFW_DRV_MSG_FAILURE_DETECTED, | |
1890 | MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, | |
1891 | MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, | |
11fdf7f2 | 1892 | MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, |
9f95a23c TL |
1893 | MFW_DRV_MSG_GET_TLV_REQ, |
1894 | MFW_DRV_MSG_OEM_CFG_UPDATE, | |
1895 | MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, | |
7c673cae FG |
1896 | MFW_DRV_MSG_MAX |
1897 | }; | |
1898 | ||
1899 | #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) | |
1900 | #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) | |
1901 | #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) | |
1902 | #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) | |
1903 | ||
1904 | #ifdef BIG_ENDIAN /* Like MFW */ | |
1905 | #define DRV_ACK_MSG(msg_p, msg_id) \ | |
1906 | ((u8)((u8 *)msg_p)[msg_id]++;) | |
1907 | #else | |
1908 | #define DRV_ACK_MSG(msg_p, msg_id) \ | |
1909 | ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;) | |
1910 | #endif | |
1911 | ||
1912 | #define MFW_DRV_UPDATE(shmem_func, msg_id) \ | |
1913 | ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;) | |
1914 | ||
1915 | struct public_mfw_mb { | |
1916 | u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ | |
1917 | /* Incremented by the MFW */ | |
1918 | u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; | |
1919 | /* Incremented by the driver */ | |
1920 | u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; | |
1921 | }; | |
1922 | ||
1923 | /**************************************/ | |
1924 | /* */ | |
1925 | /* P U B L I C D A T A */ | |
1926 | /* */ | |
1927 | /**************************************/ | |
1928 | enum public_sections { | |
1929 | PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ | |
1930 | PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ | |
1931 | PUBLIC_GLOBAL, | |
1932 | PUBLIC_PATH, | |
1933 | PUBLIC_PORT, | |
1934 | PUBLIC_FUNC, | |
1935 | PUBLIC_MAX_SECTIONS | |
1936 | }; | |
1937 | ||
1938 | struct drv_ver_info_stc { | |
1939 | u32 ver; | |
1940 | u8 name[32]; | |
1941 | }; | |
1942 | ||
1943 | /* Runtime data needs about 1/2K. We use 2K to be on the safe side. | |
1944 | * Please make sure data does not exceed this size. | |
1945 | */ | |
1946 | #define NUM_RUNTIME_DWORDS 16 | |
1947 | struct drv_init_hw_stc { | |
1948 | u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; | |
1949 | u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; | |
1950 | }; | |
1951 | ||
1952 | struct mcp_public_data { | |
1953 | /* The sections fields is an array */ | |
1954 | u32 num_sections; | |
1955 | offsize_t sections[PUBLIC_MAX_SECTIONS]; | |
1956 | struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; | |
1957 | struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; | |
1958 | struct public_global global; | |
1959 | struct public_path path[MCP_GLOB_PATH_MAX]; | |
1960 | struct public_port port[MCP_GLOB_PORT_MAX]; | |
1961 | struct public_func func[MCP_GLOB_FUNC_MAX]; | |
1962 | }; | |
1963 | ||
1964 | #define I2C_TRANSCEIVER_ADDR 0xa0 | |
1965 | #define MAX_I2C_TRANSACTION_SIZE 16 | |
1966 | #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 | |
1967 | ||
1968 | #endif /* MCP_PUBLIC_H */ |