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1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * | |
3 | * Copyright (c) 2012-2018 Solarflare Communications Inc. | |
4 | * All rights reserved. | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This is NOT the original source file. Do NOT edit it. | |
9 | * To update the tlv layout, please edit the copy in | |
10 | * the sfregistry repo and then, in that repo, | |
11 | * "make tlv_headers" or "make export" to | |
12 | * regenerate and export all types of headers. | |
13 | */ | |
11fdf7f2 TL |
14 | |
15 | /* These structures define the layouts for the TLV items stored in static and | |
16 | * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). | |
17 | * | |
18 | * They contain the same sort of information that was kept in the | |
19 | * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures | |
20 | * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for | |
21 | * Siena. | |
22 | * | |
23 | * These are used directly by the MC and should also be usable directly on host | |
24 | * systems which are little-endian and do not do strange things with structure | |
25 | * padding. (Big-endian host systems will require some byte-swapping.) | |
26 | * | |
27 | * ----- | |
28 | * | |
29 | * Please refer to SF-108797-SW for a general overview of the TLV partition | |
30 | * format. | |
31 | * | |
32 | * ----- | |
33 | * | |
34 | * The current tag IDs have a general structure: with the exception of the | |
35 | * special values defined in the document, they are of the form 0xLTTTNNNN, | |
36 | * where: | |
37 | * | |
38 | * - L is a location, indicating where this tag is expected to be found: | |
39 | * 0: static configuration | |
40 | * 1: dynamic configuration | |
41 | * 2: firmware internal use | |
42 | * 3: license partition | |
9f95a23c | 43 | * 4: tsa configuration |
11fdf7f2 TL |
44 | * |
45 | * - TTT is a type, which is just a unique value. The same type value | |
46 | * might appear in both locations, indicating a relationship between | |
47 | * the items (e.g. static and dynamic VPD below). | |
48 | * | |
49 | * - NNNN is an index of some form. Some item types are per-port, some | |
50 | * are per-PF, some are per-partition-type. | |
51 | * | |
52 | * ----- | |
53 | * | |
54 | * As with the previous Siena structures, each structure here is laid out | |
55 | * carefully: values are aligned to their natural boundary, with explicit | |
56 | * padding fields added where necessary. (No, technically this does not | |
57 | * absolutely guarantee portability. But, in practice, compilers are generally | |
58 | * sensible enough not to introduce completely pointless padding, and it works | |
59 | * well enough.) | |
60 | */ | |
61 | ||
62 | ||
63 | #ifndef CI_MGMT_TLV_LAYOUT_H | |
64 | #define CI_MGMT_TLV_LAYOUT_H | |
65 | ||
66 | ||
67 | /* ---------------------------------------------------------------------------- | |
68 | * General structure (defined by SF-108797-SW) | |
69 | * ---------------------------------------------------------------------------- | |
70 | */ | |
71 | ||
72 | ||
73 | /* The "end" tag. | |
74 | * | |
75 | * (Note that this is *not* followed by length or value fields: anything after | |
76 | * the tag itself is irrelevant.) | |
77 | */ | |
78 | ||
79 | #define TLV_TAG_END (0xEEEEEEEE) | |
80 | ||
81 | ||
82 | /* Other special reserved tag values. | |
83 | */ | |
84 | ||
85 | #define TLV_TAG_SKIP (0x00000000) | |
86 | #define TLV_TAG_INVALID (0xFFFFFFFF) | |
87 | ||
88 | ||
89 | /* TLV partition header. | |
90 | * | |
91 | * In a TLV partition, this must be the first item in the sequence, at offset | |
92 | * 0. | |
93 | */ | |
94 | ||
95 | #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A) | |
96 | ||
97 | struct tlv_partition_header { | |
98 | uint32_t tag; | |
99 | uint32_t length; | |
100 | uint16_t type_id; | |
101 | /* 0 indicates the default segment (always located at offset 0), while other values | |
102 | * are for RFID-selectable presets that should immediately follow the default segment. | |
103 | * The default segment may also have preset > 0, which means that it is a preset | |
104 | * selected through an RFID command and copied by FW to the location at offset 0. */ | |
105 | uint16_t preset; | |
106 | uint32_t generation; | |
107 | uint32_t total_length; | |
108 | }; | |
109 | ||
110 | ||
111 | /* TLV partition trailer. | |
112 | * | |
113 | * In a TLV partition, this must be the last item in the sequence, immediately | |
114 | * preceding the TLV_TAG_END word. | |
115 | */ | |
116 | ||
117 | #define TLV_TAG_PARTITION_TRAILER (0xEF101A57) | |
118 | ||
119 | struct tlv_partition_trailer { | |
120 | uint32_t tag; | |
121 | uint32_t length; | |
122 | uint32_t generation; | |
123 | uint32_t checksum; | |
124 | }; | |
125 | ||
126 | ||
127 | /* Appendable TLV partition header. | |
128 | * | |
129 | * In an appendable TLV partition, this must be the first item in the sequence, | |
130 | * at offset 0. (Note that, unlike the configuration partitions, there is no | |
131 | * trailer before the TLV_TAG_END word.) | |
132 | */ | |
133 | ||
134 | #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7) | |
135 | ||
136 | struct tlv_appendable_partition_header { | |
137 | uint32_t tag; | |
138 | uint32_t length; | |
139 | uint16_t type_id; | |
140 | uint16_t reserved; | |
141 | }; | |
142 | ||
143 | ||
144 | /* ---------------------------------------------------------------------------- | |
145 | * Configuration items | |
146 | * ---------------------------------------------------------------------------- | |
147 | */ | |
148 | ||
149 | ||
150 | /* NIC global capabilities. | |
151 | */ | |
152 | ||
153 | #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000) | |
154 | ||
155 | struct tlv_global_capabilities { | |
156 | uint32_t tag; | |
157 | uint32_t length; | |
158 | uint32_t flags; | |
159 | }; | |
160 | ||
161 | ||
162 | /* Siena-style per-port MAC address allocation. | |
163 | * | |
164 | * There are <count> addresses, starting at <base_address> and incrementing | |
165 | * by adding <stride> to the low-order byte(s). | |
166 | * | |
167 | * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool | |
168 | * of contiguous MAC addresses for the firmware to allocate as it sees fit.) | |
169 | */ | |
170 | ||
171 | #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) | |
172 | ||
173 | struct tlv_port_mac { | |
174 | uint32_t tag; | |
175 | uint32_t length; | |
176 | uint8_t base_address[6]; | |
177 | uint16_t reserved; | |
178 | uint16_t count; | |
179 | uint16_t stride; | |
180 | }; | |
181 | ||
182 | ||
183 | /* Static VPD. | |
184 | * | |
185 | * This is the portion of VPD which is set at manufacturing time and not | |
186 | * expected to change. It is formatted as a standard PCI VPD block. There are | |
187 | * global and per-pf TLVs for this, the global TLV is new for Medford and is | |
188 | * used in preference to the per-pf TLV. | |
189 | */ | |
190 | ||
191 | #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) | |
192 | ||
193 | struct tlv_pf_static_vpd { | |
194 | uint32_t tag; | |
195 | uint32_t length; | |
196 | uint8_t bytes[]; | |
197 | }; | |
198 | ||
199 | #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) | |
200 | ||
201 | struct tlv_global_static_vpd { | |
202 | uint32_t tag; | |
203 | uint32_t length; | |
204 | uint8_t bytes[]; | |
205 | }; | |
206 | ||
207 | ||
208 | /* Dynamic VPD. | |
209 | * | |
210 | * This is the portion of VPD which may be changed (e.g. by firmware updates). | |
211 | * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs | |
212 | * for this, the global TLV is new for Medford and is used in preference to the | |
213 | * per-pf TLV. | |
214 | */ | |
215 | ||
216 | #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) | |
217 | ||
218 | struct tlv_pf_dynamic_vpd { | |
219 | uint32_t tag; | |
220 | uint32_t length; | |
221 | uint8_t bytes[]; | |
222 | }; | |
223 | ||
224 | #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) | |
225 | ||
226 | struct tlv_global_dynamic_vpd { | |
227 | uint32_t tag; | |
228 | uint32_t length; | |
229 | uint8_t bytes[]; | |
230 | }; | |
231 | ||
232 | ||
233 | /* "DBI" PCI config space changes. | |
234 | * | |
235 | * This is a set of edits made to the default PCI config space values before | |
236 | * the device is allowed to enumerate. There are global and per-pf TLVs for | |
237 | * this, the global TLV is new for Medford and is used in preference to the | |
238 | * per-pf TLV. | |
239 | */ | |
240 | ||
241 | #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) | |
242 | ||
243 | struct tlv_pf_dbi { | |
244 | uint32_t tag; | |
245 | uint32_t length; | |
246 | struct { | |
247 | uint16_t addr; | |
248 | uint16_t byte_enables; | |
249 | uint32_t value; | |
250 | } items[]; | |
251 | }; | |
252 | ||
253 | ||
254 | #define TLV_TAG_GLOBAL_DBI (0x00210000) | |
255 | ||
256 | struct tlv_global_dbi { | |
257 | uint32_t tag; | |
258 | uint32_t length; | |
259 | struct { | |
260 | uint16_t addr; | |
261 | uint16_t byte_enables; | |
262 | uint32_t value; | |
263 | } items[]; | |
264 | }; | |
265 | ||
266 | ||
267 | /* Partition subtype codes. | |
268 | * | |
269 | * A subtype may optionally be stored for each type of partition present in | |
270 | * the NVRAM. For example, this may be used to allow a generic firmware update | |
271 | * utility to select a specific variant of firmware for a specific variant of | |
272 | * board. | |
273 | * | |
274 | * The description[] field is an optional string which is returned in the | |
275 | * MC_CMD_NVRAM_METADATA response if present. | |
276 | */ | |
277 | ||
278 | #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) | |
279 | ||
280 | struct tlv_partition_subtype { | |
281 | uint32_t tag; | |
282 | uint32_t length; | |
283 | uint32_t subtype; | |
284 | uint8_t description[]; | |
285 | }; | |
286 | ||
287 | ||
288 | /* Partition version codes. | |
289 | * | |
290 | * A version may optionally be stored for each type of partition present in | |
291 | * the NVRAM. This provides a standard way of tracking the currently stored | |
292 | * version of each of the various component images. | |
293 | */ | |
294 | ||
295 | #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type)) | |
296 | ||
297 | struct tlv_partition_version { | |
298 | uint32_t tag; | |
299 | uint32_t length; | |
300 | uint16_t version_w; | |
301 | uint16_t version_x; | |
302 | uint16_t version_y; | |
303 | uint16_t version_z; | |
304 | }; | |
305 | ||
306 | /* Global PCIe configuration */ | |
307 | ||
308 | #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000) | |
309 | ||
310 | struct tlv_pcie_config { | |
311 | uint32_t tag; | |
312 | uint32_t length; | |
313 | int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ | |
314 | uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ | |
315 | uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ | |
316 | uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ | |
317 | #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ | |
318 | #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ | |
319 | }; | |
320 | ||
321 | /* Per-PF configuration. Note that not all these fields are necessarily useful | |
322 | * as the apertures are constrained by the BIU settings (the one case we do | |
323 | * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can | |
324 | * tidy things up later */ | |
325 | ||
326 | #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) | |
327 | ||
328 | struct tlv_per_pf_pcie_config { | |
329 | uint32_t tag; | |
330 | uint32_t length; | |
331 | uint8_t vfs_total; | |
332 | uint8_t port_allocation; | |
333 | uint16_t vectors_per_pf; | |
334 | uint16_t vectors_per_vf; | |
335 | uint8_t pf_bar0_aperture; | |
336 | uint8_t pf_bar2_aperture; | |
337 | uint8_t vf_bar0_aperture; | |
338 | uint8_t vf_base; | |
339 | uint16_t supp_pagesz; | |
340 | uint16_t msix_vec_base; | |
341 | }; | |
342 | ||
343 | ||
344 | /* Development ONLY. This is a single TLV tag for all the gubbins | |
345 | * that can be set through the MC command-line other than the PCIe | |
346 | * settings. This is a temporary measure. */ | |
347 | #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ | |
348 | #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS | |
349 | ||
350 | struct tlv_tmp_gubbins { | |
351 | uint32_t tag; | |
352 | uint32_t length; | |
353 | /* Consumed by dpcpu.c */ | |
354 | uint64_t tx0_tags; /* Bitmap */ | |
355 | uint64_t tx1_tags; /* Bitmap */ | |
356 | uint64_t dl_tags; /* Bitmap */ | |
357 | uint32_t flags; | |
358 | #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */ | |
359 | #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ | |
360 | #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ | |
361 | #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ | |
362 | #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */ | |
363 | /* Consumed by features.c */ | |
364 | uint32_t dut_features; /* All 1s -> leave alone */ | |
365 | int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */ | |
366 | /* Consumed by clocks_hunt.c */ | |
367 | int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */ | |
368 | /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */ | |
369 | int8_t rx_dc_size; /* -1 -> leave alone */ | |
370 | int8_t tx_dc_size; | |
371 | int16_t num_q_allocs; | |
372 | }; | |
373 | ||
374 | /* Global port configuration | |
375 | * | |
376 | * This is now deprecated in favour of a platform-provided default | |
377 | * and dynamic config override via tlv_global_port_options. | |
378 | */ | |
379 | #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000) | |
380 | ||
381 | struct tlv_global_port_config { | |
382 | uint32_t tag; | |
383 | uint32_t length; | |
384 | uint32_t ports_per_core; | |
385 | uint32_t max_port_speed; | |
386 | }; | |
387 | ||
388 | ||
389 | /* Firmware options. | |
390 | * | |
391 | * This is intended for user-configurable selection of optional firmware | |
392 | * features and variants. | |
393 | * | |
394 | * Initially, this consists only of the satellite CPU firmware variant | |
395 | * selection, but this tag could be extended in the future (using the | |
396 | * tag length to determine whether additional fields are present). | |
397 | */ | |
398 | ||
399 | #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000) | |
400 | ||
401 | struct tlv_firmware_options { | |
402 | uint32_t tag; | |
403 | uint32_t length; | |
404 | uint32_t firmware_variant; | |
405 | #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff) | |
406 | ||
407 | /* These are the values for overriding the driver's choice; the definitions | |
408 | * are taken from MCDI so that they don't get out of step. Include | |
409 | * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if | |
410 | * you need to use these constants. | |
411 | */ | |
412 | #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED | |
413 | #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY | |
414 | #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM | |
415 | #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE | |
416 | #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ | |
417 | MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 | |
418 | #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE | |
9f95a23c TL |
419 | #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK |
420 | #define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP | |
11fdf7f2 TL |
421 | }; |
422 | ||
423 | /* Voltage settings | |
424 | * | |
425 | * Intended for boards with A0 silicon where the core voltage may | |
426 | * need tweaking. Most likely set once when the pass voltage is | |
427 | * determined. */ | |
428 | ||
429 | #define TLV_TAG_0V9_SETTINGS (0x000c0000) | |
430 | ||
431 | struct tlv_0v9_settings { | |
432 | uint32_t tag; | |
433 | uint32_t length; | |
434 | uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ | |
435 | #define TLV_TAG_0V9_REQUIRES_FAN (1) | |
436 | uint16_t target_voltage; /* In millivolts */ | |
437 | /* Since the limits are meant to be centred to the target (and must at least | |
438 | * contain it) they need setting as well. */ | |
439 | uint16_t warn_low; /* In millivolts */ | |
440 | uint16_t warn_high; /* In millivolts */ | |
441 | uint16_t panic_low; /* In millivolts */ | |
442 | uint16_t panic_high; /* In millivolts */ | |
443 | }; | |
444 | ||
445 | ||
446 | /* Clock configuration */ | |
447 | ||
448 | #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ | |
449 | #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG | |
450 | ||
451 | struct tlv_clock_config { | |
452 | uint32_t tag; | |
453 | uint32_t length; | |
454 | uint16_t clk_sys; /* MHz */ | |
455 | uint16_t clk_dpcpu; /* MHz */ | |
456 | uint16_t clk_icore; /* MHz */ | |
457 | uint16_t clk_pcs; /* MHz */ | |
458 | }; | |
459 | ||
460 | #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000) | |
461 | ||
462 | struct tlv_clock_config_medford { | |
463 | uint32_t tag; | |
464 | uint32_t length; | |
465 | uint16_t clk_sys; /* MHz */ | |
466 | uint16_t clk_mc; /* MHz */ | |
467 | uint16_t clk_rmon; /* MHz */ | |
468 | uint16_t clk_vswitch; /* MHz */ | |
469 | uint16_t clk_dpcpu; /* MHz */ | |
470 | uint16_t clk_pcs; /* MHz */ | |
471 | }; | |
472 | ||
473 | ||
474 | /* EF10-style global pool of MAC addresses. | |
475 | * | |
476 | * There are <count> addresses, starting at <base_address>, which are | |
477 | * contiguous. Firmware is responsible for allocating addresses from this | |
478 | * pool to ports / PFs as appropriate. | |
479 | */ | |
480 | ||
481 | #define TLV_TAG_GLOBAL_MAC (0x000e0000) | |
482 | ||
483 | struct tlv_global_mac { | |
484 | uint32_t tag; | |
485 | uint32_t length; | |
486 | uint8_t base_address[6]; | |
487 | uint16_t reserved1; | |
488 | uint16_t count; | |
489 | uint16_t reserved2; | |
490 | }; | |
491 | ||
492 | #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ | |
493 | #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET | |
494 | ||
495 | /* The target value for the 0v9 power rail measured on-chip at the | |
496 | * analogue test bus */ | |
497 | struct tlv_0v9_atb_target { | |
498 | uint32_t tag; | |
499 | uint32_t length; | |
500 | uint16_t millivolts; | |
501 | uint16_t reserved; | |
502 | }; | |
503 | ||
504 | /* Factory settings for amplitude calibration of the PCIE TX serdes */ | |
505 | #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000) | |
506 | struct tlv_pcie_tx_amp_config { | |
507 | uint32_t tag; | |
508 | uint32_t length; | |
509 | uint8_t quad_tx_imp2k[4]; | |
510 | uint8_t quad_tx_imp50[4]; | |
511 | uint8_t lane_amp[16]; | |
512 | }; | |
513 | ||
514 | ||
515 | /* Global PCIe configuration, second revision. This represents the visible PFs | |
516 | * by a bitmap rather than having the number of the highest visible one. As such | |
517 | * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG | |
518 | * can and it should be used in place of that tag in future (but compatibility with | |
519 | * the old tag will be left in the firmware indefinitely). */ | |
520 | ||
521 | #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000) | |
522 | ||
523 | struct tlv_pcie_config_r2 { | |
524 | uint32_t tag; | |
525 | uint32_t length; | |
526 | uint16_t visible_pfs; /**< Bitmap of visible PFs */ | |
527 | uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ | |
528 | uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ | |
529 | uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ | |
530 | }; | |
531 | ||
532 | /* Dynamic port mode. | |
533 | * | |
534 | * Allows selecting alternate port configuration for platforms that support it | |
535 | * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the | |
536 | * number of externally visible ports (and, hence, PF to port mapping), so must | |
537 | * be done at boot time. | |
538 | * | |
9f95a23c TL |
539 | * Port mode naming convention is |
540 | * | |
541 | * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width] | |
542 | * | |
543 | * Port lane width determines the capabilities (speeds) of the ports, subject | |
544 | * to architecture capabilities (e.g. 25G support) and switch bandwidth | |
545 | * constraints: | |
546 | * - single lane ports can do 25G/10G/1G | |
547 | * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane) | |
548 | * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes) | |
549 | ||
11fdf7f2 TL |
550 | * This tag supercedes tlv_global_port_config. |
551 | */ | |
552 | ||
553 | #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000) | |
554 | ||
555 | struct tlv_global_port_mode { | |
556 | uint32_t tag; | |
557 | uint32_t length; | |
558 | uint32_t port_mode; | |
559 | #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ | |
9f95a23c TL |
560 | |
561 | /* Huntington port modes */ | |
562 | #define TLV_PORT_MODE_10G (0) | |
563 | #define TLV_PORT_MODE_40G (1) | |
564 | #define TLV_PORT_MODE_10G_10G (2) | |
565 | #define TLV_PORT_MODE_40G_40G (3) | |
566 | #define TLV_PORT_MODE_10G_10G_10G_10G (4) | |
567 | #define TLV_PORT_MODE_40G_10G_10G (6) | |
568 | #define TLV_PORT_MODE_10G_10G_40G (7) | |
569 | ||
570 | /* Medford (and later) port modes */ | |
571 | #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */ | |
572 | #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */ | |
573 | #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */ | |
574 | #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */ | |
575 | #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */ | |
576 | #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */ | |
577 | #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */ | |
578 | #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */ | |
579 | #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */ | |
580 | #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */ | |
581 | #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */ | |
582 | #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */ | |
583 | #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */ | |
584 | #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */ | |
585 | #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */ | |
586 | #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */ | |
587 | #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */ | |
588 | #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */ | |
589 | #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */ | |
590 | ||
591 | /* Snapper-only Medford2 port modes. | |
592 | * These modes are eftest only, to allow snapper explicit | |
593 | * selection between multi-channel and LLPCS. In production, | |
594 | * this selection is automatic and outside world should not | |
595 | * care about LLPCS. | |
596 | */ | |
597 | #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */ | |
598 | #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */ | |
599 | #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */ | |
600 | #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */ | |
601 | #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */ | |
602 | #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */ | |
603 | #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL | |
604 | ||
605 | /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */ | |
606 | #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) | |
607 | #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4) | |
608 | #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) | |
609 | #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9) | |
610 | ||
611 | #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL | |
11fdf7f2 TL |
612 | }; |
613 | ||
614 | /* Type of the v-switch created implicitly by the firmware */ | |
615 | ||
616 | #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port)) | |
617 | ||
618 | struct tlv_vswitch_type { | |
619 | uint32_t tag; | |
620 | uint32_t length; | |
621 | uint32_t vswitch_type; | |
622 | #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */ | |
623 | #define TLV_VSWITCH_TYPE_NONE (0) | |
624 | #define TLV_VSWITCH_TYPE_VLAN (1) | |
625 | #define TLV_VSWITCH_TYPE_VEB (2) | |
626 | #define TLV_VSWITCH_TYPE_VEPA (3) | |
627 | #define TLV_VSWITCH_TYPE_MUX (4) | |
628 | #define TLV_VSWITCH_TYPE_TEST (5) | |
629 | }; | |
630 | ||
631 | /* A VLAN tag for the v-port created implicitly by the firmware */ | |
632 | ||
633 | #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) | |
634 | ||
635 | struct tlv_vport_vlan_tag { | |
636 | uint32_t tag; | |
637 | uint32_t length; | |
638 | uint32_t vlan_tag; | |
639 | #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */ | |
640 | }; | |
641 | ||
642 | /* Offset to be applied to the 0v9 setting, wherever it came from */ | |
643 | ||
644 | #define TLV_TAG_ATB_0V9_OFFSET (0x10140000) | |
645 | ||
646 | struct tlv_0v9_atb_offset { | |
647 | uint32_t tag; | |
648 | uint32_t length; | |
649 | int16_t offset_millivolts; | |
650 | uint16_t reserved; | |
651 | }; | |
652 | ||
653 | /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port). | |
654 | * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583. | |
655 | * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while | |
656 | * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default: | |
657 | * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */ | |
658 | ||
659 | #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */ | |
660 | ||
661 | struct tlv_privilege_mask { /* legacy structure - do not use */ | |
662 | uint32_t tag; | |
663 | uint32_t length; | |
664 | uint32_t privilege_mask; | |
665 | }; | |
666 | ||
667 | #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000) | |
668 | ||
669 | struct tlv_privilege_mask_add { | |
670 | uint32_t tag; | |
671 | uint32_t length; | |
672 | uint32_t privilege_mask_add; | |
673 | }; | |
674 | ||
675 | #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000) | |
676 | ||
677 | struct tlv_privilege_mask_rem { | |
678 | uint32_t tag; | |
679 | uint32_t length; | |
680 | uint32_t privilege_mask_rem; | |
681 | }; | |
682 | ||
683 | /* Additional privileges given to all PFs. | |
684 | * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ | |
685 | ||
686 | #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000) | |
687 | ||
688 | struct tlv_privilege_mask_add_all_pfs { | |
689 | uint32_t tag; | |
690 | uint32_t length; | |
691 | uint32_t privilege_mask_add; | |
692 | }; | |
693 | ||
694 | /* Additional privileges given to a selected PF. | |
695 | * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ | |
696 | ||
697 | #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) | |
698 | ||
699 | struct tlv_privilege_mask_add_single_pf { | |
700 | uint32_t tag; | |
701 | uint32_t length; | |
702 | uint32_t privilege_mask_add; | |
703 | }; | |
704 | ||
705 | /* Turning on/off the PFIOV mode. | |
706 | * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */ | |
707 | ||
708 | #define TLV_TAG_PFIOV(port) (0x10170000 + (port)) | |
709 | ||
710 | struct tlv_pfiov { | |
711 | uint32_t tag; | |
712 | uint32_t length; | |
713 | uint32_t pfiov; | |
714 | #define TLV_PFIOV_OFF (0) /* Default */ | |
715 | #define TLV_PFIOV_ON (1) | |
716 | }; | |
717 | ||
718 | /* Multicast filter chaining mode selection. | |
719 | * | |
720 | * When enabled, multicast packets are delivered to all recipients of all | |
721 | * matching multicast filters, with the exception that IP multicast filters | |
722 | * will steal traffic from MAC multicast filters on a per-function basis. | |
723 | * (New behaviour.) | |
724 | * | |
725 | * When disabled, multicast packets will always be delivered only to the | |
726 | * recipients of the highest priority matching multicast filter. | |
727 | * (Legacy behaviour.) | |
728 | * | |
729 | * The DEFAULT mode (which is the same as the tag not being present at all) | |
730 | * is equivalent to ENABLED in production builds, and DISABLED in eftest | |
731 | * builds. | |
732 | * | |
733 | * This option is intended to provide run-time control over this feature | |
734 | * while it is being stabilised and may be withdrawn at some point in the | |
735 | * future; the new behaviour is intended to become the standard behaviour. | |
736 | */ | |
737 | ||
738 | #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000) | |
739 | ||
740 | struct tlv_mcast_filter_chaining { | |
741 | uint32_t tag; | |
742 | uint32_t length; | |
743 | uint32_t mode; | |
744 | #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff) | |
745 | #define TLV_MCAST_FILTER_CHAINING_DISABLED (0) | |
746 | #define TLV_MCAST_FILTER_CHAINING_ENABLED (1) | |
747 | }; | |
748 | ||
749 | /* Pacer rate limit per PF */ | |
750 | #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) | |
751 | ||
752 | struct tlv_rate_limit { | |
753 | uint32_t tag; | |
754 | uint32_t length; | |
755 | uint32_t rate_mbps; | |
756 | }; | |
757 | ||
758 | /* OCSD Enable/Disable | |
759 | * | |
760 | * This setting allows OCSD to be disabled. This is a requirement for HP | |
761 | * servers to support PCI passthrough for virtualization. | |
762 | * | |
763 | * The DEFAULT mode (which is the same as the tag not being present) is | |
764 | * equivalent to ENABLED. | |
765 | * | |
766 | * This option is not used by the MCFW, and is entirely handled by the various | |
767 | * drivers that support OCSD, by reading the setting before they attempt | |
768 | * to enable OCSD. | |
769 | * | |
770 | * bit0: OCSD Disabled/Enabled | |
771 | */ | |
772 | ||
773 | #define TLV_TAG_OCSD (0x101C0000) | |
774 | ||
775 | struct tlv_ocsd { | |
776 | uint32_t tag; | |
777 | uint32_t length; | |
778 | uint32_t mode; | |
779 | #define TLV_OCSD_DISABLED 0 | |
780 | #define TLV_OCSD_ENABLED 1 /* Default */ | |
781 | }; | |
782 | ||
783 | /* Descriptor cache config. | |
784 | * | |
785 | * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also | |
786 | * sets the total number of VIs. When the number of VIs is reduced VIs are taken | |
787 | * away from the highest numbered port first, so a vi_count of 1024 means 1024 | |
788 | * VIs on the first port and 0 on the second (on a Torino). | |
789 | */ | |
790 | ||
791 | #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000) | |
792 | ||
793 | struct tlv_descriptor_cache_config { | |
794 | uint32_t tag; | |
795 | uint32_t length; | |
796 | uint8_t rx_desc_cache_size; | |
797 | uint8_t tx_desc_cache_size; | |
798 | uint16_t vi_count; | |
799 | }; | |
800 | #define TLV_DESC_CACHE_DEFAULT (0xff) | |
801 | #define TLV_VI_COUNT_DEFAULT (0xffff) | |
802 | ||
803 | /* RX event merging config (read batching). | |
804 | * | |
805 | * Sets the global maximum number of events for the merging bins, and the | |
806 | * global timeout configuration for the bins. | |
807 | */ | |
808 | ||
809 | #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000) | |
810 | ||
811 | struct tlv_rx_event_merging_config { | |
812 | uint32_t tag; | |
813 | uint32_t length; | |
814 | uint32_t max_events; | |
815 | #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) | |
816 | uint32_t timeout_ns; | |
817 | }; | |
818 | #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) | |
819 | #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) | |
820 | ||
821 | #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000) | |
822 | struct tlv_pcie_link_settings { | |
823 | uint32_t tag; | |
824 | uint32_t length; | |
825 | uint16_t gen; /* Target PCIe generation: 1, 2, 3 */ | |
826 | uint16_t width; /* Number of lanes */ | |
827 | }; | |
828 | ||
829 | /* TX event merging config. | |
830 | * | |
831 | * Sets the global maximum number of events for the merging bins, and the | |
832 | * global timeout configuration for the bins, and the global timeout for | |
833 | * empty queues. | |
834 | */ | |
835 | #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000) | |
836 | struct tlv_tx_event_merging_config { | |
837 | uint32_t tag; | |
838 | uint32_t length; | |
839 | uint32_t max_events; | |
840 | #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) | |
841 | uint32_t timeout_ns; | |
842 | uint32_t qempty_timeout_ns; /* Medford only */ | |
843 | }; | |
844 | #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) | |
845 | #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) | |
846 | #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff) | |
847 | ||
848 | #define TLV_TAG_LICENSE (0x30800000) | |
849 | ||
850 | typedef struct tlv_license { | |
851 | uint32_t tag; | |
852 | uint32_t length; | |
853 | uint8_t data[]; | |
854 | } tlv_license_t; | |
855 | ||
9f95a23c | 856 | /* TSA NIC IP address configuration (DEPRECATED) |
11fdf7f2 TL |
857 | * |
858 | * Sets the TSA NIC IP address statically via configuration tool or dynamically | |
859 | * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop) | |
860 | * | |
861 | * NOTE: This TAG is temporarily placed in the dynamic config partition and will | |
862 | * be moved to a private partition during TSA development. It is not used in any | |
863 | * released code yet. | |
864 | */ | |
865 | ||
9f95a23c | 866 | #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */ |
11fdf7f2 TL |
867 | |
868 | #define TLV_TSAN_IP_MODE_STATIC (0) | |
869 | #define TLV_TSAN_IP_MODE_DHCP (1) | |
870 | #define TLV_TSAN_IP_MODE_SNOOP (2) | |
871 | typedef struct tlv_tsan_config { | |
872 | uint32_t tag; | |
873 | uint32_t length; | |
874 | uint32_t mode; | |
875 | uint32_t ip; | |
876 | uint32_t netmask; | |
877 | uint32_t gateway; | |
878 | uint32_t port; | |
879 | uint32_t bind_retry; /* DEPRECATED */ | |
880 | uint32_t bind_bkout; /* DEPRECATED */ | |
881 | } tlv_tsan_config_t; | |
882 | ||
9f95a23c | 883 | /* TSA Controller IP address configuration (DEPRECATED) |
11fdf7f2 TL |
884 | * |
885 | * Sets the TSA Controller IP address statically via configuration tool | |
886 | * | |
887 | * NOTE: This TAG is temporarily placed in the dynamic config partition and will | |
888 | * be moved to a private partition during TSA development. It is not used in any | |
889 | * released code yet. | |
890 | */ | |
891 | ||
9f95a23c | 892 | #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */ |
11fdf7f2 TL |
893 | |
894 | #define TLV_MAX_TSACS (4) | |
895 | typedef struct tlv_tsac_config { | |
896 | uint32_t tag; | |
897 | uint32_t length; | |
898 | uint32_t num_tsacs; | |
899 | uint32_t ip[TLV_MAX_TSACS]; | |
900 | uint32_t port[TLV_MAX_TSACS]; | |
901 | } tlv_tsac_config_t; | |
902 | ||
9f95a23c | 903 | /* Binding ticket (DEPRECATED) |
11fdf7f2 TL |
904 | * |
905 | * Sets the TSA NIC binding ticket used for binding process between the TSA NIC | |
906 | * and the TSA Controller | |
907 | * | |
908 | * NOTE: This TAG is temporarily placed in the dynamic config partition and will | |
909 | * be moved to a private partition during TSA development. It is not used in any | |
910 | * released code yet. | |
911 | */ | |
912 | ||
9f95a23c | 913 | #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */ |
11fdf7f2 TL |
914 | |
915 | typedef struct tlv_binding_ticket { | |
916 | uint32_t tag; | |
917 | uint32_t length; | |
918 | uint8_t bytes[]; | |
919 | } tlv_binding_ticket_t; | |
920 | ||
921 | /* Solarflare private key (DEPRECATED) | |
922 | * | |
923 | * Sets the Solareflare private key used for signing during the binding process | |
924 | * | |
925 | * NOTE: This TAG is temporarily placed in the dynamic config partition and will | |
926 | * be moved to a private partition during TSA development. It is not used in any | |
927 | * released code yet. | |
928 | */ | |
929 | ||
930 | #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */ | |
931 | ||
932 | typedef struct tlv_pik_sf { | |
933 | uint32_t tag; | |
934 | uint32_t length; | |
935 | uint8_t bytes[]; | |
936 | } tlv_pik_sf_t; | |
937 | ||
9f95a23c | 938 | /* CA root certificate (DEPRECATED) |
11fdf7f2 TL |
939 | * |
940 | * Sets the CA root certificate used for TSA Controller verfication during | |
941 | * TLS connection setup between the TSA NIC and the TSA Controller | |
942 | * | |
943 | * NOTE: This TAG is temporarily placed in the dynamic config partition and will | |
944 | * be moved to a private partition during TSA development. It is not used in any | |
945 | * released code yet. | |
946 | */ | |
947 | ||
9f95a23c | 948 | #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */ |
11fdf7f2 TL |
949 | |
950 | typedef struct tlv_ca_root_cert { | |
951 | uint32_t tag; | |
952 | uint32_t length; | |
953 | uint8_t bytes[]; | |
954 | } tlv_ca_root_cert_t; | |
955 | ||
956 | /* Tx vFIFO Low latency configuration | |
957 | * | |
958 | * To keep the desired booting behaviour for the switch, it just requires to | |
959 | * know if the low latency mode is enabled. | |
960 | */ | |
961 | ||
962 | #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000) | |
963 | struct tlv_tx_vfifo_ull_mode { | |
964 | uint32_t tag; | |
965 | uint32_t length; | |
966 | uint8_t mode; | |
967 | #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0 | |
968 | }; | |
969 | ||
970 | /* BIU mode | |
971 | * | |
972 | * Medford2 tag for selecting VI window decode (see values below) | |
973 | */ | |
974 | #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000) | |
975 | struct tlv_biu_vi_window_mode { | |
976 | uint32_t tag; | |
977 | uint32_t length; | |
978 | uint8_t mode; | |
979 | #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */ | |
980 | #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */ | |
981 | #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */ | |
982 | }; | |
983 | ||
984 | /* FastPD mode | |
985 | * | |
986 | * Medford2 tag for configuring the FastPD mode (see values below) | |
987 | */ | |
988 | #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port)) | |
989 | struct tlv_fastpd_mode { | |
990 | uint32_t tag; | |
991 | uint32_t length; | |
992 | uint8_t mode; | |
993 | #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */ | |
994 | #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */ | |
995 | #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */ | |
996 | }; | |
997 | ||
9f95a23c TL |
998 | /* L3xUDP datapath firmware UDP port configuration |
999 | * | |
1000 | * Sets the list of UDP ports on which the encapsulation will be handled. | |
1001 | * The number of ports in the list is implied by the length of the TLV item. | |
1002 | */ | |
1003 | #define TLV_TAG_L3XUDP_PORTS (0x102a0000) | |
1004 | struct tlv_l3xudp_ports { | |
1005 | uint32_t tag; | |
1006 | uint32_t length; | |
1007 | uint16_t ports[]; | |
1008 | #define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16 | |
1009 | }; | |
1010 | ||
1011 | /* Wake on LAN setting | |
1012 | * | |
1013 | * Enables the Wake On Lan (WoL) functionality on the given port. This will be | |
1014 | * a persistent setting for manageability firmware. Drivers have direct access | |
1015 | * to WoL using MCDI. | |
1016 | */ | |
1017 | #define TLV_TAG_WAKE_ON_LAN(port) (0x102b0000 + (port)) | |
1018 | struct tlv_wake_on_lan { | |
1019 | uint32_t tag; | |
1020 | uint32_t length; | |
1021 | uint8_t mode; | |
1022 | uint8_t bytes[]; | |
1023 | #define TLV_WAKE_ON_LAN_MODE_DISABLED 0 | |
1024 | #define TLV_WAKE_ON_LAN_MODE_MAGIC_PACKET 1 | |
1025 | #define TLV_WAKE_ON_LAN_MAX_NUM_BYTES 255 | |
1026 | }; | |
1027 | ||
11fdf7f2 | 1028 | #endif /* CI_MGMT_TLV_LAYOUT_H */ |