projects / ceph.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c673cae FG |
1 | ; BSD LICENSE |
| 2 | ; | |
| 3 | ; Copyright(c) 2015-2016 Intel Corporation. All rights reserved. | |
| 4 | ; All rights reserved. | |
| 5 | ; | |
| 6 | ; Redistribution and use in source and binary forms, with or without | |
| 7 | ; modification, are permitted provided that the following conditions | |
| 8 | ; are met: | |
| 9 | ; | |
| 10 | ; * Redistributions of source code must retain the above copyright | |
| 11 | ; notice, this list of conditions and the following disclaimer. | |
| 12 | ; * Redistributions in binary form must reproduce the above copyright | |
| 13 | ; notice, this list of conditions and the following disclaimer in | |
| 14 | ; the documentation and/or other materials provided with the | |
| 15 | ; distribution. | |
| 16 | ; * Neither the name of Intel Corporation nor the names of its | |
| 17 | ; contributors may be used to endorse or promote products derived | |
| 18 | ; from this software without specific prior written permission. | |
| 19 | ; | |
| 20 | ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | ||
| 32 | ; | |
| 33 | ; The pass-through pipeline below connects the input ports to the output ports | |
| 34 | ; as follows: RXQ0.0 -> TXQ1.0, RXQ1.0 -> TXQ0.0, RXQ2.0 -> TXQ3.0 and | |
| 35 | ; RXQ3.0 -> TXQ2.0. | |
| 36 | ; ________________ | |
| 37 | ; RXQ0.0 --->|................|---> TXQ1.0 | |
| 38 | ; | | | |
| 39 | ; RXQ1.0 --->|................|---> TXQ0.0 | |
| 40 | ; | Pass-through | | |
| 41 | ; RXQ2.0 --->|................|---> TXQ3.0 | |
| 42 | ; | | | |
| 43 | ; RXQ3.0 --->|................|---> TXQ2.0 | |
| 44 | ; |________________| | |
| 45 | ; | |
| 46 | ||
| 47 | [EAL] | |
| 48 | log_level = 0 | |
| 49 | ||
| 50 | [PIPELINE0] | |
| 51 | type = MASTER | |
| 52 | core = 0 | |
| 53 | ||
| 54 | [PIPELINE1] | |
| 55 | type = PASS-THROUGH | |
| 56 | core = 1 | |
| 57 | pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0 | |
| 58 | pktq_out = TXQ1.0 TXQ0.0 TXQ3.0 TXQ2.0 |