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1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
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3 */
4
5#ifndef _RTE_IO_ARM64_H_
6#define _RTE_IO_ARM64_H_
7
8#ifdef __cplusplus
9extern "C" {
10#endif
11
12#include <stdint.h>
13
14#define RTE_OVERRIDE_IO_H
15
16#include "generic/rte_io.h"
17#include "rte_atomic_64.h"
18
9f95a23c 19static __rte_always_inline uint8_t
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20rte_read8_relaxed(const volatile void *addr)
21{
22 uint8_t val;
23
24 asm volatile(
25 "ldrb %w[val], [%x[addr]]"
26 : [val] "=r" (val)
27 : [addr] "r" (addr));
28 return val;
29}
30
9f95a23c 31static __rte_always_inline uint16_t
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32rte_read16_relaxed(const volatile void *addr)
33{
34 uint16_t val;
35
36 asm volatile(
37 "ldrh %w[val], [%x[addr]]"
38 : [val] "=r" (val)
39 : [addr] "r" (addr));
40 return val;
41}
42
9f95a23c 43static __rte_always_inline uint32_t
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44rte_read32_relaxed(const volatile void *addr)
45{
46 uint32_t val;
47
48 asm volatile(
49 "ldr %w[val], [%x[addr]]"
50 : [val] "=r" (val)
51 : [addr] "r" (addr));
52 return val;
53}
54
9f95a23c 55static __rte_always_inline uint64_t
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56rte_read64_relaxed(const volatile void *addr)
57{
58 uint64_t val;
59
60 asm volatile(
61 "ldr %x[val], [%x[addr]]"
62 : [val] "=r" (val)
63 : [addr] "r" (addr));
64 return val;
65}
66
9f95a23c 67static __rte_always_inline void
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68rte_write8_relaxed(uint8_t val, volatile void *addr)
69{
70 asm volatile(
71 "strb %w[val], [%x[addr]]"
72 :
73 : [val] "r" (val), [addr] "r" (addr));
74}
75
9f95a23c 76static __rte_always_inline void
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77rte_write16_relaxed(uint16_t val, volatile void *addr)
78{
79 asm volatile(
80 "strh %w[val], [%x[addr]]"
81 :
82 : [val] "r" (val), [addr] "r" (addr));
83}
84
9f95a23c 85static __rte_always_inline void
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86rte_write32_relaxed(uint32_t val, volatile void *addr)
87{
88 asm volatile(
89 "str %w[val], [%x[addr]]"
90 :
91 : [val] "r" (val), [addr] "r" (addr));
92}
93
9f95a23c 94static __rte_always_inline void
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95rte_write64_relaxed(uint64_t val, volatile void *addr)
96{
97 asm volatile(
98 "str %x[val], [%x[addr]]"
99 :
100 : [val] "r" (val), [addr] "r" (addr));
101}
102
9f95a23c 103static __rte_always_inline uint8_t
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104rte_read8(const volatile void *addr)
105{
106 uint8_t val;
107 val = rte_read8_relaxed(addr);
108 rte_io_rmb();
109 return val;
110}
111
9f95a23c 112static __rte_always_inline uint16_t
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113rte_read16(const volatile void *addr)
114{
115 uint16_t val;
116 val = rte_read16_relaxed(addr);
117 rte_io_rmb();
118 return val;
119}
120
9f95a23c 121static __rte_always_inline uint32_t
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122rte_read32(const volatile void *addr)
123{
124 uint32_t val;
125 val = rte_read32_relaxed(addr);
126 rte_io_rmb();
127 return val;
128}
129
9f95a23c 130static __rte_always_inline uint64_t
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131rte_read64(const volatile void *addr)
132{
133 uint64_t val;
134 val = rte_read64_relaxed(addr);
135 rte_io_rmb();
136 return val;
137}
138
9f95a23c 139static __rte_always_inline void
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140rte_write8(uint8_t value, volatile void *addr)
141{
142 rte_io_wmb();
143 rte_write8_relaxed(value, addr);
144}
145
9f95a23c 146static __rte_always_inline void
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147rte_write16(uint16_t value, volatile void *addr)
148{
149 rte_io_wmb();
150 rte_write16_relaxed(value, addr);
151}
152
9f95a23c 153static __rte_always_inline void
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154rte_write32(uint32_t value, volatile void *addr)
155{
156 rte_io_wmb();
157 rte_write32_relaxed(value, addr);
158}
159
9f95a23c 160static __rte_always_inline void
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161rte_write64(uint64_t value, volatile void *addr)
162{
163 rte_io_wmb();
164 rte_write64_relaxed(value, addr);
165}
166
167#ifdef __cplusplus
168}
169#endif
170
171#endif /* _RTE_IO_ARM64_H_ */