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7c673cae
FG		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "e1000_api.h"
29
30static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
31static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
32static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
33static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
34
35/**
36 * e1000_init_mac_ops_generic - Initialize MAC function pointers
37 * @hw: pointer to the HW structure
38 *
39 * Setups up the function pointers to no-op functions
40 **/
41void e1000_init_mac_ops_generic(struct e1000_hw *hw)
42{
43 struct e1000_mac_info *mac = &hw->mac;
44 DEBUGFUNC("e1000_init_mac_ops_generic");
45
46 /* General Setup */
47 mac->ops.init_params = e1000_null_ops_generic;
48 mac->ops.init_hw = e1000_null_ops_generic;
49 mac->ops.reset_hw = e1000_null_ops_generic;
50 mac->ops.setup_physical_interface = e1000_null_ops_generic;
51 mac->ops.get_bus_info = e1000_null_ops_generic;
52 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
53 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
54 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
55 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
56 /* LED */
57 mac->ops.cleanup_led = e1000_null_ops_generic;
58 mac->ops.setup_led = e1000_null_ops_generic;
59 mac->ops.blink_led = e1000_null_ops_generic;
60 mac->ops.led_on = e1000_null_ops_generic;
61 mac->ops.led_off = e1000_null_ops_generic;
62 /* LINK */
63 mac->ops.setup_link = e1000_null_ops_generic;
64 mac->ops.get_link_up_info = e1000_null_link_info;
65 mac->ops.check_for_link = e1000_null_ops_generic;
66 /* Management */
67 mac->ops.check_mng_mode = e1000_null_mng_mode;
68 /* VLAN, MC, etc. */
69 mac->ops.update_mc_addr_list = e1000_null_update_mc;
70 mac->ops.clear_vfta = e1000_null_mac_generic;
71 mac->ops.write_vfta = e1000_null_write_vfta;
72 mac->ops.rar_set = e1000_rar_set_generic;
73 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
74}
75
76/**
77 * e1000_null_ops_generic - No-op function, returns 0
78 * @hw: pointer to the HW structure
79 **/
80s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
81{
82 DEBUGFUNC("e1000_null_ops_generic");
83 return E1000_SUCCESS;
84}
85
86/**
87 * e1000_null_mac_generic - No-op function, return void
88 * @hw: pointer to the HW structure
89 **/
90void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
91{
92 DEBUGFUNC("e1000_null_mac_generic");
93 return;
94}
95
96/**
97 * e1000_null_link_info - No-op function, return 0
98 * @hw: pointer to the HW structure
99 **/
100s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
101 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
102{
103 DEBUGFUNC("e1000_null_link_info");
104 return E1000_SUCCESS;
105}
106
107/**
108 * e1000_null_mng_mode - No-op function, return false
109 * @hw: pointer to the HW structure
110 **/
111bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
112{
113 DEBUGFUNC("e1000_null_mng_mode");
114 return false;
115}
116
117/**
118 * e1000_null_update_mc - No-op function, return void
119 * @hw: pointer to the HW structure
120 **/
121void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
122 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
123{
124 DEBUGFUNC("e1000_null_update_mc");
125 return;
126}
127
128/**
129 * e1000_null_write_vfta - No-op function, return void
130 * @hw: pointer to the HW structure
131 **/
132void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
133 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
134{
135 DEBUGFUNC("e1000_null_write_vfta");
136 return;
137}
138
139/**
140 * e1000_null_rar_set - No-op function, return void
141 * @hw: pointer to the HW structure
142 **/
143void e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
144 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
145{
146 DEBUGFUNC("e1000_null_rar_set");
147 return;
148}
149
150/**
151 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
152 * @hw: pointer to the HW structure
153 *
154 * Determines and stores the system bus information for a particular
155 * network interface. The following bus information is determined and stored:
156 * bus speed, bus width, type (PCIe), and PCIe function.
157 **/
158s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
159{
160 struct e1000_mac_info *mac = &hw->mac;
161 struct e1000_bus_info *bus = &hw->bus;
162 s32 ret_val;
163 u16 pcie_link_status;
164
165 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
166
167 bus->type = e1000_bus_type_pci_express;
168
169 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
170 &pcie_link_status);
171 if (ret_val) {
172 bus->width = e1000_bus_width_unknown;
173 bus->speed = e1000_bus_speed_unknown;
174 } else {
175 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
176 case PCIE_LINK_SPEED_2500:
177 bus->speed = e1000_bus_speed_2500;
178 break;
179 case PCIE_LINK_SPEED_5000:
180 bus->speed = e1000_bus_speed_5000;
181 break;
182 default:
183 bus->speed = e1000_bus_speed_unknown;
184 break;
185 }
186
187 bus->width = (enum e1000_bus_width)((pcie_link_status &
188 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
189 }
190
191 mac->ops.set_lan_id(hw);
192
193 return E1000_SUCCESS;
194}
195
196/**
197 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
198 *
199 * @hw: pointer to the HW structure
200 *
201 * Determines the LAN function id by reading memory-mapped registers
202 * and swaps the port value if requested.
203 **/
204static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
205{
206 struct e1000_bus_info *bus = &hw->bus;
207 u32 reg;
208
209 /* The status register reports the correct function number
210 * for the device regardless of function swap state.
211 */
212 reg = E1000_READ_REG(hw, E1000_STATUS);
213 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
214}
215
216/**
217 * e1000_set_lan_id_single_port - Set LAN id for a single port device
218 * @hw: pointer to the HW structure
219 *
220 * Sets the LAN function id to zero for a single port device.
221 **/
222void e1000_set_lan_id_single_port(struct e1000_hw *hw)
223{
224 struct e1000_bus_info *bus = &hw->bus;
225
226 bus->func = 0;
227}
228
229/**
230 * e1000_clear_vfta_generic - Clear VLAN filter table
231 * @hw: pointer to the HW structure
232 *
233 * Clears the register array which contains the VLAN filter table by
234 * setting all the values to 0.
235 **/
236void e1000_clear_vfta_generic(struct e1000_hw *hw)
237{
238 u32 offset;
239
240 DEBUGFUNC("e1000_clear_vfta_generic");
241
242 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
243 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
244 E1000_WRITE_FLUSH(hw);
245 }
246}
247
248/**
249 * e1000_write_vfta_generic - Write value to VLAN filter table
250 * @hw: pointer to the HW structure
251 * @offset: register offset in VLAN filter table
252 * @value: register value written to VLAN filter table
253 *
254 * Writes value at the given offset in the register array which stores
255 * the VLAN filter table.
256 **/
257void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
258{
259 DEBUGFUNC("e1000_write_vfta_generic");
260
261 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
262 E1000_WRITE_FLUSH(hw);
263}
264
265/**
266 * e1000_init_rx_addrs_generic - Initialize receive address's
267 * @hw: pointer to the HW structure
268 * @rar_count: receive address registers
269 *
270 * Setup the receive address registers by setting the base receive address
271 * register to the devices MAC address and clearing all the other receive
272 * address registers to 0.
273 **/
274void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
275{
276 u32 i;
277 u8 mac_addr[ETH_ADDR_LEN] = {0};
278
279 DEBUGFUNC("e1000_init_rx_addrs_generic");
280
281 /* Setup the receive address */
282 DEBUGOUT("Programming MAC Address into RAR[0]\n");
283
284 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
285
286 /* Zero out the other (rar_entry_count - 1) receive addresses */
287 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
288 for (i = 1; i < rar_count; i++)
289 hw->mac.ops.rar_set(hw, mac_addr, i);
290}
291
292/**
293 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
294 * @hw: pointer to the HW structure
295 *
296 * Checks the nvm for an alternate MAC address. An alternate MAC address
297 * can be setup by pre-boot software and must be treated like a permanent
298 * address and must override the actual permanent MAC address. If an
299 * alternate MAC address is found it is programmed into RAR0, replacing
300 * the permanent address that was installed into RAR0 by the Si on reset.
301 * This function will return SUCCESS unless it encounters an error while
302 * reading the EEPROM.
303 **/
304s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
305{
306 u32 i;
307 s32 ret_val;
308 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
309 u8 alt_mac_addr[ETH_ADDR_LEN];
310
311 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
312
313 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
314 if (ret_val)
315 return ret_val;
316
317
318 /* Alternate MAC address is handled by the option ROM for 82580
319 * and newer. SW support not required.
320 */
321 if (hw->mac.type >= e1000_82580)
322 return E1000_SUCCESS;
323
324 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
325 &nvm_alt_mac_addr_offset);
326 if (ret_val) {
327 DEBUGOUT("NVM Read Error\n");
328 return ret_val;
329 }
330
331 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
332 (nvm_alt_mac_addr_offset == 0x0000))
333 /* There is no Alternate MAC Address */
334 return E1000_SUCCESS;
335
336 if (hw->bus.func == E1000_FUNC_1)
337 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
338 if (hw->bus.func == E1000_FUNC_2)
339 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
340
341 if (hw->bus.func == E1000_FUNC_3)
342 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
343 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
344 offset = nvm_alt_mac_addr_offset + (i >> 1);
345 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
346 if (ret_val) {
347 DEBUGOUT("NVM Read Error\n");
348 return ret_val;
349 }
350
351 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
352 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
353 }
354
355 /* if multicast bit is set, the alternate address will not be used */
356 if (alt_mac_addr[0] & 0x01) {
357 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
358 return E1000_SUCCESS;
359 }
360
361 /* We have a valid alternate MAC address, and we want to treat it the
362 * same as the normal permanent MAC address stored by the HW into the
363 * RAR. Do this by mapping this address into RAR0.
364 */
365 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
366
367 return E1000_SUCCESS;
368}
369
370/**
371 * e1000_rar_set_generic - Set receive address register
372 * @hw: pointer to the HW structure
373 * @addr: pointer to the receive address
374 * @index: receive address array register
375 *
376 * Sets the receive address array register at index to the address passed
377 * in by addr.
378 **/
379static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
380{
381 u32 rar_low, rar_high;
382
383 DEBUGFUNC("e1000_rar_set_generic");
384
385 /* HW expects these in little endian so we reverse the byte order
386 * from network order (big endian) to little endian
387 */
388 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
389 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
390
391 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
392
393 /* If MAC address zero, no need to set the AV bit */
394 if (rar_low || rar_high)
395 rar_high |= E1000_RAH_AV;
396
397 /* Some bridges will combine consecutive 32-bit writes into
398 * a single burst write, which will malfunction on some parts.
399 * The flushes avoid this.
400 */
401 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
402 E1000_WRITE_FLUSH(hw);
403 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
404 E1000_WRITE_FLUSH(hw);
405}
406
407/**
408 * e1000_hash_mc_addr_generic - Generate a multicast hash value
409 * @hw: pointer to the HW structure
410 * @mc_addr: pointer to a multicast address
411 *
412 * Generates a multicast address hash value which is used to determine
413 * the multicast filter table array address and new table value.
414 **/
415u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
416{
417 u32 hash_value, hash_mask;
418 u8 bit_shift = 0;
419
420 DEBUGFUNC("e1000_hash_mc_addr_generic");
421
422 /* Register count multiplied by bits per register */
423 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
424
425 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
426 * where 0xFF would still fall within the hash mask.
427 */
428 while (hash_mask >> bit_shift != 0xFF)
429 bit_shift++;
430
431 /* The portion of the address that is used for the hash table
432 * is determined by the mc_filter_type setting.
433 * The algorithm is such that there is a total of 8 bits of shifting.
434 * The bit_shift for a mc_filter_type of 0 represents the number of
435 * left-shifts where the MSB of mc_addr[5] would still fall within
436 * the hash_mask. Case 0 does this exactly. Since there are a total
437 * of 8 bits of shifting, then mc_addr[4] will shift right the
438 * remaining number of bits. Thus 8 - bit_shift. The rest of the
439 * cases are a variation of this algorithm...essentially raising the
440 * number of bits to shift mc_addr[5] left, while still keeping the
441 * 8-bit shifting total.
442 *
443 * For example, given the following Destination MAC Address and an
444 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
445 * we can see that the bit_shift for case 0 is 4. These are the hash
446 * values resulting from each mc_filter_type...
447 * [0] [1] [2] [3] [4] [5]
448 * 01 AA 00 12 34 56
449 * LSB MSB
450 *
451 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
452 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
453 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
454 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
455 */
456 switch (hw->mac.mc_filter_type) {
457 default:
458 case 0:
459 break;
460 case 1:
461 bit_shift += 1;
462 break;
463 case 2:
464 bit_shift += 2;
465 break;
466 case 3:
467 bit_shift += 4;
468 break;
469 }
470
471 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
472 (((u16) mc_addr[5]) << bit_shift)));
473
474 return hash_value;
475}
476
477/**
478 * e1000_update_mc_addr_list_generic - Update Multicast addresses
479 * @hw: pointer to the HW structure
480 * @mc_addr_list: array of multicast addresses to program
481 * @mc_addr_count: number of multicast addresses to program
482 *
483 * Updates entire Multicast Table Array.
484 * The caller must have a packed mc_addr_list of multicast addresses.
485 **/
486void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
487 u8 *mc_addr_list, u32 mc_addr_count)
488{
489 u32 hash_value, hash_bit, hash_reg;
490 int i;
491
492 DEBUGFUNC("e1000_update_mc_addr_list_generic");
493
494 /* clear mta_shadow */
495 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
496
497 /* update mta_shadow from mc_addr_list */
498 for (i = 0; (u32) i < mc_addr_count; i++) {
499 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
500
501 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
502 hash_bit = hash_value & 0x1F;
503
504 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
505 mc_addr_list += (ETH_ADDR_LEN);
506 }
507
508 /* replace the entire MTA table */
509 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
510 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
511 E1000_WRITE_FLUSH(hw);
512}
513
514/**
515 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
516 * @hw: pointer to the HW structure
517 *
518 * Clears the base hardware counters by reading the counter registers.
519 **/
520void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
521{
522 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
523
524 E1000_READ_REG(hw, E1000_CRCERRS);
525 E1000_READ_REG(hw, E1000_SYMERRS);
526 E1000_READ_REG(hw, E1000_MPC);
527 E1000_READ_REG(hw, E1000_SCC);
528 E1000_READ_REG(hw, E1000_ECOL);
529 E1000_READ_REG(hw, E1000_MCC);
530 E1000_READ_REG(hw, E1000_LATECOL);
531 E1000_READ_REG(hw, E1000_COLC);
532 E1000_READ_REG(hw, E1000_DC);
533 E1000_READ_REG(hw, E1000_SEC);
534 E1000_READ_REG(hw, E1000_RLEC);
535 E1000_READ_REG(hw, E1000_XONRXC);
536 E1000_READ_REG(hw, E1000_XONTXC);
537 E1000_READ_REG(hw, E1000_XOFFRXC);
538 E1000_READ_REG(hw, E1000_XOFFTXC);
539 E1000_READ_REG(hw, E1000_FCRUC);
540 E1000_READ_REG(hw, E1000_GPRC);
541 E1000_READ_REG(hw, E1000_BPRC);
542 E1000_READ_REG(hw, E1000_MPRC);
543 E1000_READ_REG(hw, E1000_GPTC);
544 E1000_READ_REG(hw, E1000_GORCL);
545 E1000_READ_REG(hw, E1000_GORCH);
546 E1000_READ_REG(hw, E1000_GOTCL);
547 E1000_READ_REG(hw, E1000_GOTCH);
548 E1000_READ_REG(hw, E1000_RNBC);
549 E1000_READ_REG(hw, E1000_RUC);
550 E1000_READ_REG(hw, E1000_RFC);
551 E1000_READ_REG(hw, E1000_ROC);
552 E1000_READ_REG(hw, E1000_RJC);
553 E1000_READ_REG(hw, E1000_TORL);
554 E1000_READ_REG(hw, E1000_TORH);
555 E1000_READ_REG(hw, E1000_TOTL);
556 E1000_READ_REG(hw, E1000_TOTH);
557 E1000_READ_REG(hw, E1000_TPR);
558 E1000_READ_REG(hw, E1000_TPT);
559 E1000_READ_REG(hw, E1000_MPTC);
560 E1000_READ_REG(hw, E1000_BPTC);
561}
562
563/**
564 * e1000_check_for_copper_link_generic - Check for link (Copper)
565 * @hw: pointer to the HW structure
566 *
567 * Checks to see of the link status of the hardware has changed. If a
568 * change in link status has been detected, then we read the PHY registers
569 * to get the current speed/duplex if link exists.
570 **/
571s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
572{
573 struct e1000_mac_info *mac = &hw->mac;
574 s32 ret_val;
575 bool link;
576
577 DEBUGFUNC("e1000_check_for_copper_link");
578
579 /* We only want to go out to the PHY registers to see if Auto-Neg
580 * has completed and/or if our link status has changed. The
581 * get_link_status flag is set upon receiving a Link Status
582 * Change or Rx Sequence Error interrupt.
583 */
584 if (!mac->get_link_status)
585 return E1000_SUCCESS;
586
587 /* First we want to see if the MII Status Register reports
588 * link. If so, then we want to get the current speed/duplex
589 * of the PHY.
590 */
591 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
592 if (ret_val)
593 return ret_val;
594
595 if (!link)
596 return E1000_SUCCESS; /* No link detected */
597
598 mac->get_link_status = false;
599
600 /* Check if there was DownShift, must be checked
601 * immediately after link-up
602 */
603 e1000_check_downshift_generic(hw);
604
605 /* If we are forcing speed/duplex, then we simply return since
606 * we have already determined whether we have link or not.
607 */
608 if (!mac->autoneg)
609 return -E1000_ERR_CONFIG;
610
611 /* Auto-Neg is enabled. Auto Speed Detection takes care
612 * of MAC speed/duplex configuration. So we only need to
613 * configure Collision Distance in the MAC.
614 */
615 mac->ops.config_collision_dist(hw);
616
617 /* Configure Flow Control now that Auto-Neg has completed.
618 * First, we need to restore the desired flow control
619 * settings because we may have had to re-autoneg with a
620 * different link partner.
621 */
622 ret_val = e1000_config_fc_after_link_up_generic(hw);
623 if (ret_val)
624 DEBUGOUT("Error configuring flow control\n");
625
626 return ret_val;
627}
628
629/**
630 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
631 * @hw: pointer to the HW structure
632 *
633 * Checks for link up on the hardware. If link is not up and we have
634 * a signal, then we need to force link up.
635 **/
636s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
637{
638 struct e1000_mac_info *mac = &hw->mac;
639 u32 rxcw;
640 u32 ctrl;
641 u32 status;
642 s32 ret_val;
643
644 DEBUGFUNC("e1000_check_for_fiber_link_generic");
645
646 ctrl = E1000_READ_REG(hw, E1000_CTRL);
647 status = E1000_READ_REG(hw, E1000_STATUS);
648 rxcw = E1000_READ_REG(hw, E1000_RXCW);
649
650 /* If we don't have link (auto-negotiation failed or link partner
651 * cannot auto-negotiate), the cable is plugged in (we have signal),
652 * and our link partner is not trying to auto-negotiate with us (we
653 * are receiving idles or data), we need to force link up. We also
654 * need to give auto-negotiation time to complete, in case the cable
655 * was just plugged in. The autoneg_failed flag does this.
656 */
657 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
658 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
659 !(rxcw & E1000_RXCW_C)) {
660 if (!mac->autoneg_failed) {
661 mac->autoneg_failed = true;
662 return E1000_SUCCESS;
663 }
664 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
665
666 /* Disable auto-negotiation in the TXCW register */
667 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
668
669 /* Force link-up and also force full-duplex. */
670 ctrl = E1000_READ_REG(hw, E1000_CTRL);
671 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
672 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
673
674 /* Configure Flow Control after forcing link up. */
675 ret_val = e1000_config_fc_after_link_up_generic(hw);
676 if (ret_val) {
677 DEBUGOUT("Error configuring flow control\n");
678 return ret_val;
679 }
680 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
681 /* If we are forcing link and we are receiving /C/ ordered
682 * sets, re-enable auto-negotiation in the TXCW register
683 * and disable forced link in the Device Control register
684 * in an attempt to auto-negotiate with our link partner.
685 */
686 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
687 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
688 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
689
690 mac->serdes_has_link = true;
691 }
692
693 return E1000_SUCCESS;
694}
695
696/**
697 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
698 * @hw: pointer to the HW structure
699 *
700 * Checks for link up on the hardware. If link is not up and we have
701 * a signal, then we need to force link up.
702 **/
703s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
704{
705 struct e1000_mac_info *mac = &hw->mac;
706 u32 rxcw;
707 u32 ctrl;
708 u32 status;
709 s32 ret_val;
710
711 DEBUGFUNC("e1000_check_for_serdes_link_generic");
712
713 ctrl = E1000_READ_REG(hw, E1000_CTRL);
714 status = E1000_READ_REG(hw, E1000_STATUS);
715 rxcw = E1000_READ_REG(hw, E1000_RXCW);
716
717 /* If we don't have link (auto-negotiation failed or link partner
718 * cannot auto-negotiate), and our link partner is not trying to
719 * auto-negotiate with us (we are receiving idles or data),
720 * we need to force link up. We also need to give auto-negotiation
721 * time to complete.
722 */
723 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
724 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
725 if (!mac->autoneg_failed) {
726 mac->autoneg_failed = true;
727 return E1000_SUCCESS;
728 }
729 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
730
731 /* Disable auto-negotiation in the TXCW register */
732 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
733
734 /* Force link-up and also force full-duplex. */
735 ctrl = E1000_READ_REG(hw, E1000_CTRL);
736 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
737 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
738
739 /* Configure Flow Control after forcing link up. */
740 ret_val = e1000_config_fc_after_link_up_generic(hw);
741 if (ret_val) {
742 DEBUGOUT("Error configuring flow control\n");
743 return ret_val;
744 }
745 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
746 /* If we are forcing link and we are receiving /C/ ordered
747 * sets, re-enable auto-negotiation in the TXCW register
748 * and disable forced link in the Device Control register
749 * in an attempt to auto-negotiate with our link partner.
750 */
751 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
752 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
753 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
754
755 mac->serdes_has_link = true;
756 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
757 /* If we force link for non-auto-negotiation switch, check
758 * link status based on MAC synchronization for internal
759 * serdes media type.
760 */
761 /* SYNCH bit and IV bit are sticky. */
762 usec_delay(10);
763 rxcw = E1000_READ_REG(hw, E1000_RXCW);
764 if (rxcw & E1000_RXCW_SYNCH) {
765 if (!(rxcw & E1000_RXCW_IV)) {
766 mac->serdes_has_link = true;
767 DEBUGOUT("SERDES: Link up - forced.\n");
768 }
769 } else {
770 mac->serdes_has_link = false;
771 DEBUGOUT("SERDES: Link down - force failed.\n");
772 }
773 }
774
775 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
776 status = E1000_READ_REG(hw, E1000_STATUS);
777 if (status & E1000_STATUS_LU) {
778 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
779 usec_delay(10);
780 rxcw = E1000_READ_REG(hw, E1000_RXCW);
781 if (rxcw & E1000_RXCW_SYNCH) {
782 if (!(rxcw & E1000_RXCW_IV)) {
783 mac->serdes_has_link = true;
784 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
785 } else {
786 mac->serdes_has_link = false;
787 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
788 }
789 } else {
790 mac->serdes_has_link = false;
791 DEBUGOUT("SERDES: Link down - no sync.\n");
792 }
793 } else {
794 mac->serdes_has_link = false;
795 DEBUGOUT("SERDES: Link down - autoneg failed\n");
796 }
797 }
798
799 return E1000_SUCCESS;
800}
801
802/**
803 * e1000_set_default_fc_generic - Set flow control default values
804 * @hw: pointer to the HW structure
805 *
806 * Read the EEPROM for the default values for flow control and store the
807 * values.
808 **/
809static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
810{
811 s32 ret_val;
812 u16 nvm_data;
813
814 DEBUGFUNC("e1000_set_default_fc_generic");
815
816 /* Read and store word 0x0F of the EEPROM. This word contains bits
817 * that determine the hardware's default PAUSE (flow control) mode,
818 * a bit that determines whether the HW defaults to enabling or
819 * disabling auto-negotiation, and the direction of the
820 * SW defined pins. If there is no SW over-ride of the flow
821 * control setting, then the variable hw->fc will
822 * be initialized based on a value in the EEPROM.
823 */
824 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
825
826 if (ret_val) {
827 DEBUGOUT("NVM Read Error\n");
828 return ret_val;
829 }
830
831 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
832 hw->fc.requested_mode = e1000_fc_none;
833 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
834 NVM_WORD0F_ASM_DIR)
835 hw->fc.requested_mode = e1000_fc_tx_pause;
836 else
837 hw->fc.requested_mode = e1000_fc_full;
838
839 return E1000_SUCCESS;
840}
841
842/**
843 * e1000_setup_link_generic - Setup flow control and link settings
844 * @hw: pointer to the HW structure
845 *
846 * Determines which flow control settings to use, then configures flow
847 * control. Calls the appropriate media-specific link configuration
848 * function. Assuming the adapter has a valid link partner, a valid link
849 * should be established. Assumes the hardware has previously been reset
850 * and the transmitter and receiver are not enabled.
851 **/
852s32 e1000_setup_link_generic(struct e1000_hw *hw)
853{
854 s32 ret_val;
855
856 DEBUGFUNC("e1000_setup_link_generic");
857
858 /* In the case of the phy reset being blocked, we already have a link.
859 * We do not need to set it up again.
860 */
861 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
862 return E1000_SUCCESS;
863
864 /* If requested flow control is set to default, set flow control
865 * based on the EEPROM flow control settings.
866 */
867 if (hw->fc.requested_mode == e1000_fc_default) {
868 ret_val = e1000_set_default_fc_generic(hw);
869 if (ret_val)
870 return ret_val;
871 }
872
873 /* Save off the requested flow control mode for use later. Depending
874 * on the link partner's capabilities, we may or may not use this mode.
875 */
876 hw->fc.current_mode = hw->fc.requested_mode;
877
878 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
879 hw->fc.current_mode);
880
881 /* Call the necessary media_type subroutine to configure the link. */
882 ret_val = hw->mac.ops.setup_physical_interface(hw);
883 if (ret_val)
884 return ret_val;
885
886 /* Initialize the flow control address, type, and PAUSE timer
887 * registers to their default values. This is done even if flow
888 * control is disabled, because it does not hurt anything to
889 * initialize these registers.
890 */
891 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
892 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
893 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
894 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
895
896 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
897
898 return e1000_set_fc_watermarks_generic(hw);
899}
900
901/**
902 * e1000_commit_fc_settings_generic - Configure flow control
903 * @hw: pointer to the HW structure
904 *
905 * Write the flow control settings to the Transmit Config Word Register (TXCW)
906 * base on the flow control settings in e1000_mac_info.
907 **/
908static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
909{
910 struct e1000_mac_info *mac = &hw->mac;
911 u32 txcw;
912
913 DEBUGFUNC("e1000_commit_fc_settings_generic");
914
915 /* Check for a software override of the flow control settings, and
916 * setup the device accordingly. If auto-negotiation is enabled, then
917 * software will have to set the "PAUSE" bits to the correct value in
918 * the Transmit Config Word Register (TXCW) and re-start auto-
919 * negotiation. However, if auto-negotiation is disabled, then
920 * software will have to manually configure the two flow control enable
921 * bits in the CTRL register.
922 *
923 * The possible values of the "fc" parameter are:
924 * 0: Flow control is completely disabled
925 * 1: Rx flow control is enabled (we can receive pause frames,
926 * but not send pause frames).
927 * 2: Tx flow control is enabled (we can send pause frames but we
928 * do not support receiving pause frames).
929 * 3: Both Rx and Tx flow control (symmetric) are enabled.
930 */
931 switch (hw->fc.current_mode) {
932 case e1000_fc_none:
933 /* Flow control completely disabled by a software over-ride. */
934 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
935 break;
936 case e1000_fc_rx_pause:
937 /* Rx Flow control is enabled and Tx Flow control is disabled
938 * by a software over-ride. Since there really isn't a way to
939 * advertise that we are capable of Rx Pause ONLY, we will
940 * advertise that we support both symmetric and asymmetric Rx
941 * PAUSE. Later, we will disable the adapter's ability to send
942 * PAUSE frames.
943 */
944 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
945 break;
946 case e1000_fc_tx_pause:
947 /* Tx Flow control is enabled, and Rx Flow control is disabled,
948 * by a software over-ride.
949 */
950 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
951 break;
952 case e1000_fc_full:
953 /* Flow control (both Rx and Tx) is enabled by a software
954 * over-ride.
955 */
956 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
957 break;
958 default:
959 DEBUGOUT("Flow control param set incorrectly\n");
960 return -E1000_ERR_CONFIG;
961 break;
962 }
963
964 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
965 mac->txcw = txcw;
966
967 return E1000_SUCCESS;
968}
969
970/**
971 * e1000_poll_fiber_serdes_link_generic - Poll for link up
972 * @hw: pointer to the HW structure
973 *
974 * Polls for link up by reading the status register, if link fails to come
975 * up with auto-negotiation, then the link is forced if a signal is detected.
976 **/
977static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
978{
979 struct e1000_mac_info *mac = &hw->mac;
980 u32 i, status;
981 s32 ret_val;
982
983 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
984
985 /* If we have a signal (the cable is plugged in, or assumed true for
986 * serdes media) then poll for a "Link-Up" indication in the Device
987 * Status Register. Time-out if a link isn't seen in 500 milliseconds
988 * seconds (Auto-negotiation should complete in less than 500
989 * milliseconds even if the other end is doing it in SW).
990 */
991 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
992 msec_delay(10);
993 status = E1000_READ_REG(hw, E1000_STATUS);
994 if (status & E1000_STATUS_LU)
995 break;
996 }
997 if (i == FIBER_LINK_UP_LIMIT) {
998 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
999 mac->autoneg_failed = true;
1000 /* AutoNeg failed to achieve a link, so we'll call
1001 * mac->check_for_link. This routine will force the
1002 * link up if we detect a signal. This will allow us to
1003 * communicate with non-autonegotiating link partners.
1004 */
1005 ret_val = mac->ops.check_for_link(hw);
1006 if (ret_val) {
1007 DEBUGOUT("Error while checking for link\n");
1008 return ret_val;
1009 }
1010 mac->autoneg_failed = false;
1011 } else {
1012 mac->autoneg_failed = false;
1013 DEBUGOUT("Valid Link Found\n");
1014 }
1015
1016 return E1000_SUCCESS;
1017}
1018
1019/**
1020 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1021 * @hw: pointer to the HW structure
1022 *
1023 * Configures collision distance and flow control for fiber and serdes
1024 * links. Upon successful setup, poll for link.
1025 **/
1026s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1027{
1028 u32 ctrl;
1029 s32 ret_val;
1030
1031 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1032
1033 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1034
1035 /* Take the link out of reset */
1036 ctrl &= ~E1000_CTRL_LRST;
1037
1038 hw->mac.ops.config_collision_dist(hw);
1039
1040 ret_val = e1000_commit_fc_settings_generic(hw);
1041 if (ret_val)
1042 return ret_val;
1043
1044 /* Since auto-negotiation is enabled, take the link out of reset (the
1045 * link will be in reset, because we previously reset the chip). This
1046 * will restart auto-negotiation. If auto-negotiation is successful
1047 * then the link-up status bit will be set and the flow control enable
1048 * bits (RFCE and TFCE) will be set according to their negotiated value.
1049 */
1050 DEBUGOUT("Auto-negotiation enabled\n");
1051
1052 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1053 E1000_WRITE_FLUSH(hw);
1054 msec_delay(1);
1055
1056 /* For these adapters, the SW definable pin 1 is set when the optics
1057 * detect a signal. If we have a signal, then poll for a "Link-Up"
1058 * indication.
1059 */
1060 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1061 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1062 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1063 } else {
1064 DEBUGOUT("No signal detected\n");
1065 }
1066
1067 return ret_val;
1068}
1069
1070/**
1071 * e1000_config_collision_dist_generic - Configure collision distance
1072 * @hw: pointer to the HW structure
1073 *
1074 * Configures the collision distance to the default value and is used
1075 * during link setup.
1076 **/
1077static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1078{
1079 u32 tctl;
1080
1081 DEBUGFUNC("e1000_config_collision_dist_generic");
1082
1083 tctl = E1000_READ_REG(hw, E1000_TCTL);
1084
1085 tctl &= ~E1000_TCTL_COLD;
1086 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1087
1088 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1089 E1000_WRITE_FLUSH(hw);
1090}
1091
1092/**
1093 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1094 * @hw: pointer to the HW structure
1095 *
1096 * Sets the flow control high/low threshold (watermark) registers. If
1097 * flow control XON frame transmission is enabled, then set XON frame
1098 * transmission as well.
1099 **/
1100s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1101{
1102 u32 fcrtl = 0, fcrth = 0;
1103
1104 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1105
1106 /* Set the flow control receive threshold registers. Normally,
1107 * these registers will be set to a default threshold that may be
1108 * adjusted later by the driver's runtime code. However, if the
1109 * ability to transmit pause frames is not enabled, then these
1110 * registers will be set to 0.
1111 */
1112 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1113 /* We need to set up the Receive Threshold high and low water
1114 * marks as well as (optionally) enabling the transmission of
1115 * XON frames.
1116 */
1117 fcrtl = hw->fc.low_water;
1118 if (hw->fc.send_xon)
1119 fcrtl |= E1000_FCRTL_XONE;
1120
1121 fcrth = hw->fc.high_water;
1122 }
1123 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1124 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1125
1126 return E1000_SUCCESS;
1127}
1128
1129/**
1130 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1131 * @hw: pointer to the HW structure
1132 *
1133 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1134 * device control register to reflect the adapter settings. TFCE and RFCE
1135 * need to be explicitly set by software when a copper PHY is used because
1136 * autonegotiation is managed by the PHY rather than the MAC. Software must
1137 * also configure these bits when link is forced on a fiber connection.
1138 **/
1139s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1140{
1141 u32 ctrl;
1142
1143 DEBUGFUNC("e1000_force_mac_fc_generic");
1144
1145 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1146
1147 /* Because we didn't get link via the internal auto-negotiation
1148 * mechanism (we either forced link or we got link via PHY
1149 * auto-neg), we have to manually enable/disable transmit an
1150 * receive flow control.
1151 *
1152 * The "Case" statement below enables/disable flow control
1153 * according to the "hw->fc.current_mode" parameter.
1154 *
1155 * The possible values of the "fc" parameter are:
1156 * 0: Flow control is completely disabled
1157 * 1: Rx flow control is enabled (we can receive pause
1158 * frames but not send pause frames).
1159 * 2: Tx flow control is enabled (we can send pause frames
1160 * frames but we do not receive pause frames).
1161 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1162 * other: No other values should be possible at this point.
1163 */
1164 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1165
1166 switch (hw->fc.current_mode) {
1167 case e1000_fc_none:
1168 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1169 break;
1170 case e1000_fc_rx_pause:
1171 ctrl &= (~E1000_CTRL_TFCE);
1172 ctrl |= E1000_CTRL_RFCE;
1173 break;
1174 case e1000_fc_tx_pause:
1175 ctrl &= (~E1000_CTRL_RFCE);
1176 ctrl |= E1000_CTRL_TFCE;
1177 break;
1178 case e1000_fc_full:
1179 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1180 break;
1181 default:
1182 DEBUGOUT("Flow control param set incorrectly\n");
1183 return -E1000_ERR_CONFIG;
1184 }
1185
1186 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1187
1188 return E1000_SUCCESS;
1189}
1190
1191/**
1192 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1193 * @hw: pointer to the HW structure
1194 *
1195 * Checks the status of auto-negotiation after link up to ensure that the
1196 * speed and duplex were not forced. If the link needed to be forced, then
1197 * flow control needs to be forced also. If auto-negotiation is enabled
1198 * and did not fail, then we configure flow control based on our link
1199 * partner.
1200 **/
1201s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1202{
1203 struct e1000_mac_info *mac = &hw->mac;
1204 s32 ret_val = E1000_SUCCESS;
1205 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1206 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1207 u16 speed, duplex;
1208
1209 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1210
1211 /* Check for the case where we have fiber media and auto-neg failed
1212 * so we had to force link. In this case, we need to force the
1213 * configuration of the MAC to match the "fc" parameter.
1214 */
1215 if (mac->autoneg_failed) {
1216 if (hw->phy.media_type == e1000_media_type_fiber ||
1217 hw->phy.media_type == e1000_media_type_internal_serdes)
1218 ret_val = e1000_force_mac_fc_generic(hw);
1219 } else {
1220 if (hw->phy.media_type == e1000_media_type_copper)
1221 ret_val = e1000_force_mac_fc_generic(hw);
1222 }
1223
1224 if (ret_val) {
1225 DEBUGOUT("Error forcing flow control settings\n");
1226 return ret_val;
1227 }
1228
1229 /* Check for the case where we have copper media and auto-neg is
1230 * enabled. In this case, we need to check and see if Auto-Neg
1231 * has completed, and if so, how the PHY and link partner has
1232 * flow control configured.
1233 */
1234 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1235 /* Read the MII Status Register and check to see if AutoNeg
1236 * has completed. We read this twice because this reg has
1237 * some "sticky" (latched) bits.
1238 */
1239 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1240 if (ret_val)
1241 return ret_val;
1242 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1243 if (ret_val)
1244 return ret_val;
1245
1246 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1247 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1248 return ret_val;
1249 }
1250
1251 /* The AutoNeg process has completed, so we now need to
1252 * read both the Auto Negotiation Advertisement
1253 * Register (Address 4) and the Auto_Negotiation Base
1254 * Page Ability Register (Address 5) to determine how
1255 * flow control was negotiated.
1256 */
1257 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1258 &mii_nway_adv_reg);
1259 if (ret_val)
1260 return ret_val;
1261 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1262 &mii_nway_lp_ability_reg);
1263 if (ret_val)
1264 return ret_val;
1265
1266 /* Two bits in the Auto Negotiation Advertisement Register
1267 * (Address 4) and two bits in the Auto Negotiation Base
1268 * Page Ability Register (Address 5) determine flow control
1269 * for both the PHY and the link partner. The following
1270 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1271 * 1999, describes these PAUSE resolution bits and how flow
1272 * control is determined based upon these settings.
1273 * NOTE: DC = Don't Care
1274 *
1275 * LOCAL DEVICE | LINK PARTNER
1276 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1277 *-------|---------|-------|---------|--------------------
1278 * 0 | 0 | DC | DC | e1000_fc_none
1279 * 0 | 1 | 0 | DC | e1000_fc_none
1280 * 0 | 1 | 1 | 0 | e1000_fc_none
1281 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1282 * 1 | 0 | 0 | DC | e1000_fc_none
1283 * 1 | DC | 1 | DC | e1000_fc_full
1284 * 1 | 1 | 0 | 0 | e1000_fc_none
1285 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1286 *
1287 * Are both PAUSE bits set to 1? If so, this implies
1288 * Symmetric Flow Control is enabled at both ends. The
1289 * ASM_DIR bits are irrelevant per the spec.
1290 *
1291 * For Symmetric Flow Control:
1292 *
1293 * LOCAL DEVICE | LINK PARTNER
1294 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1295 *-------|---------|-------|---------|--------------------
1296 * 1 | DC | 1 | DC | E1000_fc_full
1297 *
1298 */
1299 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1300 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1301 /* Now we need to check if the user selected Rx ONLY
1302 * of pause frames. In this case, we had to advertise
1303 * FULL flow control because we could not advertise Rx
1304 * ONLY. Hence, we must now check to see if we need to
1305 * turn OFF the TRANSMISSION of PAUSE frames.
1306 */
1307 if (hw->fc.requested_mode == e1000_fc_full) {
1308 hw->fc.current_mode = e1000_fc_full;
1309 DEBUGOUT("Flow Control = FULL.\n");
1310 } else {
1311 hw->fc.current_mode = e1000_fc_rx_pause;
1312 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1313 }
1314 }
1315 /* For receiving PAUSE frames ONLY.
1316 *
1317 * LOCAL DEVICE | LINK PARTNER
1318 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1319 *-------|---------|-------|---------|--------------------
1320 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1321 */
1322 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1323 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1324 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1325 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1326 hw->fc.current_mode = e1000_fc_tx_pause;
1327 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1328 }
1329 /* For transmitting PAUSE frames ONLY.
1330 *
1331 * LOCAL DEVICE | LINK PARTNER
1332 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1333 *-------|---------|-------|---------|--------------------
1334 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1335 */
1336 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1337 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1338 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1339 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1340 hw->fc.current_mode = e1000_fc_rx_pause;
1341 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1342 } else {
1343 /* Per the IEEE spec, at this point flow control
1344 * should be disabled.
1345 */
1346 hw->fc.current_mode = e1000_fc_none;
1347 DEBUGOUT("Flow Control = NONE.\n");
1348 }
1349
1350 /* Now we need to do one last check... If we auto-
1351 * negotiated to HALF DUPLEX, flow control should not be
1352 * enabled per IEEE 802.3 spec.
1353 */
1354 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1355 if (ret_val) {
1356 DEBUGOUT("Error getting link speed and duplex\n");
1357 return ret_val;
1358 }
1359
1360 if (duplex == HALF_DUPLEX)
1361 hw->fc.current_mode = e1000_fc_none;
1362
1363 /* Now we call a subroutine to actually force the MAC
1364 * controller to use the correct flow control settings.
1365 */
1366 ret_val = e1000_force_mac_fc_generic(hw);
1367 if (ret_val) {
1368 DEBUGOUT("Error forcing flow control settings\n");
1369 return ret_val;
1370 }
1371 }
1372
1373 /* Check for the case where we have SerDes media and auto-neg is
1374 * enabled. In this case, we need to check and see if Auto-Neg
1375 * has completed, and if so, how the PHY and link partner has
1376 * flow control configured.
1377 */
1378 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1379 mac->autoneg) {
1380 /* Read the PCS_LSTS and check to see if AutoNeg
1381 * has completed.
1382 */
1383 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1384
1385 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1386 DEBUGOUT("PCS Auto Neg has not completed.\n");
1387 return ret_val;
1388 }
1389
1390 /* The AutoNeg process has completed, so we now need to
1391 * read both the Auto Negotiation Advertisement
1392 * Register (PCS_ANADV) and the Auto_Negotiation Base
1393 * Page Ability Register (PCS_LPAB) to determine how
1394 * flow control was negotiated.
1395 */
1396 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1397 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1398
1399 /* Two bits in the Auto Negotiation Advertisement Register
1400 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1401 * Page Ability Register (PCS_LPAB) determine flow control
1402 * for both the PHY and the link partner. The following
1403 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1404 * 1999, describes these PAUSE resolution bits and how flow
1405 * control is determined based upon these settings.
1406 * NOTE: DC = Don't Care
1407 *
1408 * LOCAL DEVICE | LINK PARTNER
1409 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1410 *-------|---------|-------|---------|--------------------
1411 * 0 | 0 | DC | DC | e1000_fc_none
1412 * 0 | 1 | 0 | DC | e1000_fc_none
1413 * 0 | 1 | 1 | 0 | e1000_fc_none
1414 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1415 * 1 | 0 | 0 | DC | e1000_fc_none
1416 * 1 | DC | 1 | DC | e1000_fc_full
1417 * 1 | 1 | 0 | 0 | e1000_fc_none
1418 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1419 *
1420 * Are both PAUSE bits set to 1? If so, this implies
1421 * Symmetric Flow Control is enabled at both ends. The
1422 * ASM_DIR bits are irrelevant per the spec.
1423 *
1424 * For Symmetric Flow Control:
1425 *
1426 * LOCAL DEVICE | LINK PARTNER
1427 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1428 *-------|---------|-------|---------|--------------------
1429 * 1 | DC | 1 | DC | e1000_fc_full
1430 *
1431 */
1432 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1433 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1434 /* Now we need to check if the user selected Rx ONLY
1435 * of pause frames. In this case, we had to advertise
1436 * FULL flow control because we could not advertise Rx
1437 * ONLY. Hence, we must now check to see if we need to
1438 * turn OFF the TRANSMISSION of PAUSE frames.
1439 */
1440 if (hw->fc.requested_mode == e1000_fc_full) {
1441 hw->fc.current_mode = e1000_fc_full;
1442 DEBUGOUT("Flow Control = FULL.\n");
1443 } else {
1444 hw->fc.current_mode = e1000_fc_rx_pause;
1445 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1446 }
1447 }
1448 /* For receiving PAUSE frames ONLY.
1449 *
1450 * LOCAL DEVICE | LINK PARTNER
1451 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1452 *-------|---------|-------|---------|--------------------
1453 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1454 */
1455 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1456 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1457 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1458 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1459 hw->fc.current_mode = e1000_fc_tx_pause;
1460 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1461 }
1462 /* For transmitting PAUSE frames ONLY.
1463 *
1464 * LOCAL DEVICE | LINK PARTNER
1465 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1466 *-------|---------|-------|---------|--------------------
1467 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1468 */
1469 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1470 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1471 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1472 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1473 hw->fc.current_mode = e1000_fc_rx_pause;
1474 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1475 } else {
1476 /* Per the IEEE spec, at this point flow control
1477 * should be disabled.
1478 */
1479 hw->fc.current_mode = e1000_fc_none;
1480 DEBUGOUT("Flow Control = NONE.\n");
1481 }
1482
1483 /* Now we call a subroutine to actually force the MAC
1484 * controller to use the correct flow control settings.
1485 */
1486 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1487 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1488 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1489
1490 ret_val = e1000_force_mac_fc_generic(hw);
1491 if (ret_val) {
1492 DEBUGOUT("Error forcing flow control settings\n");
1493 return ret_val;
1494 }
1495 }
1496
1497 return E1000_SUCCESS;
1498}
1499
1500/**
1501 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1502 * @hw: pointer to the HW structure
1503 * @speed: stores the current speed
1504 * @duplex: stores the current duplex
1505 *
1506 * Read the status register for the current speed/duplex and store the current
1507 * speed and duplex for copper connections.
1508 **/
1509s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1510 u16 *duplex)
1511{
1512 u32 status;
1513
1514 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1515
1516 status = E1000_READ_REG(hw, E1000_STATUS);
1517 if (status & E1000_STATUS_SPEED_1000) {
1518 *speed = SPEED_1000;
1519 DEBUGOUT("1000 Mbs, ");
1520 } else if (status & E1000_STATUS_SPEED_100) {
1521 *speed = SPEED_100;
1522 DEBUGOUT("100 Mbs, ");
1523 } else {
1524 *speed = SPEED_10;
1525 DEBUGOUT("10 Mbs, ");
1526 }
1527
1528 if (status & E1000_STATUS_FD) {
1529 *duplex = FULL_DUPLEX;
1530 DEBUGOUT("Full Duplex\n");
1531 } else {
1532 *duplex = HALF_DUPLEX;
1533 DEBUGOUT("Half Duplex\n");
1534 }
1535
1536 return E1000_SUCCESS;
1537}
1538
1539/**
1540 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1541 * @hw: pointer to the HW structure
1542 * @speed: stores the current speed
1543 * @duplex: stores the current duplex
1544 *
1545 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1546 * for fiber/serdes links.
1547 **/
1548s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1549 u16 *speed, u16 *duplex)
1550{
1551 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1552
1553 *speed = SPEED_1000;
1554 *duplex = FULL_DUPLEX;
1555
1556 return E1000_SUCCESS;
1557}
1558
1559/**
1560 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1561 * @hw: pointer to the HW structure
1562 *
1563 * Acquire the HW semaphore to access the PHY or NVM
1564 **/
1565s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1566{
1567 u32 swsm;
1568 s32 timeout = hw->nvm.word_size + 1;
1569 s32 i = 0;
1570
1571 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1572
1573 /* Get the SW semaphore */
1574 while (i < timeout) {
1575 swsm = E1000_READ_REG(hw, E1000_SWSM);
1576 if (!(swsm & E1000_SWSM_SMBI))
1577 break;
1578
1579 usec_delay(50);
1580 i++;
1581 }
1582
1583 if (i == timeout) {
1584 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1585 return -E1000_ERR_NVM;
1586 }
1587
1588 /* Get the FW semaphore. */
1589 for (i = 0; i < timeout; i++) {
1590 swsm = E1000_READ_REG(hw, E1000_SWSM);
1591 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1592
1593 /* Semaphore acquired if bit latched */
1594 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1595 break;
1596
1597 usec_delay(50);
1598 }
1599
1600 if (i == timeout) {
1601 /* Release semaphores */
1602 e1000_put_hw_semaphore_generic(hw);
1603 DEBUGOUT("Driver can't access the NVM\n");
1604 return -E1000_ERR_NVM;
1605 }
1606
1607 return E1000_SUCCESS;
1608}
1609
1610/**
1611 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1612 * @hw: pointer to the HW structure
1613 *
1614 * Release hardware semaphore used to access the PHY or NVM
1615 **/
1616void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1617{
1618 u32 swsm;
1619
1620 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1621
1622 swsm = E1000_READ_REG(hw, E1000_SWSM);
1623
1624 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1625
1626 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1627}
1628
1629/**
1630 * e1000_get_auto_rd_done_generic - Check for auto read completion
1631 * @hw: pointer to the HW structure
1632 *
1633 * Check EEPROM for Auto Read done bit.
1634 **/
1635s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1636{
1637 s32 i = 0;
1638
1639 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1640
1641 while (i < AUTO_READ_DONE_TIMEOUT) {
1642 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1643 break;
1644 msec_delay(1);
1645 i++;
1646 }
1647
1648 if (i == AUTO_READ_DONE_TIMEOUT) {
1649 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1650 return -E1000_ERR_RESET;
1651 }
1652
1653 return E1000_SUCCESS;
1654}
1655
1656/**
1657 * e1000_valid_led_default_generic - Verify a valid default LED config
1658 * @hw: pointer to the HW structure
1659 * @data: pointer to the NVM (EEPROM)
1660 *
1661 * Read the EEPROM for the current default LED configuration. If the
1662 * LED configuration is not valid, set to a valid LED configuration.
1663 **/
1664s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1665{
1666 s32 ret_val;
1667
1668 DEBUGFUNC("e1000_valid_led_default_generic");
1669
1670 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1671 if (ret_val) {
1672 DEBUGOUT("NVM Read Error\n");
1673 return ret_val;
1674 }
1675
1676 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1677 *data = ID_LED_DEFAULT;
1678
1679 return E1000_SUCCESS;
1680}
1681
1682/**
1683 * e1000_id_led_init_generic -
1684 * @hw: pointer to the HW structure
1685 *
1686 **/
1687s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1688{
1689 struct e1000_mac_info *mac = &hw->mac;
1690 s32 ret_val;
1691 const u32 ledctl_mask = 0x000000FF;
1692 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1693 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1694 u16 data, i, temp;
1695 const u16 led_mask = 0x0F;
1696
1697 DEBUGFUNC("e1000_id_led_init_generic");
1698
1699 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1700 if (ret_val)
1701 return ret_val;
1702
1703 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1704 mac->ledctl_mode1 = mac->ledctl_default;
1705 mac->ledctl_mode2 = mac->ledctl_default;
1706
1707 for (i = 0; i < 4; i++) {
1708 temp = (data >> (i << 2)) & led_mask;
1709 switch (temp) {
1710 case ID_LED_ON1_DEF2:
1711 case ID_LED_ON1_ON2:
1712 case ID_LED_ON1_OFF2:
1713 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1714 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1715 break;
1716 case ID_LED_OFF1_DEF2:
1717 case ID_LED_OFF1_ON2:
1718 case ID_LED_OFF1_OFF2:
1719 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1720 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1721 break;
1722 default:
1723 /* Do nothing */
1724 break;
1725 }
1726 switch (temp) {
1727 case ID_LED_DEF1_ON2:
1728 case ID_LED_ON1_ON2:
1729 case ID_LED_OFF1_ON2:
1730 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1731 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1732 break;
1733 case ID_LED_DEF1_OFF2:
1734 case ID_LED_ON1_OFF2:
1735 case ID_LED_OFF1_OFF2:
1736 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1737 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1738 break;
1739 default:
1740 /* Do nothing */
1741 break;
1742 }
1743 }
1744
1745 return E1000_SUCCESS;
1746}
1747
1748/**
1749 * e1000_setup_led_generic - Configures SW controllable LED
1750 * @hw: pointer to the HW structure
1751 *
1752 * This prepares the SW controllable LED for use and saves the current state
1753 * of the LED so it can be later restored.
1754 **/
1755s32 e1000_setup_led_generic(struct e1000_hw *hw)
1756{
1757 u32 ledctl;
1758
1759 DEBUGFUNC("e1000_setup_led_generic");
1760
1761 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1762 return -E1000_ERR_CONFIG;
1763
1764 if (hw->phy.media_type == e1000_media_type_fiber) {
1765 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1766 hw->mac.ledctl_default = ledctl;
1767 /* Turn off LED0 */
1768 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1769 E1000_LEDCTL_LED0_MODE_MASK);
1770 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1771 E1000_LEDCTL_LED0_MODE_SHIFT);
1772 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1773 } else if (hw->phy.media_type == e1000_media_type_copper) {
1774 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1775 }
1776
1777 return E1000_SUCCESS;
1778}
1779
1780/**
1781 * e1000_cleanup_led_generic - Set LED config to default operation
1782 * @hw: pointer to the HW structure
1783 *
1784 * Remove the current LED configuration and set the LED configuration
1785 * to the default value, saved from the EEPROM.
1786 **/
1787s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1788{
1789 DEBUGFUNC("e1000_cleanup_led_generic");
1790
1791 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1792 return E1000_SUCCESS;
1793}
1794
1795/**
1796 * e1000_blink_led_generic - Blink LED
1797 * @hw: pointer to the HW structure
1798 *
1799 * Blink the LEDs which are set to be on.
1800 **/
1801s32 e1000_blink_led_generic(struct e1000_hw *hw)
1802{
1803 u32 ledctl_blink = 0;
1804 u32 i;
1805
1806 DEBUGFUNC("e1000_blink_led_generic");
1807
1808 if (hw->phy.media_type == e1000_media_type_fiber) {
1809 /* always blink LED0 for PCI-E fiber */
1810 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1811 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1812 } else {
1813 /* Set the blink bit for each LED that's "on" (0x0E)
1814 * (or "off" if inverted) in ledctl_mode2. The blink
1815 * logic in hardware only works when mode is set to "on"
1816 * so it must be changed accordingly when the mode is
1817 * "off" and inverted.
1818 */
1819 ledctl_blink = hw->mac.ledctl_mode2;
1820 for (i = 0; i < 32; i += 8) {
1821 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1822 E1000_LEDCTL_LED0_MODE_MASK;
1823 u32 led_default = hw->mac.ledctl_default >> i;
1824
1825 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1826 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1827 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1828 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1829 ledctl_blink &=
1830 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1831 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1832 E1000_LEDCTL_MODE_LED_ON) << i;
1833 }
1834 }
1835 }
1836
1837 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1838
1839 return E1000_SUCCESS;
1840}
1841
1842/**
1843 * e1000_led_on_generic - Turn LED on
1844 * @hw: pointer to the HW structure
1845 *
1846 * Turn LED on.
1847 **/
1848s32 e1000_led_on_generic(struct e1000_hw *hw)
1849{
1850 u32 ctrl;
1851
1852 DEBUGFUNC("e1000_led_on_generic");
1853
1854 switch (hw->phy.media_type) {
1855 case e1000_media_type_fiber:
1856 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1857 ctrl &= ~E1000_CTRL_SWDPIN0;
1858 ctrl |= E1000_CTRL_SWDPIO0;
1859 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1860 break;
1861 case e1000_media_type_copper:
1862 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1863 break;
1864 default:
1865 break;
1866 }
1867
1868 return E1000_SUCCESS;
1869}
1870
1871/**
1872 * e1000_led_off_generic - Turn LED off
1873 * @hw: pointer to the HW structure
1874 *
1875 * Turn LED off.
1876 **/
1877s32 e1000_led_off_generic(struct e1000_hw *hw)
1878{
1879 u32 ctrl;
1880
1881 DEBUGFUNC("e1000_led_off_generic");
1882
1883 switch (hw->phy.media_type) {
1884 case e1000_media_type_fiber:
1885 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1886 ctrl |= E1000_CTRL_SWDPIN0;
1887 ctrl |= E1000_CTRL_SWDPIO0;
1888 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1889 break;
1890 case e1000_media_type_copper:
1891 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1892 break;
1893 default:
1894 break;
1895 }
1896
1897 return E1000_SUCCESS;
1898}
1899
1900/**
1901 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1902 * @hw: pointer to the HW structure
1903 * @no_snoop: bitmap of snoop events
1904 *
1905 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1906 **/
1907void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1908{
1909 u32 gcr;
1910
1911 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1912
1913 if (no_snoop) {
1914 gcr = E1000_READ_REG(hw, E1000_GCR);
1915 gcr &= ~(PCIE_NO_SNOOP_ALL);
1916 gcr |= no_snoop;
1917 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1918 }
1919}
1920
1921/**
1922 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1923 * @hw: pointer to the HW structure
1924 *
1925 * Returns E1000_SUCCESS if successful, else returns -10
1926 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1927 * the master requests to be disabled.
1928 *
1929 * Disables PCI-Express master access and verifies there are no pending
1930 * requests.
1931 **/
1932s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1933{
1934 u32 ctrl;
1935 s32 timeout = MASTER_DISABLE_TIMEOUT;
1936
1937 DEBUGFUNC("e1000_disable_pcie_master_generic");
1938
1939 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1940 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1941 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1942
1943 while (timeout) {
1944 if (!(E1000_READ_REG(hw, E1000_STATUS) &
1945 E1000_STATUS_GIO_MASTER_ENABLE))
1946 break;
1947 usec_delay(100);
1948 timeout--;
1949 }
1950
1951 if (!timeout) {
1952 DEBUGOUT("Master requests are pending.\n");
1953 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1954 }
1955
1956 return E1000_SUCCESS;
1957}
1958
1959/**
1960 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1961 * @hw: pointer to the HW structure
1962 *
1963 * Reset the Adaptive Interframe Spacing throttle to default values.
1964 **/
1965void e1000_reset_adaptive_generic(struct e1000_hw *hw)
1966{
1967 struct e1000_mac_info *mac = &hw->mac;
1968
1969 DEBUGFUNC("e1000_reset_adaptive_generic");
1970
1971 if (!mac->adaptive_ifs) {
1972 DEBUGOUT("Not in Adaptive IFS mode!\n");
1973 return;
1974 }
1975
1976 mac->current_ifs_val = 0;
1977 mac->ifs_min_val = IFS_MIN;
1978 mac->ifs_max_val = IFS_MAX;
1979 mac->ifs_step_size = IFS_STEP;
1980 mac->ifs_ratio = IFS_RATIO;
1981
1982 mac->in_ifs_mode = false;
1983 E1000_WRITE_REG(hw, E1000_AIT, 0);
1984}
1985
1986/**
1987 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
1988 * @hw: pointer to the HW structure
1989 *
1990 * Update the Adaptive Interframe Spacing Throttle value based on the
1991 * time between transmitted packets and time between collisions.
1992 **/
1993void e1000_update_adaptive_generic(struct e1000_hw *hw)
1994{
1995 struct e1000_mac_info *mac = &hw->mac;
1996
1997 DEBUGFUNC("e1000_update_adaptive_generic");
1998
1999 if (!mac->adaptive_ifs) {
2000 DEBUGOUT("Not in Adaptive IFS mode!\n");
2001 return;
2002 }
2003
2004 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2005 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2006 mac->in_ifs_mode = true;
2007 if (mac->current_ifs_val < mac->ifs_max_val) {
2008 if (!mac->current_ifs_val)
2009 mac->current_ifs_val = mac->ifs_min_val;
2010 else
2011 mac->current_ifs_val +=
2012 mac->ifs_step_size;
2013 E1000_WRITE_REG(hw, E1000_AIT,
2014 mac->current_ifs_val);
2015 }
2016 }
2017 } else {
2018 if (mac->in_ifs_mode &&
2019 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2020 mac->current_ifs_val = 0;
2021 mac->in_ifs_mode = false;
2022 E1000_WRITE_REG(hw, E1000_AIT, 0);
2023 }
2024 }
2025}
2026
2027/**
2028 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2029 * @hw: pointer to the HW structure
2030 *
2031 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2032 * set, which is forced to MDI mode only.
2033 **/
2034static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2035{
2036 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2037
2038 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2039 DEBUGOUT("Invalid MDI setting detected\n");
2040 hw->phy.mdix = 1;
2041 return -E1000_ERR_CONFIG;
2042 }
2043
2044 return E1000_SUCCESS;
2045}
2046
2047/**
2048 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2049 * @hw: pointer to the HW structure
2050 *
2051 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2052 * operation.
2053 **/
2054s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2055{
2056 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2057
2058 return E1000_SUCCESS;
2059}
2060
2061/**
2062 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2063 * @hw: pointer to the HW structure
2064 * @reg: 32bit register offset such as E1000_SCTL
2065 * @offset: register offset to write to
2066 * @data: data to write at register offset
2067 *
2068 * Writes an address/data control type register. There are several of these
2069 * and they all have the format address << 8 | data and bit 31 is polled for
2070 * completion.
2071 **/
2072s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2073 u32 offset, u8 data)
2074{
2075 u32 i, regvalue = 0;
2076
2077 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2078
2079 /* Set up the address and data */
2080 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2081 E1000_WRITE_REG(hw, reg, regvalue);
2082
2083 /* Poll the ready bit to see if the MDI read completed */
2084 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2085 usec_delay(5);
2086 regvalue = E1000_READ_REG(hw, reg);
2087 if (regvalue & E1000_GEN_CTL_READY)
2088 break;
2089 }
2090 if (!(regvalue & E1000_GEN_CTL_READY)) {
2091 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2092 return -E1000_ERR_PHY;
2093 }
2094
2095 return E1000_SUCCESS;
2096}
Ceph