[ceph.git] / ceph / src / seastar / dpdk / lib / librte_eal / linuxapp / kni / ethtool / ixgbe / ixgbe_dcb.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2012 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "LICENSE.GPL".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_DCB_H_
#define _IXGBE_DCB_H_


#include "ixgbe_type.h"

/* DCB defines */
/* DCB credit calculation defines */
#define IXGBE_DCB_CREDIT_QUANTUM	64
#define IXGBE_DCB_MAX_CREDIT_REFILL	200   /* 200 * 64B = 12800B */
#define IXGBE_DCB_MAX_TSO_SIZE		(32 * 1024) /* Max TSO pkt size in DCB*/
#define IXGBE_DCB_MAX_CREDIT		(2 * IXGBE_DCB_MAX_CREDIT_REFILL)

/* 513 for 32KB TSO packet */
#define IXGBE_DCB_MIN_TSO_CREDIT	\
	((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)

/* DCB configuration defines */
#define IXGBE_DCB_MAX_USER_PRIORITY	8
#define IXGBE_DCB_MAX_BW_GROUP		8
#define IXGBE_DCB_BW_PERCENT		100

#define IXGBE_DCB_TX_CONFIG		0
#define IXGBE_DCB_RX_CONFIG		1

/* DCB capability defines */
#define IXGBE_DCB_PG_SUPPORT	0x00000001
#define IXGBE_DCB_PFC_SUPPORT	0x00000002
#define IXGBE_DCB_BCN_SUPPORT	0x00000004
#define IXGBE_DCB_UP2TC_SUPPORT	0x00000008
#define IXGBE_DCB_GSP_SUPPORT	0x00000010

struct ixgbe_dcb_support {
	u32 capabilities; /* DCB capabilities */

	/* Each bit represents a number of TCs configurable in the hw.
	 * If 8 traffic classes can be configured, the value is 0x80. */
	u8 traffic_classes;
	u8 pfc_traffic_classes;
};

enum ixgbe_dcb_tsa {
	ixgbe_dcb_tsa_ets = 0,
	ixgbe_dcb_tsa_group_strict_cee,
	ixgbe_dcb_tsa_strict
};

/* Traffic class bandwidth allocation per direction */
struct ixgbe_dcb_tc_path {
	u8 bwg_id; /* Bandwidth Group (BWG) ID */
	u8 bwg_percent; /* % of BWG's bandwidth */
	u8 link_percent; /* % of link bandwidth */
	u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
	u16 data_credits_refill; /* Credit refill amount in 64B granularity */
	u16 data_credits_max; /* Max credits for a configured packet buffer
			       * in 64B granularity.*/
	enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */
};

enum ixgbe_dcb_pfc {
	ixgbe_dcb_pfc_disabled = 0,
	ixgbe_dcb_pfc_enabled,
	ixgbe_dcb_pfc_enabled_txonly,
	ixgbe_dcb_pfc_enabled_rxonly
};

/* Traffic class configuration */
struct ixgbe_dcb_tc_config {
	struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */
	enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */

	u16 desc_credits_max; /* For Tx Descriptor arbitration */
	u8 tc; /* Traffic class (TC) */
};

enum ixgbe_dcb_pba {
	/* PBA[0-7] each use 64KB FIFO */
	ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,
	/* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
	ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED
};

struct ixgbe_dcb_num_tcs {
	u8 pg_tcs;
	u8 pfc_tcs;
};

struct ixgbe_dcb_config {
	struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];
	struct ixgbe_dcb_support support;
	struct ixgbe_dcb_num_tcs num_tcs;
	u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */
	bool pfc_mode_enable;
	bool round_robin_enable;

	enum ixgbe_dcb_pba rx_pba_cfg;

	u32 dcb_cfg_version; /* Not used...OS-specific? */
	u32 link_speed; /* For bandwidth allocation validation purpose */
	bool vt_mode;
};

/* DCB driver APIs */

/* DCB rule checking */
s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);

/* DCB credits calculation */
s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);
s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,
				       struct ixgbe_dcb_config *, u32, u8);

/* DCB PFC */
s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);
s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);

/* DCB stats */
s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);

/* DCB config arbiters */
s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,
					 struct ixgbe_dcb_config *);
s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,
					 struct ixgbe_dcb_config *);
s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,
				    struct ixgbe_dcb_config *);

/* DCB unpack routines */
void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);
void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);
void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);
void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);
void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);
void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);

/* DCB initialization */
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);
s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
#endif /* _IXGBE_DCB_H_ */
Commit	Line	Data
7c673cae FG	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
	4	Copyright(c) 1999 - 2012 Intel Corporation.
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "LICENSE.GPL".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBE_DCB_H_
	29	#define _IXGBE_DCB_H_
	30
	31
	32	#include "ixgbe_type.h"
	33
	34	/* DCB defines */
	35	/* DCB credit calculation defines */
	36	#define IXGBE_DCB_CREDIT_QUANTUM 64
	37	#define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */
	38	#define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/
	39	#define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL)
	40
	41	/* 513 for 32KB TSO packet */
	42	#define IXGBE_DCB_MIN_TSO_CREDIT \
	43	((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)
	44
	45	/* DCB configuration defines */
	46	#define IXGBE_DCB_MAX_USER_PRIORITY 8
	47	#define IXGBE_DCB_MAX_BW_GROUP 8
	48	#define IXGBE_DCB_BW_PERCENT 100
	49
	50	#define IXGBE_DCB_TX_CONFIG 0
	51	#define IXGBE_DCB_RX_CONFIG 1
	52
	53	/* DCB capability defines */
	54	#define IXGBE_DCB_PG_SUPPORT 0x00000001
	55	#define IXGBE_DCB_PFC_SUPPORT 0x00000002
	56	#define IXGBE_DCB_BCN_SUPPORT 0x00000004
	57	#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
	58	#define IXGBE_DCB_GSP_SUPPORT 0x00000010
	59
	60	struct ixgbe_dcb_support {
	61	u32 capabilities; /* DCB capabilities */
	62
	63	/* Each bit represents a number of TCs configurable in the hw.
	64	* If 8 traffic classes can be configured, the value is 0x80. */
65	u8 traffic_classes;
66	u8 pfc_traffic_classes;
67	};
68
69	enum ixgbe_dcb_tsa {
70	ixgbe_dcb_tsa_ets = 0,
71	ixgbe_dcb_tsa_group_strict_cee,
72	ixgbe_dcb_tsa_strict
73	};
74
75	/* Traffic class bandwidth allocation per direction */
76	struct ixgbe_dcb_tc_path {
77	u8 bwg_id; /* Bandwidth Group (BWG) ID */
78	u8 bwg_percent; /* % of BWG's bandwidth */
79	u8 link_percent; /* % of link bandwidth */
80	u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
81	u16 data_credits_refill; /* Credit refill amount in 64B granularity */
82	u16 data_credits_max; /* Max credits for a configured packet buffer
83	* in 64B granularity.*/
84	enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */
85	};
86
87	enum ixgbe_dcb_pfc {
88	ixgbe_dcb_pfc_disabled = 0,
89	ixgbe_dcb_pfc_enabled,
90	ixgbe_dcb_pfc_enabled_txonly,
91	ixgbe_dcb_pfc_enabled_rxonly
92	};
93
94	/* Traffic class configuration */
95	struct ixgbe_dcb_tc_config {
96	struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */
97	enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */
98
99	u16 desc_credits_max; /* For Tx Descriptor arbitration */
100	u8 tc; /* Traffic class (TC) */
101	};
102
103	enum ixgbe_dcb_pba {
104	/* PBA[0-7] each use 64KB FIFO */
105	ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,
106	/* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
107	ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED
108	};
109
110	struct ixgbe_dcb_num_tcs {
111	u8 pg_tcs;
112	u8 pfc_tcs;
113	};
114
115	struct ixgbe_dcb_config {
116	struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];
117	struct ixgbe_dcb_support support;
118	struct ixgbe_dcb_num_tcs num_tcs;
119	u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */
120	bool pfc_mode_enable;
121	bool round_robin_enable;
122
123	enum ixgbe_dcb_pba rx_pba_cfg;
124
125	u32 dcb_cfg_version; /* Not used...OS-specific? */
126	u32 link_speed; /* For bandwidth allocation validation purpose */
127	bool vt_mode;
128	};
129
130	/* DCB driver APIs */
131
132	/* DCB rule checking */
133	s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);
134
135	/* DCB credits calculation */
136	s32 ixgbe_dcb_calculate_tc_credits(u8 , u16 , u16 *, int);
137	s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,
138	struct ixgbe_dcb_config *, u32, u8);
139
140	/* DCB PFC */
141	s32 ixgbe_dcb_config_pfc(struct ixgbe_hw , u8, u8 );
142	s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw , struct ixgbe_dcb_config );
143
144	/* DCB stats */
145	s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
146	s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw , struct ixgbe_hw_stats , u8);
147	s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw , struct ixgbe_hw_stats , u8);
148
149	/* DCB config arbiters */
150	s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,
151	struct ixgbe_dcb_config *);
152	s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,
153	struct ixgbe_dcb_config *);
154	s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,
155	struct ixgbe_dcb_config *);
156
157	/* DCB unpack routines */
158	void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config , u8 , u8 *);
159	void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config , int, u16 );
160	void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config , u16 );
161	void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config , int, u8 );
162	void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config , int, u8 );
163	void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config , int, u8 );
164
165	/* DCB initialization */
166	s32 ixgbe_dcb_hw_config(struct ixgbe_hw , u16 , u16 , u8 , u8 , u8 );
167	s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw , struct ixgbe_dcb_config );
168	#endif /* _IXGBE_DCB_H_ */