[ceph.git] / ceph / src / spdk / dpdk / drivers / common / qat / qat_adf / icp_qat_fw.h

/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
 * Copyright(c) 2015-2018 Intel Corporation
 */
#ifndef _ICP_QAT_FW_H_
#define _ICP_QAT_FW_H_
#include <sys/types.h>
#include "icp_qat_hw.h"

#define QAT_FIELD_SET(flags, val, bitpos, mask) \
{ (flags) = (((flags) & (~((mask) << (bitpos)))) | \
		(((val) & (mask)) << (bitpos))) ; }

#define QAT_FIELD_GET(flags, bitpos, mask) \
	(((flags) >> (bitpos)) & (mask))

#define ICP_QAT_FW_REQ_DEFAULT_SZ 128
#define ICP_QAT_FW_RESP_DEFAULT_SZ 32
#define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
#define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
#define ICP_QAT_FW_NUM_LONGWORDS_1 1
#define ICP_QAT_FW_NUM_LONGWORDS_2 2
#define ICP_QAT_FW_NUM_LONGWORDS_3 3
#define ICP_QAT_FW_NUM_LONGWORDS_4 4
#define ICP_QAT_FW_NUM_LONGWORDS_5 5
#define ICP_QAT_FW_NUM_LONGWORDS_6 6
#define ICP_QAT_FW_NUM_LONGWORDS_7 7
#define ICP_QAT_FW_NUM_LONGWORDS_10 10
#define ICP_QAT_FW_NUM_LONGWORDS_13 13
#define ICP_QAT_FW_NULL_REQ_SERV_ID 1

enum icp_qat_fw_comn_resp_serv_id {
	ICP_QAT_FW_COMN_RESP_SERV_NULL,
	ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
	ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
};

enum icp_qat_fw_comn_request_id {
	ICP_QAT_FW_COMN_REQ_NULL = 0,
	ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
	ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
	ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
	ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
	ICP_QAT_FW_COMN_REQ_DELIMITER
};

struct icp_qat_fw_comn_req_hdr_cd_pars {
	union {
		struct {
			uint64_t content_desc_addr;
			uint16_t content_desc_resrvd1;
			uint8_t content_desc_params_sz;
			uint8_t content_desc_hdr_resrvd2;
			uint32_t content_desc_resrvd3;
		} s;
		struct {
			uint32_t serv_specif_fields[4];
		} s1;
	} u;
};

struct icp_qat_fw_comn_req_mid {
	uint64_t opaque_data;
	uint64_t src_data_addr;
	uint64_t dest_data_addr;
	uint32_t src_length;
	uint32_t dst_length;
};

struct icp_qat_fw_comn_req_cd_ctrl {
	uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
};

struct icp_qat_fw_comn_req_hdr {
	uint8_t resrvd1;
	uint8_t service_cmd_id;
	uint8_t service_type;
	uint8_t hdr_flags;
	uint16_t serv_specif_flags;
	uint16_t comn_req_flags;
};

struct icp_qat_fw_comn_req_rqpars {
	uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
};

struct icp_qat_fw_comn_req {
	struct icp_qat_fw_comn_req_hdr comn_hdr;
	struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
	struct icp_qat_fw_comn_req_mid comn_mid;
	struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
	struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
};

struct icp_qat_fw_comn_error {
	uint8_t xlat_err_code;
	uint8_t cmp_err_code;
};

struct icp_qat_fw_comn_resp_hdr {
	uint8_t resrvd1;
	uint8_t service_id;
	uint8_t response_type;
	uint8_t hdr_flags;
	struct icp_qat_fw_comn_error comn_error;
	uint8_t comn_status;
	uint8_t cmd_id;
};

struct icp_qat_fw_comn_resp {
	struct icp_qat_fw_comn_resp_hdr comn_hdr;
	uint64_t opaque_data;
	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
};

#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1

#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
	icp_qat_fw_comn_req_hdr_t.service_type

#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
	icp_qat_fw_comn_req_hdr_t.service_type = val

#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
	icp_qat_fw_comn_req_hdr_t.service_cmd_id

#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
	icp_qat_fw_comn_req_hdr_t.service_cmd_id = val

#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
	ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)

#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
	QAT_FIELD_GET(hdr_flags, \
		ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
		ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)

#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
	QAT_FIELD_GET(hdr_flags, \
		ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
		ICP_QAT_FW_COMN_CNV_FLAG_MASK)

#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
	ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)

#define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
	QAT_FIELD_GET(hdr_flags, \
	ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
	ICP_QAT_FW_COMN_VALID_FLAG_MASK)

#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
	(hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)

#define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
	QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
	ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
	ICP_QAT_FW_COMN_VALID_FLAG_MASK)

#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
	(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
	 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)

#define QAT_COMN_PTR_TYPE_BITPOS 0
#define QAT_COMN_PTR_TYPE_MASK 0x1
#define QAT_COMN_CD_FLD_TYPE_BITPOS 1
#define QAT_COMN_CD_FLD_TYPE_MASK 0x1
#define QAT_COMN_PTR_TYPE_FLAT 0x0
#define QAT_COMN_PTR_TYPE_SGL 0x1
#define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
#define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1

#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
	((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
	 | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))

#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
	QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)

#define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
	QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
			QAT_COMN_CD_FLD_TYPE_MASK)

#define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
	QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
			QAT_COMN_PTR_TYPE_MASK)

#define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
	QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
			QAT_COMN_CD_FLD_TYPE_MASK)

#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F

#define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
	((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
	>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))

#define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
	{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
	& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
	((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
	 & ICP_QAT_FW_COMN_NEXT_ID_MASK)); }

#define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
	(((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)

#define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
	{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
	& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }

#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val)                       \
	do {                                                                   \
		(next_curr_id) =                                               \
		    (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) |         \
		     (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) &              \
		      ICP_QAT_FW_COMN_NEXT_ID_MASK))                           \
	} while (0)

#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val)                       \
	do {                                                                   \
		(next_curr_id) =                                               \
		    (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) |         \
		     ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK))                   \
	} while (0)

#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1

#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
	QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
	QAT_COMN_RESP_CRYPTO_STATUS_MASK)

#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
	QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
	QAT_COMN_RESP_PKE_STATUS_MASK)

#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
	QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
	QAT_COMN_RESP_CMP_STATUS_MASK)

#define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
	QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
	QAT_COMN_RESP_XLAT_STATUS_MASK)

#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
	QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
	QAT_COMN_RESP_XLT_WA_APPLIED_MASK)

#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
	QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
	QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)

#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
	QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
	QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)

#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
#define ERR_CODE_NO_ERROR 0
#define ERR_CODE_INVALID_BLOCK_TYPE -1
#define ERR_CODE_NO_MATCH_ONES_COMP -2
#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
#define ERR_CODE_INCOMPLETE_LEN -4
#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
#define ERR_CODE_RPT_GT_SPEC_LEN -6
#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
#define ERR_CODE_INV_DIS_CODE_LEN -8
#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
#define ERR_CODE_DIS_TOO_FAR_BACK -10
#define ERR_CODE_OVERFLOW_ERROR -11
#define ERR_CODE_SOFT_ERROR -12
#define ERR_CODE_FATAL_ERROR -13
#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
#define ERR_CODE_HW_INCOMPLETE_FILE -15
#define ERR_CODE_SSM_ERROR -16
#define ERR_CODE_ENDPOINT_ERROR -17
#define ERR_CODE_CNV_ERROR -18
#define ERR_CODE_EMPTY_DYM_BLOCK -19
#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23

enum icp_qat_fw_slice {
	ICP_QAT_FW_SLICE_NULL = 0,
	ICP_QAT_FW_SLICE_CIPHER = 1,
	ICP_QAT_FW_SLICE_AUTH = 2,
	ICP_QAT_FW_SLICE_DRAM_RD = 3,
	ICP_QAT_FW_SLICE_DRAM_WR = 4,
	ICP_QAT_FW_SLICE_COMP = 5,
	ICP_QAT_FW_SLICE_XLAT = 6,
	ICP_QAT_FW_SLICE_DELIMITER
};
#endif
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
11fdf7f2 TL	2	* Copyright(c) 2015-2018 Intel Corporation
7c673cae FG	3	*/
	4	#ifndef _ICP_QAT_FW_H_
	5	#define _ICP_QAT_FW_H_
	6	#include <sys/types.h>
	7	#include "icp_qat_hw.h"
	8
	9	#define QAT_FIELD_SET(flags, val, bitpos, mask) \
	10	{ (flags) = (((flags) & (~((mask) << (bitpos)))) \| \
	11	(((val) & (mask)) << (bitpos))) ; }
	12
	13	#define QAT_FIELD_GET(flags, bitpos, mask) \
	14	(((flags) >> (bitpos)) & (mask))
	15
	16	#define ICP_QAT_FW_REQ_DEFAULT_SZ 128
	17	#define ICP_QAT_FW_RESP_DEFAULT_SZ 32
	18	#define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
	19	#define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
	20	#define ICP_QAT_FW_NUM_LONGWORDS_1 1
	21	#define ICP_QAT_FW_NUM_LONGWORDS_2 2
	22	#define ICP_QAT_FW_NUM_LONGWORDS_3 3
	23	#define ICP_QAT_FW_NUM_LONGWORDS_4 4
	24	#define ICP_QAT_FW_NUM_LONGWORDS_5 5
	25	#define ICP_QAT_FW_NUM_LONGWORDS_6 6
	26	#define ICP_QAT_FW_NUM_LONGWORDS_7 7
	27	#define ICP_QAT_FW_NUM_LONGWORDS_10 10
	28	#define ICP_QAT_FW_NUM_LONGWORDS_13 13
	29	#define ICP_QAT_FW_NULL_REQ_SERV_ID 1
	30
	31	enum icp_qat_fw_comn_resp_serv_id {
	32	ICP_QAT_FW_COMN_RESP_SERV_NULL,
	33	ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
	34	ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
	35	};
	36
	37	enum icp_qat_fw_comn_request_id {
	38	ICP_QAT_FW_COMN_REQ_NULL = 0,
	39	ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
	40	ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
	41	ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
	42	ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
	43	ICP_QAT_FW_COMN_REQ_DELIMITER
	44	};
	45
	46	struct icp_qat_fw_comn_req_hdr_cd_pars {
	47	union {
	48	struct {
	49	uint64_t content_desc_addr;
	50	uint16_t content_desc_resrvd1;
	51	uint8_t content_desc_params_sz;
	52	uint8_t content_desc_hdr_resrvd2;
	53	uint32_t content_desc_resrvd3;
	54	} s;
	55	struct {
	56	uint32_t serv_specif_fields[4];
	57	} s1;
	58	} u;
	59	};
	60
	61	struct icp_qat_fw_comn_req_mid {
	62	uint64_t opaque_data;
	63	uint64_t src_data_addr;
	64	uint64_t dest_data_addr;
	65	uint32_t src_length;
	66	uint32_t dst_length;
67	};
68
69	struct icp_qat_fw_comn_req_cd_ctrl {
70	uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
71	};
72
73	struct icp_qat_fw_comn_req_hdr {
74	uint8_t resrvd1;
75	uint8_t service_cmd_id;
76	uint8_t service_type;
77	uint8_t hdr_flags;
78	uint16_t serv_specif_flags;
79	uint16_t comn_req_flags;
80	};
81
82	struct icp_qat_fw_comn_req_rqpars {
83	uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
84	};
85
86	struct icp_qat_fw_comn_req {
87	struct icp_qat_fw_comn_req_hdr comn_hdr;
88	struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
89	struct icp_qat_fw_comn_req_mid comn_mid;
90	struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
91	struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
92	};
93
94	struct icp_qat_fw_comn_error {
95	uint8_t xlat_err_code;
96	uint8_t cmp_err_code;
97	};
98
99	struct icp_qat_fw_comn_resp_hdr {
100	uint8_t resrvd1;
101	uint8_t service_id;
102	uint8_t response_type;
103	uint8_t hdr_flags;
104	struct icp_qat_fw_comn_error comn_error;
105	uint8_t comn_status;
106	uint8_t cmd_id;
107	};
108
109	struct icp_qat_fw_comn_resp {
110	struct icp_qat_fw_comn_resp_hdr comn_hdr;
111	uint64_t opaque_data;
112	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
113	};
114
115	#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
116	#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
117	#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
118	#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
119	#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
11fdf7f2 TL	120	#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
	121	#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
	122	#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
	123	#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
7c673cae FG	124
	125	#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
	126	icp_qat_fw_comn_req_hdr_t.service_type
	127
	128	#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
	129	icp_qat_fw_comn_req_hdr_t.service_type = val
	130
	131	#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
	132	icp_qat_fw_comn_req_hdr_t.service_cmd_id
	133
	134	#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
	135	icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
	136
	137	#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
	138	ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
	139
11fdf7f2 TL	140	#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
	141	QAT_FIELD_GET(hdr_flags, \
	142	ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
	143	ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
	144
	145	#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
	146	QAT_FIELD_GET(hdr_flags, \
	147	ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
	148	ICP_QAT_FW_COMN_CNV_FLAG_MASK)
	149
7c673cae FG	150	#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
	151	ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
	152
	153	#define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
	154	QAT_FIELD_GET(hdr_flags, \
	155	ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
	156	ICP_QAT_FW_COMN_VALID_FLAG_MASK)
	157
	158	#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
	159	(hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)
	160
	161	#define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
	162	QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
	163	ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
	164	ICP_QAT_FW_COMN_VALID_FLAG_MASK)
	165
	166	#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
	167	(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
	168	ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
	169
	170	#define QAT_COMN_PTR_TYPE_BITPOS 0
	171	#define QAT_COMN_PTR_TYPE_MASK 0x1
	172	#define QAT_COMN_CD_FLD_TYPE_BITPOS 1
	173	#define QAT_COMN_CD_FLD_TYPE_MASK 0x1
	174	#define QAT_COMN_PTR_TYPE_FLAT 0x0
	175	#define QAT_COMN_PTR_TYPE_SGL 0x1
	176	#define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
	177	#define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
	178
	179	#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
	180	((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
	181	\| (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
	182
	183	#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
	184	QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
	185
	186	#define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
	187	QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
	188	QAT_COMN_CD_FLD_TYPE_MASK)
	189
	190	#define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
	191	QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
	192	QAT_COMN_PTR_TYPE_MASK)
	193
	194	#define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
	195	QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
	196	QAT_COMN_CD_FLD_TYPE_MASK)
	197
	198	#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
	199	#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
	200	#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
	201	#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
	202
	203	#define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
	204	((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
	205	>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
	206
	207	#define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
	208	{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
	209	& ICP_QAT_FW_COMN_CURR_ID_MASK) \| \
	210	((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
	211	& ICP_QAT_FW_COMN_NEXT_ID_MASK)); }
	212
	213	#define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
214	(((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)
215
216	#define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
217	{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
218	& ICP_QAT_FW_COMN_NEXT_ID_MASK) \| \
219	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
220
11fdf7f2 TL	221	#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
	222	do { \
	223	(next_curr_id) = \
	224	(((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) \| \
	225	(((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
	226	ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
	227	} while (0)
	228
	229	#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
	230	do { \
	231	(next_curr_id) = \
	232	(((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \| \
	233	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
	234	} while (0)
	235
7c673cae FG	236	#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
7c673cae FG	237	#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
11fdf7f2 TL	238	#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
11fdf7f2 TL	239	#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
7c673cae FG	240	#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
	241	#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
	242	#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
	243	#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
	244	#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
	245	#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
11fdf7f2 TL	246	#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
	247	#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
	248	#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
	249	#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
7c673cae FG	250
	251	#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
	252	QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
	253	QAT_COMN_RESP_CRYPTO_STATUS_MASK)
	254
11fdf7f2 TL	255	#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
	256	QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
	257	QAT_COMN_RESP_PKE_STATUS_MASK)
	258
7c673cae FG	259	#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
	260	QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
	261	QAT_COMN_RESP_CMP_STATUS_MASK)
	262
	263	#define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
	264	QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
	265	QAT_COMN_RESP_XLAT_STATUS_MASK)
	266
11fdf7f2 TL	267	#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
	268	QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
	269	QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
	270
7c673cae FG	271	#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
	272	QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
	273	QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
	274
11fdf7f2 TL	275	#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
	276	QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
	277	QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
	278
7c673cae FG	279	#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
	280	#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
	281	#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
	282	#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
	283	#define ERR_CODE_NO_ERROR 0
	284	#define ERR_CODE_INVALID_BLOCK_TYPE -1
	285	#define ERR_CODE_NO_MATCH_ONES_COMP -2
	286	#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
	287	#define ERR_CODE_INCOMPLETE_LEN -4
	288	#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
	289	#define ERR_CODE_RPT_GT_SPEC_LEN -6
	290	#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
	291	#define ERR_CODE_INV_DIS_CODE_LEN -8
	292	#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
	293	#define ERR_CODE_DIS_TOO_FAR_BACK -10
	294	#define ERR_CODE_OVERFLOW_ERROR -11
	295	#define ERR_CODE_SOFT_ERROR -12
	296	#define ERR_CODE_FATAL_ERROR -13
11fdf7f2 TL	297	#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
	298	#define ERR_CODE_HW_INCOMPLETE_FILE -15
	299	#define ERR_CODE_SSM_ERROR -16
	300	#define ERR_CODE_ENDPOINT_ERROR -17
	301	#define ERR_CODE_CNV_ERROR -18
	302	#define ERR_CODE_EMPTY_DYM_BLOCK -19
	303	#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
	304	#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
	305	#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
	306	#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
7c673cae FG	307
	308	enum icp_qat_fw_slice {
	309	ICP_QAT_FW_SLICE_NULL = 0,
	310	ICP_QAT_FW_SLICE_CIPHER = 1,
	311	ICP_QAT_FW_SLICE_AUTH = 2,
	312	ICP_QAT_FW_SLICE_DRAM_RD = 3,
	313	ICP_QAT_FW_SLICE_DRAM_WR = 4,
	314	ICP_QAT_FW_SLICE_COMP = 5,
	315	ICP_QAT_FW_SLICE_XLAT = 6,
	316	ICP_QAT_FW_SLICE_DELIMITER
	317	};
	318	#endif