[ceph.git] / ceph / src / spdk / dpdk / drivers / crypto / aesni_mb / aesni_mb_pmd_private.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2015-2016 Intel Corporation
 */

#ifndef _AESNI_MB_PMD_PRIVATE_H_
#define _AESNI_MB_PMD_PRIVATE_H_

#include <intel-ipsec-mb.h>

enum aesni_mb_vector_mode {
	RTE_AESNI_MB_NOT_SUPPORTED = 0,
	RTE_AESNI_MB_SSE,
	RTE_AESNI_MB_AVX,
	RTE_AESNI_MB_AVX2,
	RTE_AESNI_MB_AVX512
};

#define CRYPTODEV_NAME_AESNI_MB_PMD	crypto_aesni_mb
/**< AES-NI Multi buffer PMD device name */

/** AESNI_MB PMD LOGTYPE DRIVER */
extern int aesni_mb_logtype_driver;

#define AESNI_MB_LOG(level, fmt, ...)  \
	rte_log(RTE_LOG_ ## level, aesni_mb_logtype_driver,  \
			"%s() line %u: " fmt "\n", __func__, __LINE__,  \
					## __VA_ARGS__)


#define HMAC_IPAD_VALUE			(0x36)
#define HMAC_OPAD_VALUE			(0x5C)

/* Maximum length for digest */
#define DIGEST_LENGTH_MAX 64
static const unsigned auth_blocksize[] = {
		[NULL_HASH]	= 0,
		[MD5]		= 64,
		[SHA1]		= 64,
		[SHA_224]	= 64,
		[SHA_256]	= 64,
		[SHA_384]	= 128,
		[SHA_512]	= 128,
		[AES_XCBC]	= 16,
		[AES_CCM]	= 16,
		[AES_CMAC]	= 16,
		[AES_GMAC]	= 16,
		[PLAIN_SHA1]	= 64,
		[PLAIN_SHA_224]	= 64,
		[PLAIN_SHA_256]	= 64,
		[PLAIN_SHA_384]	= 128,
		[PLAIN_SHA_512]	= 128
};

/**
 * Get the blocksize in bytes for a specified authentication algorithm
 *
 * @Note: this function will not return a valid value for a non-valid
 * authentication algorithm
 */
static inline unsigned
get_auth_algo_blocksize(JOB_HASH_ALG algo)
{
	return auth_blocksize[algo];
}

static const unsigned auth_truncated_digest_byte_lengths[] = {
		[MD5]		= 12,
		[SHA1]		= 12,
		[SHA_224]	= 14,
		[SHA_256]	= 16,
		[SHA_384]	= 24,
		[SHA_512]	= 32,
		[AES_XCBC]	= 12,
		[AES_CMAC]	= 12,
		[AES_CCM]	= 8,
		[NULL_HASH]	= 0,
		[AES_GMAC]	= 16,
		[PLAIN_SHA1]	= 20,
		[PLAIN_SHA_224]	= 28,
		[PLAIN_SHA_256]	= 32,
		[PLAIN_SHA_384]	= 48,
		[PLAIN_SHA_512]	= 64
};

/**
 * Get the IPsec specified truncated length in bytes of the HMAC digest for a
 * specified authentication algorithm
 *
 * @Note: this function will not return a valid value for a non-valid
 * authentication algorithm
 */
static inline unsigned
get_truncated_digest_byte_length(JOB_HASH_ALG algo)
{
	return auth_truncated_digest_byte_lengths[algo];
}

static const unsigned auth_digest_byte_lengths[] = {
		[MD5]		= 16,
		[SHA1]		= 20,
		[SHA_224]	= 28,
		[SHA_256]	= 32,
		[SHA_384]	= 48,
		[SHA_512]	= 64,
		[AES_XCBC]	= 16,
		[AES_CMAC]	= 16,
		[AES_CCM]	= 16,
		[AES_GMAC]	= 12,
		[NULL_HASH]	= 0,
		[PLAIN_SHA1]	= 20,
		[PLAIN_SHA_224]	= 28,
		[PLAIN_SHA_256]	= 32,
		[PLAIN_SHA_384]	= 48,
		[PLAIN_SHA_512]	= 64
	/**< Vector mode dependent pointer table of the multi-buffer APIs */

};

/**
 * Get the full digest size in bytes for a specified authentication algorithm
 * (if available in the Multi-buffer library)
 *
 * @Note: this function will not return a valid value for a non-valid
 * authentication algorithm
 */
static inline unsigned
get_digest_byte_length(JOB_HASH_ALG algo)
{
	return auth_digest_byte_lengths[algo];
}

enum aesni_mb_operation {
	AESNI_MB_OP_HASH_CIPHER,
	AESNI_MB_OP_CIPHER_HASH,
	AESNI_MB_OP_HASH_ONLY,
	AESNI_MB_OP_CIPHER_ONLY,
	AESNI_MB_OP_AEAD_HASH_CIPHER,
	AESNI_MB_OP_AEAD_CIPHER_HASH,
	AESNI_MB_OP_NOT_SUPPORTED
};

/** private data structure for each virtual AESNI device */
struct aesni_mb_private {
	enum aesni_mb_vector_mode vector_mode;
	/**< CPU vector instruction set mode */
	unsigned max_nb_queue_pairs;
	/**< Max number of queue pairs supported by device */
	MB_MGR *mb_mgr;
	/**< Multi-buffer instance */
};

/** AESNI Multi buffer queue pair */
struct aesni_mb_qp {
	uint16_t id;
	/**< Queue Pair Identifier */
	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
	/**< Unique Queue Pair Name */
	MB_MGR *mb_mgr;
	/**< Multi-buffer instance */
	struct rte_ring *ingress_queue;
	/**< Ring for placing operations ready for processing */
	struct rte_mempool *sess_mp;
	/**< Session Mempool */
	struct rte_mempool *sess_mp_priv;
	/**< Session Private Data Mempool */
	struct rte_cryptodev_stats stats;
	/**< Queue pair statistics */
	uint8_t digest_idx;
	/**< Index of the next slot to be used in temp_digests,
	 * to store the digest for a given operation
	 */
	uint8_t temp_digests[MAX_JOBS][DIGEST_LENGTH_MAX];
	/**< Buffers used to store the digest generated
	 * by the driver when verifying a digest provided
	 * by the user (using authentication verify operation)
	 */
} __rte_cache_aligned;

/** AES-NI multi-buffer private session structure */
struct aesni_mb_session {
	JOB_CHAIN_ORDER chain_order;
	struct {
		uint16_t length;
		uint16_t offset;
	} iv;
	/**< IV parameters */

	/** Cipher Parameters */const struct aesni_mb_op_fns *op_fns;
	/**< Vector mode dependent pointer table of the multi-buffer APIs */

	struct {
		/** Cipher direction - encrypt / decrypt */
		JOB_CIPHER_DIRECTION direction;
		/** Cipher mode - CBC / Counter */
		JOB_CIPHER_MODE mode;

		uint64_t key_length_in_bytes;

		union {
			struct {
				uint32_t encode[60] __rte_aligned(16);
				/**< encode key */
				uint32_t decode[60] __rte_aligned(16);
				/**< decode key */
			} expanded_aes_keys;
			struct {
				const void *ks_ptr[3];
				uint64_t key[3][16];
			} exp_3des_keys;

			struct gcm_key_data gcm_key;
		};
		/**< Expanded AES keys - Allocating space to
		 * contain the maximum expanded key size which
		 * is 240 bytes for 256 bit AES, calculate by:
		 * ((key size (bytes)) *
		 * ((number of rounds) + 1))
		 */
	} cipher;

	/** Authentication Parameters */
	struct {
		JOB_HASH_ALG algo; /**< Authentication Algorithm */
		enum rte_crypto_auth_operation operation;
		/**< auth operation generate or verify */
		union {
			struct {
				uint8_t inner[128] __rte_aligned(16);
				/**< inner pad */
				uint8_t outer[128] __rte_aligned(16);
				/**< outer pad */
			} pads;
			/**< HMAC Authentication pads -
			 * allocating space for the maximum pad
			 * size supported which is 128 bytes for
			 * SHA512
			 */

			struct {
			    uint32_t k1_expanded[44] __rte_aligned(16);
			    /**< k1 (expanded key). */
			    uint8_t k2[16] __rte_aligned(16);
			    /**< k2. */
			    uint8_t k3[16] __rte_aligned(16);
			    /**< k3. */
			} xcbc;

			struct {
				uint32_t expkey[60] __rte_aligned(16);
						    /**< k1 (expanded key). */
				uint32_t skey1[4] __rte_aligned(16);
						    /**< k2. */
				uint32_t skey2[4] __rte_aligned(16);
						    /**< k3. */
			} cmac;
			/**< Expanded XCBC authentication keys */
		};
	/** Generated digest size by the Multi-buffer library */
	uint16_t gen_digest_len;
	/** Requested digest size from Cryptodev */
	uint16_t req_digest_len;

	} auth;
	struct {
		/** AAD data length */
		uint16_t aad_len;
	} aead;
} __rte_cache_aligned;

extern int
aesni_mb_set_session_parameters(const MB_MGR *mb_mgr,
		struct aesni_mb_session *sess,
		const struct rte_crypto_sym_xform *xform);

/** device specific operations function pointer structure */
extern struct rte_cryptodev_ops *rte_aesni_mb_pmd_ops;

extern uint32_t
aesni_mb_cpu_crypto_process_bulk(struct rte_cryptodev *dev,
	struct rte_cryptodev_sym_session *sess, union rte_crypto_sym_ofs sofs,
	struct rte_crypto_sym_vec *vec);

#endif /* _AESNI_MB_PMD_PRIVATE_H_ */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
11fdf7f2 TL	2	* Copyright(c) 2015-2016 Intel Corporation
7c673cae FG	3	*/
7c673cae FG	4
f67539c2 TL	5	#ifndef _AESNI_MB_PMD_PRIVATE_H_
f67539c2 TL	6	#define _AESNI_MB_PMD_PRIVATE_H_
7c673cae	7
9f95a23c TL	8	#include <intel-ipsec-mb.h>
	9
	10	enum aesni_mb_vector_mode {
	11	RTE_AESNI_MB_NOT_SUPPORTED = 0,
	12	RTE_AESNI_MB_SSE,
	13	RTE_AESNI_MB_AVX,
	14	RTE_AESNI_MB_AVX2,
	15	RTE_AESNI_MB_AVX512
	16	};
7c673cae	17
11fdf7f2 TL	18	#define CRYPTODEV_NAME_AESNI_MB_PMD crypto_aesni_mb
	19	/*< AES-NI Multi buffer PMD device name /
	20
	21	/** AESNI_MB PMD LOGTYPE DRIVER */
f67539c2	22	extern int aesni_mb_logtype_driver;
11fdf7f2 TL	23
	24	#define AESNI_MB_LOG(level, fmt, ...) \
	25	rte_log(RTE_LOG_ ## level, aesni_mb_logtype_driver, \
	26	"%s() line %u: " fmt "\n", __func__, __LINE__, \
	27	## __VA_ARGS__)
	28
	29
7c673cae FG	30	#define HMAC_IPAD_VALUE (0x36)
	31	#define HMAC_OPAD_VALUE (0x5C)
	32
9f95a23c TL	33	/* Maximum length for digest */
9f95a23c TL	34	#define DIGEST_LENGTH_MAX 64
7c673cae	35	static const unsigned auth_blocksize[] = {
f67539c2	36	[NULL_HASH] = 0,
7c673cae FG	37	[MD5] = 64,
	38	[SHA1] = 64,
	39	[SHA_224] = 64,
	40	[SHA_256] = 64,
	41	[SHA_384] = 128,
	42	[SHA_512] = 128,
	43	[AES_XCBC] = 16,
11fdf7f2	44	[AES_CCM] = 16,
f67539c2 TL	45	[AES_CMAC] = 16,
	46	[AES_GMAC] = 16,
	47	[PLAIN_SHA1] = 64,
	48	[PLAIN_SHA_224] = 64,
	49	[PLAIN_SHA_256] = 64,
	50	[PLAIN_SHA_384] = 128,
	51	[PLAIN_SHA_512] = 128
7c673cae FG	52	};
	53
	54	/**
	55	* Get the blocksize in bytes for a specified authentication algorithm
	56	*
	57	* @Note: this function will not return a valid value for a non-valid
	58	* authentication algorithm
	59	*/
	60	static inline unsigned
	61	get_auth_algo_blocksize(JOB_HASH_ALG algo)
	62	{
	63	return auth_blocksize[algo];
	64	}
	65
	66	static const unsigned auth_truncated_digest_byte_lengths[] = {
	67	[MD5] = 12,
	68	[SHA1] = 12,
	69	[SHA_224] = 14,
	70	[SHA_256] = 16,
	71	[SHA_384] = 24,
	72	[SHA_512] = 32,
	73	[AES_XCBC] = 12,
9f95a23c	74	[AES_CMAC] = 12,
11fdf7f2	75	[AES_CCM] = 8,
f67539c2 TL	76	[NULL_HASH] = 0,
	77	[AES_GMAC] = 16,
	78	[PLAIN_SHA1] = 20,
	79	[PLAIN_SHA_224] = 28,
	80	[PLAIN_SHA_256] = 32,
	81	[PLAIN_SHA_384] = 48,
	82	[PLAIN_SHA_512] = 64
7c673cae FG	83	};
	84
	85	/**
	86	* Get the IPsec specified truncated length in bytes of the HMAC digest for a
	87	* specified authentication algorithm
	88	*
	89	* @Note: this function will not return a valid value for a non-valid
	90	* authentication algorithm
	91	*/
	92	static inline unsigned
	93	get_truncated_digest_byte_length(JOB_HASH_ALG algo)
	94	{
	95	return auth_truncated_digest_byte_lengths[algo];
	96	}
	97
	98	static const unsigned auth_digest_byte_lengths[] = {
	99	[MD5] = 16,
	100	[SHA1] = 20,
	101	[SHA_224] = 28,
	102	[SHA_256] = 32,
	103	[SHA_384] = 48,
	104	[SHA_512] = 64,
	105	[AES_XCBC] = 16,
11fdf7f2	106	[AES_CMAC] = 16,
f67539c2	107	[AES_CCM] = 16,
9f95a23c TL	108	[AES_GMAC] = 12,
	109	[NULL_HASH] = 0,
	110	[PLAIN_SHA1] = 20,
	111	[PLAIN_SHA_224] = 28,
	112	[PLAIN_SHA_256] = 32,
	113	[PLAIN_SHA_384] = 48,
	114	[PLAIN_SHA_512] = 64
	115	/*< Vector mode dependent pointer table of the multi-buffer APIs /
	116
7c673cae FG	117	};
	118
	119	/**
9f95a23c TL	120	* Get the full digest size in bytes for a specified authentication algorithm
9f95a23c TL	121	* (if available in the Multi-buffer library)
7c673cae FG	122	*
	123	* @Note: this function will not return a valid value for a non-valid
	124	* authentication algorithm
	125	*/
	126	static inline unsigned
	127	get_digest_byte_length(JOB_HASH_ALG algo)
	128	{
	129	return auth_digest_byte_lengths[algo];
	130	}
	131
11fdf7f2 TL	132	enum aesni_mb_operation {
	133	AESNI_MB_OP_HASH_CIPHER,
	134	AESNI_MB_OP_CIPHER_HASH,
	135	AESNI_MB_OP_HASH_ONLY,
	136	AESNI_MB_OP_CIPHER_ONLY,
	137	AESNI_MB_OP_AEAD_HASH_CIPHER,
	138	AESNI_MB_OP_AEAD_CIPHER_HASH,
	139	AESNI_MB_OP_NOT_SUPPORTED
	140	};
7c673cae FG	141
	142	/** private data structure for each virtual AESNI device */
	143	struct aesni_mb_private {
	144	enum aesni_mb_vector_mode vector_mode;
	145	/*< CPU vector instruction set mode /
	146	unsigned max_nb_queue_pairs;
	147	/*< Max number of queue pairs supported by device /
9f95a23c TL	148	MB_MGR *mb_mgr;
9f95a23c TL	149	/*< Multi-buffer instance /
7c673cae FG	150	};
	151
	152	/** AESNI Multi buffer queue pair */
	153	struct aesni_mb_qp {
	154	uint16_t id;
	155	/*< Queue Pair Identifier /
11fdf7f2	156	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
7c673cae	157	/*< Unique Queue Pair Name /
9f95a23c	158	MB_MGR *mb_mgr;
7c673cae	159	/*< Multi-buffer instance /
11fdf7f2	160	struct rte_ring *ingress_queue;
9f95a23c	161	/*< Ring for placing operations ready for processing /
7c673cae FG	162	struct rte_mempool *sess_mp;
7c673cae FG	163	/*< Session Mempool /
9f95a23c TL	164	struct rte_mempool *sess_mp_priv;
9f95a23c TL	165	/*< Session Private Data Mempool /
7c673cae FG	166	struct rte_cryptodev_stats stats;
7c673cae FG	167	/*< Queue pair statistics /
11fdf7f2 TL	168	uint8_t digest_idx;
	169	/**< Index of the next slot to be used in temp_digests,
	170	* to store the digest for a given operation
	171	*/
	172	uint8_t temp_digests[MAX_JOBS][DIGEST_LENGTH_MAX];
	173	/**< Buffers used to store the digest generated
	174	* by the driver when verifying a digest provided
	175	* by the user (using authentication verify operation)
	176	*/
7c673cae FG	177	} __rte_cache_aligned;
7c673cae FG	178
7c673cae FG	179	/** AES-NI multi-buffer private session structure */
	180	struct aesni_mb_session {
	181	JOB_CHAIN_ORDER chain_order;
11fdf7f2 TL	182	struct {
	183	uint16_t length;
	184	uint16_t offset;
	185	} iv;
	186	/*< IV parameters /
7c673cae	187
9f95a23c TL	188	/** Cipher Parameters /const struct aesni_mb_op_fns op_fns;
	189	/*< Vector mode dependent pointer table of the multi-buffer APIs /
	190
7c673cae FG	191	struct {
	192	/** Cipher direction - encrypt / decrypt */
	193	JOB_CIPHER_DIRECTION direction;
	194	/** Cipher mode - CBC / Counter */
	195	JOB_CIPHER_MODE mode;
	196
	197	uint64_t key_length_in_bytes;
	198
11fdf7f2 TL	199	union {
	200	struct {
	201	uint32_t encode[60] __rte_aligned(16);
	202	/*< encode key /
	203	uint32_t decode[60] __rte_aligned(16);
	204	/*< decode key /
	205	} expanded_aes_keys;
	206	struct {
	207	const void *ks_ptr[3];
	208	uint64_t key[3][16];
	209	} exp_3des_keys;
9f95a23c TL	210
9f95a23c TL	211	struct gcm_key_data gcm_key;
11fdf7f2	212	};
7c673cae FG	213	/**< Expanded AES keys - Allocating space to
	214	* contain the maximum expanded key size which
	215	* is 240 bytes for 256 bit AES, calculate by:
	216	* ((key size (bytes)) *
	217	* ((number of rounds) + 1))
	218	*/
	219	} cipher;
	220
	221	/** Authentication Parameters */
	222	struct {
	223	JOB_HASH_ALG algo; /*< Authentication Algorithm /
11fdf7f2 TL	224	enum rte_crypto_auth_operation operation;
11fdf7f2 TL	225	/*< auth operation generate or verify /
7c673cae FG	226	union {
	227	struct {
	228	uint8_t inner[128] __rte_aligned(16);
	229	/*< inner pad /
	230	uint8_t outer[128] __rte_aligned(16);
	231	/*< outer pad /
	232	} pads;
	233	/**< HMAC Authentication pads -
	234	* allocating space for the maximum pad
	235	* size supported which is 128 bytes for
	236	* SHA512
	237	*/
	238
	239	struct {
	240	uint32_t k1_expanded[44] __rte_aligned(16);
	241	/*< k1 (expanded key). /
	242	uint8_t k2[16] __rte_aligned(16);
	243	/*< k2. /
	244	uint8_t k3[16] __rte_aligned(16);
	245	/*< k3. /
	246	} xcbc;
11fdf7f2 TL	247
	248	struct {
	249	uint32_t expkey[60] __rte_aligned(16);
	250	/*< k1 (expanded key). /
	251	uint32_t skey1[4] __rte_aligned(16);
	252	/*< k2. /
	253	uint32_t skey2[4] __rte_aligned(16);
	254	/*< k3. /
	255	} cmac;
7c673cae FG	256	/*< Expanded XCBC authentication keys /
7c673cae FG	257	};
9f95a23c TL	258	/** Generated digest size by the Multi-buffer library */
	259	uint16_t gen_digest_len;
	260	/** Requested digest size from Cryptodev */
	261	uint16_t req_digest_len;
11fdf7f2	262
7c673cae	263	} auth;
11fdf7f2 TL	264	struct {
	265	/** AAD data length */
	266	uint16_t aad_len;
	267	} aead;
7c673cae FG	268	} __rte_cache_aligned;
7c673cae FG	269
7c673cae	270	extern int
9f95a23c	271	aesni_mb_set_session_parameters(const MB_MGR *mb_mgr,
7c673cae FG	272	struct aesni_mb_session *sess,
	273	const struct rte_crypto_sym_xform *xform);
	274
7c673cae FG	275	/** device specific operations function pointer structure */
	276	extern struct rte_cryptodev_ops *rte_aesni_mb_pmd_ops;
	277
f67539c2 TL	278	extern uint32_t
	279	aesni_mb_cpu_crypto_process_bulk(struct rte_cryptodev *dev,
	280	struct rte_cryptodev_sym_session *sess, union rte_crypto_sym_ofs sofs,
	281	struct rte_crypto_sym_vec *vec);
7c673cae	282
f67539c2	283	#endif /* _AESNI_MB_PMD_PRIVATE_H_ */