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1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(C) 2019 Marvell International Ltd. | |
3 | */ | |
4 | ||
5 | #ifndef _NITROX_CSR_H_ | |
6 | #define _NITROX_CSR_H_ | |
7 | ||
8 | #include <rte_common.h> | |
9 | #include <rte_io.h> | |
10 | ||
11 | #define CSR_DELAY 30 | |
12 | #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset)) | |
13 | ||
14 | /* NPS packet registers */ | |
15 | #define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060UL + ((_i) * 0x40000UL)) | |
16 | #define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068UL + ((_i) * 0x40000UL)) | |
17 | #define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070UL + ((_i) * 0x40000UL)) | |
18 | #define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080UL + ((_i) * 0x40000UL)) | |
19 | #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078UL + ((_i) * 0x40000UL)) | |
20 | #define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088UL + ((_i) * 0x40000UL)) | |
21 | #define NPS_PKT_SLC_CTLX(_i) (0x10000UL + ((_i) * 0x40000UL)) | |
22 | #define NPS_PKT_SLC_CNTSX(_i) (0x10008UL + ((_i) * 0x40000UL)) | |
23 | #define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010UL + ((_i) * 0x40000UL)) | |
24 | ||
25 | /* AQM Virtual Function Registers */ | |
26 | #define AQMQ_QSZX(_i) (0x20008UL + ((_i) * 0x40000UL)) | |
27 | ||
28 | static inline uint64_t | |
29 | nitrox_read_csr(uint8_t *bar_addr, uint64_t offset) | |
30 | { | |
31 | return rte_read64(bar_addr + offset); | |
32 | } | |
33 | ||
34 | static inline void | |
35 | nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value) | |
36 | { | |
37 | rte_write64(value, (bar_addr + offset)); | |
38 | } | |
39 | ||
40 | #endif /* _NITROX_CSR_H_ */ |