projects / ceph.git / blame
| Commit | Line | Data |
|---|---|---|
| f67539c2 TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
| 2 | * Copyright(C) 2019 Marvell International Ltd. | |
| 3 | */ | |
| 4 | ||
| 5 | #ifndef _NITROX_HAL_H_ | |
| 6 | #define _NITROX_HAL_H_ | |
| 7 | ||
| 8 | #include <rte_cycles.h> | |
| 9 | #include <rte_byteorder.h> | |
| 10 | ||
| 11 | #include "nitrox_csr.h" | |
| 12 | ||
| 13 | union nps_pkt_slc_cnts { | |
| 14 | uint64_t u64; | |
| 15 | struct { | |
| 16 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 17 | uint64_t slc_int : 1; | |
| 18 | uint64_t uns_int : 1; | |
| 19 | uint64_t in_int : 1; | |
| 20 | uint64_t mbox_int : 1; | |
| 21 | uint64_t resend : 1; | |
| 22 | uint64_t raz : 5; | |
| 23 | uint64_t timer : 22; | |
| 24 | uint64_t cnt : 32; | |
| 25 | #else | |
| 26 | uint64_t cnt : 32; | |
| 27 | uint64_t timer : 22; | |
| 28 | uint64_t raz : 5; | |
| 29 | uint64_t resend : 1; | |
| 30 | uint64_t mbox_int : 1; | |
| 31 | uint64_t in_int : 1; | |
| 32 | uint64_t uns_int : 1; | |
| 33 | uint64_t slc_int : 1; | |
| 34 | #endif | |
| 35 | } s; | |
| 36 | }; | |
| 37 | ||
| 38 | union nps_pkt_slc_int_levels { | |
| 39 | uint64_t u64; | |
| 40 | struct { | |
| 41 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 42 | uint64_t bmode : 1; | |
| 43 | uint64_t raz : 9; | |
| 44 | uint64_t timet : 22; | |
| 45 | uint64_t cnt : 32; | |
| 46 | #else | |
| 47 | uint64_t cnt : 32; | |
| 48 | uint64_t timet : 22; | |
| 49 | uint64_t raz : 9; | |
| 50 | uint64_t bmode : 1; | |
| 51 | #endif | |
| 52 | } s; | |
| 53 | }; | |
| 54 | ||
| 55 | union nps_pkt_slc_ctl { | |
| 56 | uint64_t u64; | |
| 57 | struct { | |
| 58 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 59 | uint64_t raz : 61; | |
| 60 | uint64_t rh : 1; | |
| 61 | uint64_t z : 1; | |
| 62 | uint64_t enb : 1; | |
| 63 | #else | |
| 64 | uint64_t enb : 1; | |
| 65 | uint64_t z : 1; | |
| 66 | uint64_t rh : 1; | |
| 67 | uint64_t raz : 61; | |
| 68 | #endif | |
| 69 | } s; | |
| 70 | }; | |
| 71 | ||
| 72 | union nps_pkt_in_instr_ctl { | |
| 73 | uint64_t u64; | |
| 74 | struct { | |
| 75 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 76 | uint64_t raz : 62; | |
| 77 | uint64_t is64b : 1; | |
| 78 | uint64_t enb : 1; | |
| 79 | #else | |
| 80 | uint64_t enb : 1; | |
| 81 | uint64_t is64b : 1; | |
| 82 | uint64_t raz : 62; | |
| 83 | #endif | |
| 84 | } s; | |
| 85 | }; | |
| 86 | ||
| 87 | union nps_pkt_in_instr_rsize { | |
| 88 | uint64_t u64; | |
| 89 | struct { | |
| 90 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 91 | uint64_t raz : 32; | |
| 92 | uint64_t rsize : 32; | |
| 93 | #else | |
| 94 | uint64_t rsize : 32; | |
| 95 | uint64_t raz : 32; | |
| 96 | #endif | |
| 97 | } s; | |
| 98 | }; | |
| 99 | ||
| 100 | union nps_pkt_in_instr_baoff_dbell { | |
| 101 | uint64_t u64; | |
| 102 | struct { | |
| 103 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 104 | uint64_t aoff : 32; | |
| 105 | uint64_t dbell : 32; | |
| 106 | #else | |
| 107 | uint64_t dbell : 32; | |
| 108 | uint64_t aoff : 32; | |
| 109 | #endif | |
| 110 | } s; | |
| 111 | }; | |
| 112 | ||
| 113 | union nps_pkt_in_done_cnts { | |
| 114 | uint64_t u64; | |
| 115 | struct { | |
| 116 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 117 | uint64_t slc_int : 1; | |
| 118 | uint64_t uns_int : 1; | |
| 119 | uint64_t in_int : 1; | |
| 120 | uint64_t mbox_int : 1; | |
| 121 | uint64_t resend : 1; | |
| 122 | uint64_t raz : 27; | |
| 123 | uint64_t cnt : 32; | |
| 124 | #else | |
| 125 | uint64_t cnt : 32; | |
| 126 | uint64_t raz : 27; | |
| 127 | uint64_t resend : 1; | |
| 128 | uint64_t mbox_int : 1; | |
| 129 | uint64_t in_int : 1; | |
| 130 | uint64_t uns_int : 1; | |
| 131 | uint64_t slc_int : 1; | |
| 132 | #endif | |
| 133 | } s; | |
| 134 | }; | |
| 135 | ||
| 136 | union aqmq_qsz { | |
| 137 | uint64_t u64; | |
| 138 | struct { | |
| 139 | #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN | |
| 140 | uint64_t raz : 32; | |
| 141 | uint64_t host_queue_size : 32; | |
| 142 | #else | |
| 143 | uint64_t host_queue_size : 32; | |
| 144 | uint64_t raz : 32; | |
| 145 | #endif | |
| 146 | } s; | |
| 147 | }; | |
| 148 | ||
| 149 | enum nitrox_vf_mode { | |
| 150 | NITROX_MODE_PF = 0x0, | |
| 151 | NITROX_MODE_VF16 = 0x1, | |
| 152 | NITROX_MODE_VF32 = 0x2, | |
| 153 | NITROX_MODE_VF64 = 0x3, | |
| 154 | NITROX_MODE_VF128 = 0x4, | |
| 155 | }; | |
| 156 | ||
| 157 | int vf_get_vf_config_mode(uint8_t *bar_addr); | |
| 158 | int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode); | |
| 159 | void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize, | |
| 160 | phys_addr_t raddr); | |
| 161 | void setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port); | |
| 162 | void nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring); | |
| 163 | void nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port); | |
| 164 | ||
| 165 | #endif /* _NITROX_HAL_H_ */ |