[ceph.git] / ceph / src / spdk / dpdk / drivers / event / octeontx / ssovf_evdev.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2017 Cavium, Inc
 */

#ifndef __SSOVF_EVDEV_H__
#define __SSOVF_EVDEV_H__

#include <rte_event_eth_tx_adapter.h>
#include <rte_eventdev_pmd_vdev.h>
#include <rte_io.h>

#include <octeontx_mbox.h>
#include <octeontx_ethdev.h>

#define EVENTDEV_NAME_OCTEONTX_PMD event_octeontx

#define SSOVF_LOG(level, fmt, args...) \
	rte_log(RTE_LOG_ ## level, otx_logtype_ssovf, \
			"[%s] %s() " fmt "\n", \
			RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args)

#define ssovf_log_info(fmt, ...) SSOVF_LOG(INFO, fmt, ##__VA_ARGS__)
#define ssovf_log_dbg(fmt, ...) SSOVF_LOG(DEBUG, fmt, ##__VA_ARGS__)
#define ssovf_log_err(fmt, ...) SSOVF_LOG(ERR, fmt, ##__VA_ARGS__)
#define ssovf_func_trace ssovf_log_dbg
#define ssovf_log_selftest ssovf_log_info

#define SSO_MAX_VHGRP                     (64)
#define SSO_MAX_VHWS                      (32)

/* SSO VF register offsets */
#define SSO_VHGRP_QCTL                    (0x010ULL)
#define SSO_VHGRP_INT                     (0x100ULL)
#define SSO_VHGRP_INT_W1S                 (0x108ULL)
#define SSO_VHGRP_INT_ENA_W1S             (0x110ULL)
#define SSO_VHGRP_INT_ENA_W1C             (0x118ULL)
#define SSO_VHGRP_INT_THR                 (0x140ULL)
#define SSO_VHGRP_INT_CNT                 (0x180ULL)
#define SSO_VHGRP_XAQ_CNT                 (0x1B0ULL)
#define SSO_VHGRP_AQ_CNT                  (0x1C0ULL)
#define SSO_VHGRP_AQ_THR                  (0x1E0ULL)

/* BAR2 */
#define SSO_VHGRP_OP_ADD_WORK0            (0x00ULL)
#define SSO_VHGRP_OP_ADD_WORK1            (0x08ULL)

/* SSOW VF register offsets (BAR0) */
#define SSOW_VHWS_GRPMSK_CHGX(x)          (0x080ULL | ((x) << 3))
#define SSOW_VHWS_TAG                     (0x300ULL)
#define SSOW_VHWS_WQP                     (0x308ULL)
#define SSOW_VHWS_LINKS                   (0x310ULL)
#define SSOW_VHWS_PENDTAG                 (0x340ULL)
#define SSOW_VHWS_PENDWQP                 (0x348ULL)
#define SSOW_VHWS_SWTP                    (0x400ULL)
#define SSOW_VHWS_OP_ALLOC_WE             (0x410ULL)
#define SSOW_VHWS_OP_UPD_WQP_GRP0         (0x440ULL)
#define SSOW_VHWS_OP_UPD_WQP_GRP1         (0x448ULL)
#define SSOW_VHWS_OP_SWTAG_UNTAG          (0x490ULL)
#define SSOW_VHWS_OP_SWTAG_CLR            (0x820ULL)
#define SSOW_VHWS_OP_DESCHED              (0x860ULL)
#define SSOW_VHWS_OP_DESCHED_NOSCH        (0x870ULL)
#define SSOW_VHWS_OP_SWTAG_DESCHED        (0x8C0ULL)
#define SSOW_VHWS_OP_SWTAG_NOSCHED        (0x8D0ULL)
#define SSOW_VHWS_OP_SWTP_SET             (0xC20ULL)
#define SSOW_VHWS_OP_SWTAG_NORM           (0xC80ULL)
#define SSOW_VHWS_OP_SWTAG_FULL0          (0xCA0UL)
#define SSOW_VHWS_OP_SWTAG_FULL1          (0xCA8ULL)
#define SSOW_VHWS_OP_CLR_NSCHED           (0x10000ULL)
#define SSOW_VHWS_OP_GET_WORK0            (0x80000ULL)
#define SSOW_VHWS_OP_GET_WORK1            (0x80008ULL)

/* Mailbox message constants */
#define SSO_COPROC                        0x2

#define SSO_GETDOMAINCFG                  0x1
#define SSO_IDENTIFY                      0x2
#define SSO_GET_DEV_INFO                  0x3
#define SSO_GET_GETWORK_WAIT              0x4
#define SSO_SET_GETWORK_WAIT              0x5
#define SSO_CONVERT_NS_GETWORK_ITER       0x6
#define SSO_GRP_GET_PRIORITY              0x7
#define SSO_GRP_SET_PRIORITY              0x8

#define SSOVF_SELFTEST_ARG               ("selftest")

/*
 * In Cavium OCTEON TX SoC, all accesses to the device registers are
 * implictly strongly ordered. So, The relaxed version of IO operation is
 * safe to use with out any IO memory barriers.
 */
#define ssovf_read64 rte_read64_relaxed
#define ssovf_write64 rte_write64_relaxed

/* ARM64 specific functions */
#if defined(RTE_ARCH_ARM64)
#define ssovf_load_pair(val0, val1, addr) ({		\
			asm volatile(			\
			"ldp %x[x0], %x[x1], [%x[p1]]"	\
			:[x0]"=r"(val0), [x1]"=r"(val1) \
			:[p1]"r"(addr)			\
			); })

#define ssovf_store_pair(val0, val1, addr) ({		\
			asm volatile(			\
			"stp %x[x0], %x[x1], [%x[p1]]"	\
			::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
			); })
#else /* Un optimized functions for building on non arm64 arch */

#define ssovf_load_pair(val0, val1, addr)		\
do {							\
	val0 = rte_read64(addr);			\
	val1 = rte_read64(((uint8_t *)addr) + 8);	\
} while (0)

#define ssovf_store_pair(val0, val1, addr)		\
do {							\
	rte_write64(val0, addr);			\
	rte_write64(val1, (((uint8_t *)addr) + 8));	\
} while (0)
#endif

struct ssovf_info {
	uint16_t domain; /* Domain id */
	uint8_t total_ssovfs; /* Total sso groups available in domain */
	uint8_t total_ssowvfs;/* Total sso hws available in domain */
};

enum ssovf_type {
	OCTEONTX_SSO_GROUP, /* SSO group vf */
	OCTEONTX_SSO_HWS,  /* SSO hardware workslot vf */
};

struct ssovf_evdev {
	uint8_t max_event_queues;
	uint8_t max_event_ports;
	uint8_t is_timeout_deq;
	uint8_t nb_event_queues;
	uint8_t nb_event_ports;
	uint32_t min_deq_timeout_ns;
	uint32_t max_deq_timeout_ns;
	int32_t max_num_events;
} __rte_cache_aligned;

/* Event port aka HWS */
struct ssows {
	uint8_t cur_tt;
	uint8_t cur_grp;
	uint8_t swtag_req;
	uint8_t *base;
	uint8_t *getwork;
	uint8_t *grps[SSO_MAX_VHGRP];
	uint8_t port;
} __rte_cache_aligned;

static inline struct ssovf_evdev *
ssovf_pmd_priv(const struct rte_eventdev *eventdev)
{
	return eventdev->data->dev_private;
}

extern int otx_logtype_ssovf;

uint16_t ssows_enq(void *port, const struct rte_event *ev);
uint16_t ssows_enq_burst(void *port,
		const struct rte_event ev[], uint16_t nb_events);
uint16_t ssows_enq_new_burst(void *port,
		const struct rte_event ev[], uint16_t nb_events);
uint16_t ssows_enq_fwd_burst(void *port,
		const struct rte_event ev[], uint16_t nb_events);
uint16_t ssows_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks);
uint16_t ssows_deq_burst(void *port, struct rte_event ev[],
		uint16_t nb_events, uint64_t timeout_ticks);
uint16_t ssows_deq_timeout(void *port, struct rte_event *ev,
		uint64_t timeout_ticks);
uint16_t ssows_deq_timeout_burst(void *port, struct rte_event ev[],
		uint16_t nb_events, uint64_t timeout_ticks);

typedef void (*ssows_handle_event_t)(void *arg, struct rte_event ev);
void ssows_flush_events(struct ssows *ws, uint8_t queue_id,
		ssows_handle_event_t fn, void *arg);
void ssows_reset(struct ssows *ws);
uint16_t sso_event_tx_adapter_enqueue(void *port,
		struct rte_event ev[], uint16_t nb_events);
int ssovf_info(struct ssovf_info *info);
void *ssovf_bar(enum ssovf_type, uint8_t id, uint8_t bar);
int test_eventdev_octeontx(void);

#endif /* __SSOVF_EVDEV_H__ */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	* Copyright(c) 2017 Cavium, Inc
	3	*/
	4
	5	#ifndef __SSOVF_EVDEV_H__
	6	#define __SSOVF_EVDEV_H__
	7
9f95a23c	8	#include <rte_event_eth_tx_adapter.h>
11fdf7f2 TL	9	#include <rte_eventdev_pmd_vdev.h>
	10	#include <rte_io.h>
	11
	12	#include <octeontx_mbox.h>
	13	#include <octeontx_ethdev.h>
	14
	15	#define EVENTDEV_NAME_OCTEONTX_PMD event_octeontx
	16
	17	#define SSOVF_LOG(level, fmt, args...) \
	18	rte_log(RTE_LOG_ ## level, otx_logtype_ssovf, \
	19	"[%s] %s() " fmt "\n", \
	20	RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args)
	21
	22	#define ssovf_log_info(fmt, ...) SSOVF_LOG(INFO, fmt, ##__VA_ARGS__)
	23	#define ssovf_log_dbg(fmt, ...) SSOVF_LOG(DEBUG, fmt, ##__VA_ARGS__)
	24	#define ssovf_log_err(fmt, ...) SSOVF_LOG(ERR, fmt, ##__VA_ARGS__)
	25	#define ssovf_func_trace ssovf_log_dbg
	26	#define ssovf_log_selftest ssovf_log_info
	27
	28	#define SSO_MAX_VHGRP (64)
	29	#define SSO_MAX_VHWS (32)
	30
	31	/* SSO VF register offsets */
	32	#define SSO_VHGRP_QCTL (0x010ULL)
	33	#define SSO_VHGRP_INT (0x100ULL)
	34	#define SSO_VHGRP_INT_W1S (0x108ULL)
	35	#define SSO_VHGRP_INT_ENA_W1S (0x110ULL)
	36	#define SSO_VHGRP_INT_ENA_W1C (0x118ULL)
	37	#define SSO_VHGRP_INT_THR (0x140ULL)
	38	#define SSO_VHGRP_INT_CNT (0x180ULL)
	39	#define SSO_VHGRP_XAQ_CNT (0x1B0ULL)
	40	#define SSO_VHGRP_AQ_CNT (0x1C0ULL)
	41	#define SSO_VHGRP_AQ_THR (0x1E0ULL)
	42
	43	/* BAR2 */
	44	#define SSO_VHGRP_OP_ADD_WORK0 (0x00ULL)
	45	#define SSO_VHGRP_OP_ADD_WORK1 (0x08ULL)
	46
	47	/* SSOW VF register offsets (BAR0) */
	48	#define SSOW_VHWS_GRPMSK_CHGX(x) (0x080ULL \| ((x) << 3))
	49	#define SSOW_VHWS_TAG (0x300ULL)
	50	#define SSOW_VHWS_WQP (0x308ULL)
	51	#define SSOW_VHWS_LINKS (0x310ULL)
	52	#define SSOW_VHWS_PENDTAG (0x340ULL)
	53	#define SSOW_VHWS_PENDWQP (0x348ULL)
	54	#define SSOW_VHWS_SWTP (0x400ULL)
	55	#define SSOW_VHWS_OP_ALLOC_WE (0x410ULL)
	56	#define SSOW_VHWS_OP_UPD_WQP_GRP0 (0x440ULL)
	57	#define SSOW_VHWS_OP_UPD_WQP_GRP1 (0x448ULL)
	58	#define SSOW_VHWS_OP_SWTAG_UNTAG (0x490ULL)
	59	#define SSOW_VHWS_OP_SWTAG_CLR (0x820ULL)
	60	#define SSOW_VHWS_OP_DESCHED (0x860ULL)
	61	#define SSOW_VHWS_OP_DESCHED_NOSCH (0x870ULL)
	62	#define SSOW_VHWS_OP_SWTAG_DESCHED (0x8C0ULL)
	63	#define SSOW_VHWS_OP_SWTAG_NOSCHED (0x8D0ULL)
	64	#define SSOW_VHWS_OP_SWTP_SET (0xC20ULL)
	65	#define SSOW_VHWS_OP_SWTAG_NORM (0xC80ULL)
	66	#define SSOW_VHWS_OP_SWTAG_FULL0 (0xCA0UL)
	67	#define SSOW_VHWS_OP_SWTAG_FULL1 (0xCA8ULL)
	68	#define SSOW_VHWS_OP_CLR_NSCHED (0x10000ULL)
	69	#define SSOW_VHWS_OP_GET_WORK0 (0x80000ULL)
	70	#define SSOW_VHWS_OP_GET_WORK1 (0x80008ULL)
	71
	72	/* Mailbox message constants */
73	#define SSO_COPROC 0x2
74
75	#define SSO_GETDOMAINCFG 0x1
76	#define SSO_IDENTIFY 0x2
77	#define SSO_GET_DEV_INFO 0x3
78	#define SSO_GET_GETWORK_WAIT 0x4
79	#define SSO_SET_GETWORK_WAIT 0x5
80	#define SSO_CONVERT_NS_GETWORK_ITER 0x6
81	#define SSO_GRP_GET_PRIORITY 0x7
82	#define SSO_GRP_SET_PRIORITY 0x8
83
84	#define SSOVF_SELFTEST_ARG ("selftest")
85
86	/*
9f95a23c	87	* In Cavium OCTEON TX SoC, all accesses to the device registers are
11fdf7f2 TL	88	* implictly strongly ordered. So, The relaxed version of IO operation is
	89	* safe to use with out any IO memory barriers.
	90	*/
	91	#define ssovf_read64 rte_read64_relaxed
	92	#define ssovf_write64 rte_write64_relaxed
	93
	94	/* ARM64 specific functions */
	95	#if defined(RTE_ARCH_ARM64)
	96	#define ssovf_load_pair(val0, val1, addr) ({ \
	97	asm volatile( \
	98	"ldp %x[x0], %x[x1], [%x[p1]]" \
	99	:[x0]"=r"(val0), [x1]"=r"(val1) \
	100	:[p1]"r"(addr) \
	101	); })
	102
	103	#define ssovf_store_pair(val0, val1, addr) ({ \
	104	asm volatile( \
	105	"stp %x[x0], %x[x1], [%x[p1]]" \
	106	::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
	107	); })
	108	#else /* Un optimized functions for building on non arm64 arch */
	109
	110	#define ssovf_load_pair(val0, val1, addr) \
	111	do { \
	112	val0 = rte_read64(addr); \
	113	val1 = rte_read64(((uint8_t *)addr) + 8); \
	114	} while (0)
	115
	116	#define ssovf_store_pair(val0, val1, addr) \
	117	do { \
	118	rte_write64(val0, addr); \
	119	rte_write64(val1, (((uint8_t *)addr) + 8)); \
	120	} while (0)
	121	#endif
	122
	123	struct ssovf_info {
	124	uint16_t domain; /* Domain id */
	125	uint8_t total_ssovfs; /* Total sso groups available in domain */
	126	uint8_t total_ssowvfs;/* Total sso hws available in domain */
	127	};
	128
	129	enum ssovf_type {
	130	OCTEONTX_SSO_GROUP, /* SSO group vf */
	131	OCTEONTX_SSO_HWS, /* SSO hardware workslot vf */
	132	};
	133
	134	struct ssovf_evdev {
	135	uint8_t max_event_queues;
	136	uint8_t max_event_ports;
	137	uint8_t is_timeout_deq;
	138	uint8_t nb_event_queues;
	139	uint8_t nb_event_ports;
	140	uint32_t min_deq_timeout_ns;
	141	uint32_t max_deq_timeout_ns;
	142	int32_t max_num_events;
	143	} __rte_cache_aligned;
	144
	145	/* Event port aka HWS */
	146	struct ssows {
	147	uint8_t cur_tt;
	148	uint8_t cur_grp;
	149	uint8_t swtag_req;
	150	uint8_t *base;
	151	uint8_t *getwork;
152	uint8_t *grps[SSO_MAX_VHGRP];
153	uint8_t port;
154	} __rte_cache_aligned;
155
156	static inline struct ssovf_evdev *
157	ssovf_pmd_priv(const struct rte_eventdev *eventdev)
158	{
159	return eventdev->data->dev_private;
160	}
161
162	extern int otx_logtype_ssovf;
163
164	uint16_t ssows_enq(void port, const struct rte_event ev);
165	uint16_t ssows_enq_burst(void *port,
166	const struct rte_event ev[], uint16_t nb_events);
167	uint16_t ssows_enq_new_burst(void *port,
168	const struct rte_event ev[], uint16_t nb_events);
169	uint16_t ssows_enq_fwd_burst(void *port,
170	const struct rte_event ev[], uint16_t nb_events);
171	uint16_t ssows_deq(void port, struct rte_event ev, uint64_t timeout_ticks);
172	uint16_t ssows_deq_burst(void *port, struct rte_event ev[],
173	uint16_t nb_events, uint64_t timeout_ticks);
174	uint16_t ssows_deq_timeout(void port, struct rte_event ev,
175	uint64_t timeout_ticks);
176	uint16_t ssows_deq_timeout_burst(void *port, struct rte_event ev[],
177	uint16_t nb_events, uint64_t timeout_ticks);
178
179	typedef void (ssows_handle_event_t)(void arg, struct rte_event ev);
180	void ssows_flush_events(struct ssows *ws, uint8_t queue_id,
181	ssows_handle_event_t fn, void *arg);
182	void ssows_reset(struct ssows *ws);
9f95a23c TL	183	uint16_t sso_event_tx_adapter_enqueue(void *port,
9f95a23c TL	184	struct rte_event ev[], uint16_t nb_events);
11fdf7f2 TL	185	int ssovf_info(struct ssovf_info *info);
	186	void *ssovf_bar(enum ssovf_type, uint8_t id, uint8_t bar);
	187	int test_eventdev_octeontx(void);
	188
	189	#endif /* __SSOVF_EVDEV_H__ */