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1 | /******************************************************************************* |
2 | ||
3 | Copyright (c) 2013 - 2015, Intel Corporation | |
4 | All rights reserved. | |
5 | ||
6 | Redistribution and use in source and binary forms, with or without | |
7 | modification, are permitted provided that the following conditions are met: | |
8 | ||
9 | 1. Redistributions of source code must retain the above copyright notice, | |
10 | this list of conditions and the following disclaimer. | |
11 | ||
12 | 2. Redistributions in binary form must reproduce the above copyright | |
13 | notice, this list of conditions and the following disclaimer in the | |
14 | documentation and/or other materials provided with the distribution. | |
15 | ||
16 | 3. Neither the name of the Intel Corporation nor the names of its | |
17 | contributors may be used to endorse or promote products derived from | |
18 | this software without specific prior written permission. | |
19 | ||
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
30 | POSSIBILITY OF SUCH DAMAGE. | |
31 | ||
32 | ***************************************************************************/ | |
33 | ||
34 | #ifndef _AVF_REGISTER_H_ | |
35 | #define _AVF_REGISTER_H_ | |
36 | ||
37 | ||
38 | #define AVFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ | |
39 | #define AVFMSIX_PBA1_MAX_INDEX 19 | |
40 | #define AVFMSIX_PBA1_PENBIT_SHIFT 0 | |
41 | #define AVFMSIX_PBA1_PENBIT_MASK AVF_MASK(0xFFFFFFFF, AVFMSIX_PBA1_PENBIT_SHIFT) | |
42 | #define AVFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
43 | #define AVFMSIX_TADD1_MAX_INDEX 639 | |
44 | #define AVFMSIX_TADD1_MSIXTADD10_SHIFT 0 | |
45 | #define AVFMSIX_TADD1_MSIXTADD10_MASK AVF_MASK(0x3, AVFMSIX_TADD1_MSIXTADD10_SHIFT) | |
46 | #define AVFMSIX_TADD1_MSIXTADD_SHIFT 2 | |
47 | #define AVFMSIX_TADD1_MSIXTADD_MASK AVF_MASK(0x3FFFFFFF, AVFMSIX_TADD1_MSIXTADD_SHIFT) | |
48 | #define AVFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
49 | #define AVFMSIX_TMSG1_MAX_INDEX 639 | |
50 | #define AVFMSIX_TMSG1_MSIXTMSG_SHIFT 0 | |
51 | #define AVFMSIX_TMSG1_MSIXTMSG_MASK AVF_MASK(0xFFFFFFFF, AVFMSIX_TMSG1_MSIXTMSG_SHIFT) | |
52 | #define AVFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
53 | #define AVFMSIX_TUADD1_MAX_INDEX 639 | |
54 | #define AVFMSIX_TUADD1_MSIXTUADD_SHIFT 0 | |
55 | #define AVFMSIX_TUADD1_MSIXTUADD_MASK AVF_MASK(0xFFFFFFFF, AVFMSIX_TUADD1_MSIXTUADD_SHIFT) | |
56 | #define AVFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
57 | #define AVFMSIX_TVCTRL1_MAX_INDEX 639 | |
58 | #define AVFMSIX_TVCTRL1_MASK_SHIFT 0 | |
59 | #define AVFMSIX_TVCTRL1_MASK_MASK AVF_MASK(0x1, AVFMSIX_TVCTRL1_MASK_SHIFT) | |
60 | #define AVF_ARQBAH1 0x00006000 /* Reset: EMPR */ | |
61 | #define AVF_ARQBAH1_ARQBAH_SHIFT 0 | |
62 | #define AVF_ARQBAH1_ARQBAH_MASK AVF_MASK(0xFFFFFFFF, AVF_ARQBAH1_ARQBAH_SHIFT) | |
63 | #define AVF_ARQBAL1 0x00006C00 /* Reset: EMPR */ | |
64 | #define AVF_ARQBAL1_ARQBAL_SHIFT 0 | |
65 | #define AVF_ARQBAL1_ARQBAL_MASK AVF_MASK(0xFFFFFFFF, AVF_ARQBAL1_ARQBAL_SHIFT) | |
66 | #define AVF_ARQH1 0x00007400 /* Reset: EMPR */ | |
67 | #define AVF_ARQH1_ARQH_SHIFT 0 | |
68 | #define AVF_ARQH1_ARQH_MASK AVF_MASK(0x3FF, AVF_ARQH1_ARQH_SHIFT) | |
69 | #define AVF_ARQLEN1 0x00008000 /* Reset: EMPR */ | |
70 | #define AVF_ARQLEN1_ARQLEN_SHIFT 0 | |
71 | #define AVF_ARQLEN1_ARQLEN_MASK AVF_MASK(0x3FF, AVF_ARQLEN1_ARQLEN_SHIFT) | |
72 | #define AVF_ARQLEN1_ARQVFE_SHIFT 28 | |
73 | #define AVF_ARQLEN1_ARQVFE_MASK AVF_MASK(0x1, AVF_ARQLEN1_ARQVFE_SHIFT) | |
74 | #define AVF_ARQLEN1_ARQOVFL_SHIFT 29 | |
75 | #define AVF_ARQLEN1_ARQOVFL_MASK AVF_MASK(0x1, AVF_ARQLEN1_ARQOVFL_SHIFT) | |
76 | #define AVF_ARQLEN1_ARQCRIT_SHIFT 30 | |
77 | #define AVF_ARQLEN1_ARQCRIT_MASK AVF_MASK(0x1, AVF_ARQLEN1_ARQCRIT_SHIFT) | |
78 | #define AVF_ARQLEN1_ARQENABLE_SHIFT 31 | |
79 | #define AVF_ARQLEN1_ARQENABLE_MASK AVF_MASK(0x1, AVF_ARQLEN1_ARQENABLE_SHIFT) | |
80 | #define AVF_ARQT1 0x00007000 /* Reset: EMPR */ | |
81 | #define AVF_ARQT1_ARQT_SHIFT 0 | |
82 | #define AVF_ARQT1_ARQT_MASK AVF_MASK(0x3FF, AVF_ARQT1_ARQT_SHIFT) | |
83 | #define AVF_ATQBAH1 0x00007800 /* Reset: EMPR */ | |
84 | #define AVF_ATQBAH1_ATQBAH_SHIFT 0 | |
85 | #define AVF_ATQBAH1_ATQBAH_MASK AVF_MASK(0xFFFFFFFF, AVF_ATQBAH1_ATQBAH_SHIFT) | |
86 | #define AVF_ATQBAL1 0x00007C00 /* Reset: EMPR */ | |
87 | #define AVF_ATQBAL1_ATQBAL_SHIFT 0 | |
88 | #define AVF_ATQBAL1_ATQBAL_MASK AVF_MASK(0xFFFFFFFF, AVF_ATQBAL1_ATQBAL_SHIFT) | |
89 | #define AVF_ATQH1 0x00006400 /* Reset: EMPR */ | |
90 | #define AVF_ATQH1_ATQH_SHIFT 0 | |
91 | #define AVF_ATQH1_ATQH_MASK AVF_MASK(0x3FF, AVF_ATQH1_ATQH_SHIFT) | |
92 | #define AVF_ATQLEN1 0x00006800 /* Reset: EMPR */ | |
93 | #define AVF_ATQLEN1_ATQLEN_SHIFT 0 | |
94 | #define AVF_ATQLEN1_ATQLEN_MASK AVF_MASK(0x3FF, AVF_ATQLEN1_ATQLEN_SHIFT) | |
95 | #define AVF_ATQLEN1_ATQVFE_SHIFT 28 | |
96 | #define AVF_ATQLEN1_ATQVFE_MASK AVF_MASK(0x1, AVF_ATQLEN1_ATQVFE_SHIFT) | |
97 | #define AVF_ATQLEN1_ATQOVFL_SHIFT 29 | |
98 | #define AVF_ATQLEN1_ATQOVFL_MASK AVF_MASK(0x1, AVF_ATQLEN1_ATQOVFL_SHIFT) | |
99 | #define AVF_ATQLEN1_ATQCRIT_SHIFT 30 | |
100 | #define AVF_ATQLEN1_ATQCRIT_MASK AVF_MASK(0x1, AVF_ATQLEN1_ATQCRIT_SHIFT) | |
101 | #define AVF_ATQLEN1_ATQENABLE_SHIFT 31 | |
102 | #define AVF_ATQLEN1_ATQENABLE_MASK AVF_MASK(0x1, AVF_ATQLEN1_ATQENABLE_SHIFT) | |
103 | #define AVF_ATQT1 0x00008400 /* Reset: EMPR */ | |
104 | #define AVF_ATQT1_ATQT_SHIFT 0 | |
105 | #define AVF_ATQT1_ATQT_MASK AVF_MASK(0x3FF, AVF_ATQT1_ATQT_SHIFT) | |
106 | #define AVFGEN_RSTAT 0x00008800 /* Reset: VFR */ | |
107 | #define AVFGEN_RSTAT_VFR_STATE_SHIFT 0 | |
108 | #define AVFGEN_RSTAT_VFR_STATE_MASK AVF_MASK(0x3, AVFGEN_RSTAT_VFR_STATE_SHIFT) | |
109 | #define AVFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ | |
110 | #define AVFINT_DYN_CTL01_INTENA_SHIFT 0 | |
111 | #define AVFINT_DYN_CTL01_INTENA_MASK AVF_MASK(0x1, AVFINT_DYN_CTL01_INTENA_SHIFT) | |
112 | #define AVFINT_DYN_CTL01_CLEARPBA_SHIFT 1 | |
113 | #define AVFINT_DYN_CTL01_CLEARPBA_MASK AVF_MASK(0x1, AVFINT_DYN_CTL01_CLEARPBA_SHIFT) | |
114 | #define AVFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 | |
115 | #define AVFINT_DYN_CTL01_SWINT_TRIG_MASK AVF_MASK(0x1, AVFINT_DYN_CTL01_SWINT_TRIG_SHIFT) | |
116 | #define AVFINT_DYN_CTL01_ITR_INDX_SHIFT 3 | |
117 | #define AVFINT_DYN_CTL01_ITR_INDX_MASK AVF_MASK(0x3, AVFINT_DYN_CTL01_ITR_INDX_SHIFT) | |
118 | #define AVFINT_DYN_CTL01_INTERVAL_SHIFT 5 | |
119 | #define AVFINT_DYN_CTL01_INTERVAL_MASK AVF_MASK(0xFFF, AVFINT_DYN_CTL01_INTERVAL_SHIFT) | |
120 | #define AVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 | |
121 | #define AVFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK AVF_MASK(0x1, AVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) | |
122 | #define AVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 | |
123 | #define AVFINT_DYN_CTL01_SW_ITR_INDX_MASK AVF_MASK(0x3, AVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) | |
124 | #define AVFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 | |
125 | #define AVFINT_DYN_CTL01_INTENA_MSK_MASK AVF_MASK(0x1, AVFINT_DYN_CTL01_INTENA_MSK_SHIFT) | |
126 | #define AVFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ | |
127 | #define AVFINT_DYN_CTLN1_MAX_INDEX 15 | |
128 | #define AVFINT_DYN_CTLN1_INTENA_SHIFT 0 | |
129 | #define AVFINT_DYN_CTLN1_INTENA_MASK AVF_MASK(0x1, AVFINT_DYN_CTLN1_INTENA_SHIFT) | |
130 | #define AVFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 | |
131 | #define AVFINT_DYN_CTLN1_CLEARPBA_MASK AVF_MASK(0x1, AVFINT_DYN_CTLN1_CLEARPBA_SHIFT) | |
132 | #define AVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 | |
133 | #define AVFINT_DYN_CTLN1_SWINT_TRIG_MASK AVF_MASK(0x1, AVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) | |
134 | #define AVFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 | |
135 | #define AVFINT_DYN_CTLN1_ITR_INDX_MASK AVF_MASK(0x3, AVFINT_DYN_CTLN1_ITR_INDX_SHIFT) | |
136 | #define AVFINT_DYN_CTLN1_INTERVAL_SHIFT 5 | |
137 | #define AVFINT_DYN_CTLN1_INTERVAL_MASK AVF_MASK(0xFFF, AVFINT_DYN_CTLN1_INTERVAL_SHIFT) | |
138 | #define AVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 | |
139 | #define AVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK AVF_MASK(0x1, AVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) | |
140 | #define AVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 | |
141 | #define AVFINT_DYN_CTLN1_SW_ITR_INDX_MASK AVF_MASK(0x3, AVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) | |
142 | #define AVFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 | |
143 | #define AVFINT_DYN_CTLN1_INTENA_MSK_MASK AVF_MASK(0x1, AVFINT_DYN_CTLN1_INTENA_MSK_SHIFT) | |
144 | #define AVFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ | |
145 | #define AVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 | |
146 | #define AVFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK AVF_MASK(0x1, AVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) | |
147 | #define AVFINT_ICR0_ENA1_ADMINQ_SHIFT 30 | |
148 | #define AVFINT_ICR0_ENA1_ADMINQ_MASK AVF_MASK(0x1, AVFINT_ICR0_ENA1_ADMINQ_SHIFT) | |
149 | #define AVFINT_ICR0_ENA1_RSVD_SHIFT 31 | |
150 | #define AVFINT_ICR0_ENA1_RSVD_MASK AVF_MASK(0x1, AVFINT_ICR0_ENA1_RSVD_SHIFT) | |
151 | #define AVFINT_ICR01 0x00004800 /* Reset: CORER */ | |
152 | #define AVFINT_ICR01_INTEVENT_SHIFT 0 | |
153 | #define AVFINT_ICR01_INTEVENT_MASK AVF_MASK(0x1, AVFINT_ICR01_INTEVENT_SHIFT) | |
154 | #define AVFINT_ICR01_QUEUE_0_SHIFT 1 | |
155 | #define AVFINT_ICR01_QUEUE_0_MASK AVF_MASK(0x1, AVFINT_ICR01_QUEUE_0_SHIFT) | |
156 | #define AVFINT_ICR01_QUEUE_1_SHIFT 2 | |
157 | #define AVFINT_ICR01_QUEUE_1_MASK AVF_MASK(0x1, AVFINT_ICR01_QUEUE_1_SHIFT) | |
158 | #define AVFINT_ICR01_QUEUE_2_SHIFT 3 | |
159 | #define AVFINT_ICR01_QUEUE_2_MASK AVF_MASK(0x1, AVFINT_ICR01_QUEUE_2_SHIFT) | |
160 | #define AVFINT_ICR01_QUEUE_3_SHIFT 4 | |
161 | #define AVFINT_ICR01_QUEUE_3_MASK AVF_MASK(0x1, AVFINT_ICR01_QUEUE_3_SHIFT) | |
162 | #define AVFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 | |
163 | #define AVFINT_ICR01_LINK_STAT_CHANGE_MASK AVF_MASK(0x1, AVFINT_ICR01_LINK_STAT_CHANGE_SHIFT) | |
164 | #define AVFINT_ICR01_ADMINQ_SHIFT 30 | |
165 | #define AVFINT_ICR01_ADMINQ_MASK AVF_MASK(0x1, AVFINT_ICR01_ADMINQ_SHIFT) | |
166 | #define AVFINT_ICR01_SWINT_SHIFT 31 | |
167 | #define AVFINT_ICR01_SWINT_MASK AVF_MASK(0x1, AVFINT_ICR01_SWINT_SHIFT) | |
168 | #define AVFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ | |
169 | #define AVFINT_ITR01_MAX_INDEX 2 | |
170 | #define AVFINT_ITR01_INTERVAL_SHIFT 0 | |
171 | #define AVFINT_ITR01_INTERVAL_MASK AVF_MASK(0xFFF, AVFINT_ITR01_INTERVAL_SHIFT) | |
172 | #define AVFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ | |
173 | #define AVFINT_ITRN1_MAX_INDEX 2 | |
174 | #define AVFINT_ITRN1_INTERVAL_SHIFT 0 | |
175 | #define AVFINT_ITRN1_INTERVAL_MASK AVF_MASK(0xFFF, AVFINT_ITRN1_INTERVAL_SHIFT) | |
176 | #define AVFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ | |
177 | #define AVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 | |
178 | #define AVFINT_STAT_CTL01_OTHER_ITR_INDX_MASK AVF_MASK(0x3, AVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) | |
179 | #define AVF_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ | |
180 | #define AVF_QRX_TAIL1_MAX_INDEX 15 | |
181 | #define AVF_QRX_TAIL1_TAIL_SHIFT 0 | |
182 | #define AVF_QRX_TAIL1_TAIL_MASK AVF_MASK(0x1FFF, AVF_QRX_TAIL1_TAIL_SHIFT) | |
183 | #define AVF_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ | |
184 | #define AVF_QTX_TAIL1_MAX_INDEX 15 | |
185 | #define AVF_QTX_TAIL1_TAIL_SHIFT 0 | |
186 | #define AVF_QTX_TAIL1_TAIL_MASK AVF_MASK(0x1FFF, AVF_QTX_TAIL1_TAIL_SHIFT) | |
187 | #define AVFMSIX_PBA 0x00002000 /* Reset: VFLR */ | |
188 | #define AVFMSIX_PBA_PENBIT_SHIFT 0 | |
189 | #define AVFMSIX_PBA_PENBIT_MASK AVF_MASK(0xFFFFFFFF, AVFMSIX_PBA_PENBIT_SHIFT) | |
190 | #define AVFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
191 | #define AVFMSIX_TADD_MAX_INDEX 16 | |
192 | #define AVFMSIX_TADD_MSIXTADD10_SHIFT 0 | |
193 | #define AVFMSIX_TADD_MSIXTADD10_MASK AVF_MASK(0x3, AVFMSIX_TADD_MSIXTADD10_SHIFT) | |
194 | #define AVFMSIX_TADD_MSIXTADD_SHIFT 2 | |
195 | #define AVFMSIX_TADD_MSIXTADD_MASK AVF_MASK(0x3FFFFFFF, AVFMSIX_TADD_MSIXTADD_SHIFT) | |
196 | #define AVFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
197 | #define AVFMSIX_TMSG_MAX_INDEX 16 | |
198 | #define AVFMSIX_TMSG_MSIXTMSG_SHIFT 0 | |
199 | #define AVFMSIX_TMSG_MSIXTMSG_MASK AVF_MASK(0xFFFFFFFF, AVFMSIX_TMSG_MSIXTMSG_SHIFT) | |
200 | #define AVFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
201 | #define AVFMSIX_TUADD_MAX_INDEX 16 | |
202 | #define AVFMSIX_TUADD_MSIXTUADD_SHIFT 0 | |
203 | #define AVFMSIX_TUADD_MSIXTUADD_MASK AVF_MASK(0xFFFFFFFF, AVFMSIX_TUADD_MSIXTUADD_SHIFT) | |
204 | #define AVFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
205 | #define AVFMSIX_TVCTRL_MAX_INDEX 16 | |
206 | #define AVFMSIX_TVCTRL_MASK_SHIFT 0 | |
207 | #define AVFMSIX_TVCTRL_MASK_MASK AVF_MASK(0x1, AVFMSIX_TVCTRL_MASK_SHIFT) | |
208 | #define AVFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ | |
209 | #define AVFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 | |
210 | #define AVFCM_PE_ERRDATA_ERROR_CODE_MASK AVF_MASK(0xF, AVFCM_PE_ERRDATA_ERROR_CODE_SHIFT) | |
211 | #define AVFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 | |
212 | #define AVFCM_PE_ERRDATA_Q_TYPE_MASK AVF_MASK(0x7, AVFCM_PE_ERRDATA_Q_TYPE_SHIFT) | |
213 | #define AVFCM_PE_ERRDATA_Q_NUM_SHIFT 8 | |
214 | #define AVFCM_PE_ERRDATA_Q_NUM_MASK AVF_MASK(0x3FFFF, AVFCM_PE_ERRDATA_Q_NUM_SHIFT) | |
215 | #define AVFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ | |
216 | #define AVFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 | |
217 | #define AVFCM_PE_ERRINFO_ERROR_VALID_MASK AVF_MASK(0x1, AVFCM_PE_ERRINFO_ERROR_VALID_SHIFT) | |
218 | #define AVFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 | |
219 | #define AVFCM_PE_ERRINFO_ERROR_INST_MASK AVF_MASK(0x7, AVFCM_PE_ERRINFO_ERROR_INST_SHIFT) | |
220 | #define AVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 | |
221 | #define AVFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK AVF_MASK(0xFF, AVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) | |
222 | #define AVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 | |
223 | #define AVFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK AVF_MASK(0xFF, AVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) | |
224 | #define AVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 | |
225 | #define AVFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK AVF_MASK(0xFF, AVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) | |
226 | #define AVFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ | |
227 | #define AVFQF_HENA_MAX_INDEX 1 | |
228 | #define AVFQF_HENA_PTYPE_ENA_SHIFT 0 | |
229 | #define AVFQF_HENA_PTYPE_ENA_MASK AVF_MASK(0xFFFFFFFF, AVFQF_HENA_PTYPE_ENA_SHIFT) | |
230 | #define AVFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ | |
231 | #define AVFQF_HKEY_MAX_INDEX 12 | |
232 | #define AVFQF_HKEY_KEY_0_SHIFT 0 | |
233 | #define AVFQF_HKEY_KEY_0_MASK AVF_MASK(0xFF, AVFQF_HKEY_KEY_0_SHIFT) | |
234 | #define AVFQF_HKEY_KEY_1_SHIFT 8 | |
235 | #define AVFQF_HKEY_KEY_1_MASK AVF_MASK(0xFF, AVFQF_HKEY_KEY_1_SHIFT) | |
236 | #define AVFQF_HKEY_KEY_2_SHIFT 16 | |
237 | #define AVFQF_HKEY_KEY_2_MASK AVF_MASK(0xFF, AVFQF_HKEY_KEY_2_SHIFT) | |
238 | #define AVFQF_HKEY_KEY_3_SHIFT 24 | |
239 | #define AVFQF_HKEY_KEY_3_MASK AVF_MASK(0xFF, AVFQF_HKEY_KEY_3_SHIFT) | |
240 | #define AVFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ | |
241 | #define AVFQF_HLUT_MAX_INDEX 15 | |
242 | #define AVFQF_HLUT_LUT0_SHIFT 0 | |
243 | #define AVFQF_HLUT_LUT0_MASK AVF_MASK(0xF, AVFQF_HLUT_LUT0_SHIFT) | |
244 | #define AVFQF_HLUT_LUT1_SHIFT 8 | |
245 | #define AVFQF_HLUT_LUT1_MASK AVF_MASK(0xF, AVFQF_HLUT_LUT1_SHIFT) | |
246 | #define AVFQF_HLUT_LUT2_SHIFT 16 | |
247 | #define AVFQF_HLUT_LUT2_MASK AVF_MASK(0xF, AVFQF_HLUT_LUT2_SHIFT) | |
248 | #define AVFQF_HLUT_LUT3_SHIFT 24 | |
249 | #define AVFQF_HLUT_LUT3_MASK AVF_MASK(0xF, AVFQF_HLUT_LUT3_SHIFT) | |
250 | #define AVFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ | |
251 | #define AVFQF_HREGION_MAX_INDEX 7 | |
252 | #define AVFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 | |
253 | #define AVFQF_HREGION_OVERRIDE_ENA_0_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_0_SHIFT) | |
254 | #define AVFQF_HREGION_REGION_0_SHIFT 1 | |
255 | #define AVFQF_HREGION_REGION_0_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_0_SHIFT) | |
256 | #define AVFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 | |
257 | #define AVFQF_HREGION_OVERRIDE_ENA_1_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_1_SHIFT) | |
258 | #define AVFQF_HREGION_REGION_1_SHIFT 5 | |
259 | #define AVFQF_HREGION_REGION_1_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_1_SHIFT) | |
260 | #define AVFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 | |
261 | #define AVFQF_HREGION_OVERRIDE_ENA_2_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_2_SHIFT) | |
262 | #define AVFQF_HREGION_REGION_2_SHIFT 9 | |
263 | #define AVFQF_HREGION_REGION_2_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_2_SHIFT) | |
264 | #define AVFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 | |
265 | #define AVFQF_HREGION_OVERRIDE_ENA_3_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_3_SHIFT) | |
266 | #define AVFQF_HREGION_REGION_3_SHIFT 13 | |
267 | #define AVFQF_HREGION_REGION_3_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_3_SHIFT) | |
268 | #define AVFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 | |
269 | #define AVFQF_HREGION_OVERRIDE_ENA_4_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_4_SHIFT) | |
270 | #define AVFQF_HREGION_REGION_4_SHIFT 17 | |
271 | #define AVFQF_HREGION_REGION_4_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_4_SHIFT) | |
272 | #define AVFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 | |
273 | #define AVFQF_HREGION_OVERRIDE_ENA_5_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_5_SHIFT) | |
274 | #define AVFQF_HREGION_REGION_5_SHIFT 21 | |
275 | #define AVFQF_HREGION_REGION_5_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_5_SHIFT) | |
276 | #define AVFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 | |
277 | #define AVFQF_HREGION_OVERRIDE_ENA_6_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_6_SHIFT) | |
278 | #define AVFQF_HREGION_REGION_6_SHIFT 25 | |
279 | #define AVFQF_HREGION_REGION_6_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_6_SHIFT) | |
280 | #define AVFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 | |
281 | #define AVFQF_HREGION_OVERRIDE_ENA_7_MASK AVF_MASK(0x1, AVFQF_HREGION_OVERRIDE_ENA_7_SHIFT) | |
282 | #define AVFQF_HREGION_REGION_7_SHIFT 29 | |
283 | #define AVFQF_HREGION_REGION_7_MASK AVF_MASK(0x7, AVFQF_HREGION_REGION_7_SHIFT) | |
284 | ||
285 | #define AVFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 | |
286 | #define AVFINT_DYN_CTL01_WB_ON_ITR_MASK AVF_MASK(0x1, AVFINT_DYN_CTL01_WB_ON_ITR_SHIFT) | |
287 | #define AVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 | |
288 | #define AVFINT_DYN_CTLN1_WB_ON_ITR_MASK AVF_MASK(0x1, AVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) | |
289 | #define AVFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ | |
290 | #define AVFPE_AEQALLOC1_AECOUNT_SHIFT 0 | |
291 | #define AVFPE_AEQALLOC1_AECOUNT_MASK AVF_MASK(0xFFFFFFFF, AVFPE_AEQALLOC1_AECOUNT_SHIFT) | |
292 | #define AVFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ | |
293 | #define AVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 | |
294 | #define AVFPE_CCQPHIGH1_PECCQPHIGH_MASK AVF_MASK(0xFFFFFFFF, AVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) | |
295 | #define AVFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ | |
296 | #define AVFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 | |
297 | #define AVFPE_CCQPLOW1_PECCQPLOW_MASK AVF_MASK(0xFFFFFFFF, AVFPE_CCQPLOW1_PECCQPLOW_SHIFT) | |
298 | #define AVFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ | |
299 | #define AVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 | |
300 | #define AVFPE_CCQPSTATUS1_CCQP_DONE_MASK AVF_MASK(0x1, AVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) | |
301 | #define AVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 | |
302 | #define AVFPE_CCQPSTATUS1_HMC_PROFILE_MASK AVF_MASK(0x7, AVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) | |
303 | #define AVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 | |
304 | #define AVFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK AVF_MASK(0x3F, AVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) | |
305 | #define AVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 | |
306 | #define AVFPE_CCQPSTATUS1_CCQP_ERR_MASK AVF_MASK(0x1, AVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) | |
307 | #define AVFPE_CQACK1 0x0000B000 /* Reset: VFR */ | |
308 | #define AVFPE_CQACK1_PECQID_SHIFT 0 | |
309 | #define AVFPE_CQACK1_PECQID_MASK AVF_MASK(0x1FFFF, AVFPE_CQACK1_PECQID_SHIFT) | |
310 | #define AVFPE_CQARM1 0x0000B400 /* Reset: VFR */ | |
311 | #define AVFPE_CQARM1_PECQID_SHIFT 0 | |
312 | #define AVFPE_CQARM1_PECQID_MASK AVF_MASK(0x1FFFF, AVFPE_CQARM1_PECQID_SHIFT) | |
313 | #define AVFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ | |
314 | #define AVFPE_CQPDB1_WQHEAD_SHIFT 0 | |
315 | #define AVFPE_CQPDB1_WQHEAD_MASK AVF_MASK(0x7FF, AVFPE_CQPDB1_WQHEAD_SHIFT) | |
316 | #define AVFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ | |
317 | #define AVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 | |
318 | #define AVFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK AVF_MASK(0xFFFF, AVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) | |
319 | #define AVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 | |
320 | #define AVFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK AVF_MASK(0xFFFF, AVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) | |
321 | #define AVFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ | |
322 | #define AVFPE_CQPTAIL1_WQTAIL_SHIFT 0 | |
323 | #define AVFPE_CQPTAIL1_WQTAIL_MASK AVF_MASK(0x7FF, AVFPE_CQPTAIL1_WQTAIL_SHIFT) | |
324 | #define AVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 | |
325 | #define AVFPE_CQPTAIL1_CQP_OP_ERR_MASK AVF_MASK(0x1, AVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) | |
326 | #define AVFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ | |
327 | #define AVFPE_IPCONFIG01_PEIPID_SHIFT 0 | |
328 | #define AVFPE_IPCONFIG01_PEIPID_MASK AVF_MASK(0xFFFF, AVFPE_IPCONFIG01_PEIPID_SHIFT) | |
329 | #define AVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 | |
330 | #define AVFPE_IPCONFIG01_USEENTIREIDRANGE_MASK AVF_MASK(0x1, AVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) | |
331 | #define AVFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ | |
332 | #define AVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 | |
333 | #define AVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK AVF_MASK(0x1F, AVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) | |
334 | #define AVFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ | |
335 | #define AVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 | |
336 | #define AVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK AVF_MASK(0xFFFFFF, AVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) | |
337 | #define AVFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ | |
338 | #define AVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 | |
339 | #define AVFPE_TCPNOWTIMER1_TCP_NOW_MASK AVF_MASK(0xFFFFFFFF, AVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) | |
340 | #define AVFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ | |
341 | #define AVFPE_WQEALLOC1_PEQPID_SHIFT 0 | |
342 | #define AVFPE_WQEALLOC1_PEQPID_MASK AVF_MASK(0x3FFFF, AVFPE_WQEALLOC1_PEQPID_SHIFT) | |
343 | #define AVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 | |
344 | #define AVFPE_WQEALLOC1_WQE_DESC_INDEX_MASK AVF_MASK(0xFFF, AVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) | |
345 | ||
346 | #endif /* _AVF_REGISTER_H_ */ |