[ceph.git] / ceph / src / spdk / dpdk / drivers / net / axgbe / axgbe_ethdev.h

/*   SPDX-License-Identifier: BSD-3-Clause
 *   Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
 *   Copyright(c) 2018 Synopsys, Inc. All rights reserved.
 */

#ifndef RTE_ETH_AXGBE_H_
#define RTE_ETH_AXGBE_H_

#include <rte_mempool.h>
#include <rte_lcore.h>
#include "axgbe_common.h"

#define IRQ				0xff
#define VLAN_HLEN			4

#define AXGBE_TX_MAX_BUF_SIZE		(0x3fff & ~(64 - 1))
#define AXGBE_RX_MAX_BUF_SIZE		(0x3fff & ~(64 - 1))
#define AXGBE_RX_MIN_BUF_SIZE		(RTE_ETHER_MAX_LEN + VLAN_HLEN)
#define AXGBE_MAX_MAC_ADDRS		32
#define AXGBE_MAX_HASH_MAC_ADDRS	256

#define AXGBE_RX_BUF_ALIGN		64

#define AXGBE_MAX_DMA_CHANNELS		16
#define AXGBE_MAX_QUEUES		16
#define AXGBE_PRIORITY_QUEUES		8
#define AXGBE_DMA_STOP_TIMEOUT		1

/* DMA cache settings - Outer sharable, write-back, write-allocate */
#define AXGBE_DMA_OS_AXDOMAIN		0x2
#define AXGBE_DMA_OS_ARCACHE		0xb
#define AXGBE_DMA_OS_AWCACHE		0xf

/* DMA cache settings - System, no caches used */
#define AXGBE_DMA_SYS_AXDOMAIN		0x3
#define AXGBE_DMA_SYS_ARCACHE		0x0
#define AXGBE_DMA_SYS_AWCACHE		0x0

/* DMA channel interrupt modes */
#define AXGBE_IRQ_MODE_EDGE		0
#define AXGBE_IRQ_MODE_LEVEL		1

#define AXGBE_DMA_INTERRUPT_MASK	0x31c7

#define AXGMAC_MIN_PACKET		60
#define AXGMAC_STD_PACKET_MTU		1500
#define AXGMAC_MAX_STD_PACKET		1518
#define AXGMAC_JUMBO_PACKET_MTU		9000
#define AXGMAC_MAX_JUMBO_PACKET		9018
/* Inter-frame gap + preamble */
#define AXGMAC_ETH_PREAMBLE		(12 + 8)

#define AXGMAC_PFC_DATA_LEN		46
#define AXGMAC_PFC_DELAYS		14000

/* PCI BAR mapping */
#define AXGBE_AXGMAC_BAR		0
#define AXGBE_XPCS_BAR			1
#define AXGBE_MAC_PROP_OFFSET		0x1d000
#define AXGBE_I2C_CTRL_OFFSET		0x1e000

/* PCI clock frequencies */
#define AXGBE_V2_DMA_CLOCK_FREQ		500000000
#define AXGBE_V2_PTP_CLOCK_FREQ		125000000

#define AXGMAC_FIFO_MIN_ALLOC		2048
#define AXGMAC_FIFO_UNIT		256
#define AXGMAC_FIFO_ALIGN(_x)                            \
	(((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
#define AXGMAC_FIFO_FC_OFF		2048
#define AXGMAC_FIFO_FC_MIN		4096

#define AXGBE_TC_MIN_QUANTUM		10

/* Flow control queue count */
#define AXGMAC_MAX_FLOW_CONTROL_QUEUES	8

/* Flow control threshold units */
#define AXGMAC_FLOW_CONTROL_UNIT	512
#define AXGMAC_FLOW_CONTROL_ALIGN(_x)				\
	(((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) &		\
	~(AXGMAC_FLOW_CONTROL_UNIT - 1))
#define AXGMAC_FLOW_CONTROL_VALUE(_x)				\
	(((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
#define AXGMAC_FLOW_CONTROL_MAX		33280

/* Maximum MAC address hash table size (256 bits = 8 dword) */
#define AXGBE_MAC_HASH_TABLE_SIZE	8

/* Receive Side Scaling */
#define AXGBE_RSS_OFFLOAD  ( \
	ETH_RSS_IPV4 | \
	ETH_RSS_NONFRAG_IPV4_TCP | \
	ETH_RSS_NONFRAG_IPV4_UDP | \
	ETH_RSS_IPV6 | \
	ETH_RSS_NONFRAG_IPV6_TCP | \
	ETH_RSS_NONFRAG_IPV6_UDP)

#define AXGBE_RSS_HASH_KEY_SIZE		40
#define AXGBE_RSS_MAX_TABLE_SIZE	256
#define AXGBE_RSS_LOOKUP_TABLE_TYPE	0
#define AXGBE_RSS_HASH_KEY_TYPE		1

/* Auto-negotiation */
#define AXGBE_AN_MS_TIMEOUT		500
#define AXGBE_LINK_TIMEOUT		5

#define AXGBE_SGMII_AN_LINK_STATUS	BIT(1)
#define AXGBE_SGMII_AN_LINK_SPEED	(BIT(2) | BIT(3))
#define AXGBE_SGMII_AN_LINK_SPEED_100	0x04
#define AXGBE_SGMII_AN_LINK_SPEED_1000	0x08
#define AXGBE_SGMII_AN_LINK_DUPLEX	BIT(4)

/* ECC correctable error notification window (seconds) */
#define AXGBE_ECC_LIMIT			60

/* MDIO port types */
#define AXGMAC_MAX_C22_PORT		3

/* Helper macro for descriptor handling
 *  Always use AXGBE_GET_DESC_DATA to access the descriptor data
 *  since the index is free-running and needs to be and-ed
 *  with the descriptor count value of the ring to index to
 *  the proper descriptor data.
 */
#define AXGBE_GET_DESC_DATA(_ring, _idx)			\
	((_ring)->rdata +					\
	 ((_idx) & ((_ring)->rdesc_count - 1)))

struct axgbe_port;

enum axgbe_state {
	AXGBE_DOWN,
	AXGBE_LINK_INIT,
	AXGBE_LINK_ERR,
	AXGBE_STOPPED,
};

enum axgbe_int {
	AXGMAC_INT_DMA_CH_SR_TI,
	AXGMAC_INT_DMA_CH_SR_TPS,
	AXGMAC_INT_DMA_CH_SR_TBU,
	AXGMAC_INT_DMA_CH_SR_RI,
	AXGMAC_INT_DMA_CH_SR_RBU,
	AXGMAC_INT_DMA_CH_SR_RPS,
	AXGMAC_INT_DMA_CH_SR_TI_RI,
	AXGMAC_INT_DMA_CH_SR_FBE,
	AXGMAC_INT_DMA_ALL,
};

enum axgbe_int_state {
	AXGMAC_INT_STATE_SAVE,
	AXGMAC_INT_STATE_RESTORE,
};

enum axgbe_ecc_sec {
	AXGBE_ECC_SEC_TX,
	AXGBE_ECC_SEC_RX,
	AXGBE_ECC_SEC_DESC,
};

enum axgbe_speed {
	AXGBE_SPEED_1000 = 0,
	AXGBE_SPEED_2500,
	AXGBE_SPEED_10000,
	AXGBE_SPEEDS,
};

enum axgbe_xpcs_access {
	AXGBE_XPCS_ACCESS_V1 = 0,
	AXGBE_XPCS_ACCESS_V2,
};

enum axgbe_an_mode {
	AXGBE_AN_MODE_CL73 = 0,
	AXGBE_AN_MODE_CL73_REDRV,
	AXGBE_AN_MODE_CL37,
	AXGBE_AN_MODE_CL37_SGMII,
	AXGBE_AN_MODE_NONE,
};

enum axgbe_an {
	AXGBE_AN_READY = 0,
	AXGBE_AN_PAGE_RECEIVED,
	AXGBE_AN_INCOMPAT_LINK,
	AXGBE_AN_COMPLETE,
	AXGBE_AN_NO_LINK,
	AXGBE_AN_ERROR,
};

enum axgbe_rx {
	AXGBE_RX_BPA = 0,
	AXGBE_RX_XNP,
	AXGBE_RX_COMPLETE,
	AXGBE_RX_ERROR,
};

enum axgbe_mode {
	AXGBE_MODE_KX_1000 = 0,
	AXGBE_MODE_KX_2500,
	AXGBE_MODE_KR,
	AXGBE_MODE_X,
	AXGBE_MODE_SGMII_100,
	AXGBE_MODE_SGMII_1000,
	AXGBE_MODE_SFI,
	AXGBE_MODE_UNKNOWN,
};

enum axgbe_speedset {
	AXGBE_SPEEDSET_1000_10000 = 0,
	AXGBE_SPEEDSET_2500_10000,
};

enum axgbe_mdio_mode {
	AXGBE_MDIO_MODE_NONE = 0,
	AXGBE_MDIO_MODE_CL22,
	AXGBE_MDIO_MODE_CL45,
};

struct axgbe_phy {
	uint32_t supported;
	uint32_t advertising;
	uint32_t lp_advertising;

	int address;

	int autoneg;
	int speed;
	int duplex;

	int link;

	int pause_autoneg;
	int tx_pause;
	int rx_pause;
};

enum axgbe_i2c_cmd {
	AXGBE_I2C_CMD_READ = 0,
	AXGBE_I2C_CMD_WRITE,
};

struct axgbe_i2c_op {
	enum axgbe_i2c_cmd cmd;

	unsigned int target;

	uint8_t *buf;
	unsigned int len;
};

struct axgbe_i2c_op_state {
	struct axgbe_i2c_op *op;

	unsigned int tx_len;
	unsigned char *tx_buf;

	unsigned int rx_len;
	unsigned char *rx_buf;

	unsigned int tx_abort_source;

	int ret;
};

struct axgbe_i2c {
	unsigned int started;
	unsigned int max_speed_mode;
	unsigned int rx_fifo_size;
	unsigned int tx_fifo_size;

	struct axgbe_i2c_op_state op_state;
};

struct axgbe_hw_if {
	void (*config_flow_control)(struct axgbe_port *);
	int (*config_rx_mode)(struct axgbe_port *);

	int (*init)(struct axgbe_port *);

	int (*read_mmd_regs)(struct axgbe_port *, int, int);
	void (*write_mmd_regs)(struct axgbe_port *, int, int, int);
	int (*set_speed)(struct axgbe_port *, int);

	int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int,
				enum axgbe_mdio_mode);
	int (*read_ext_mii_regs)(struct axgbe_port *, int, int);
	int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t);

	/* For FLOW ctrl */
	int (*config_tx_flow_control)(struct axgbe_port *);
	int (*config_rx_flow_control)(struct axgbe_port *);

	int (*exit)(struct axgbe_port *);
};

/* This structure represents implementation specific routines for an
 * implementation of a PHY. All routines are required unless noted below.
 *   Optional routines:
 *     kr_training_pre, kr_training_post
 */
struct axgbe_phy_impl_if {
	/* Perform Setup/teardown actions */
	int (*init)(struct axgbe_port *);
	void (*exit)(struct axgbe_port *);

	/* Perform start/stop specific actions */
	int (*reset)(struct axgbe_port *);
	int (*start)(struct axgbe_port *);
	void (*stop)(struct axgbe_port *);

	/* Return the link status */
	int (*link_status)(struct axgbe_port *, int *);

	/* Indicate if a particular speed is valid */
	int (*valid_speed)(struct axgbe_port *, int);

	/* Check if the specified mode can/should be used */
	bool (*use_mode)(struct axgbe_port *, enum axgbe_mode);
	/* Switch the PHY into various modes */
	void (*set_mode)(struct axgbe_port *, enum axgbe_mode);
	/* Retrieve mode needed for a specific speed */
	enum axgbe_mode (*get_mode)(struct axgbe_port *, int);
	/* Retrieve new/next mode when trying to auto-negotiate */
	enum axgbe_mode (*switch_mode)(struct axgbe_port *);
	/* Retrieve current mode */
	enum axgbe_mode (*cur_mode)(struct axgbe_port *);

	/* Retrieve current auto-negotiation mode */
	enum axgbe_an_mode (*an_mode)(struct axgbe_port *);

	/* Configure auto-negotiation settings */
	int (*an_config)(struct axgbe_port *);

	/* Set/override auto-negotiation advertisement settings */
	unsigned int (*an_advertising)(struct axgbe_port *port);

	/* Process results of auto-negotiation */
	enum axgbe_mode (*an_outcome)(struct axgbe_port *);

	/* Pre/Post auto-negotiation support */
	void (*an_pre)(struct axgbe_port *port);
	void (*an_post)(struct axgbe_port *port);

	/* Pre/Post KR training enablement support */
	void (*kr_training_pre)(struct axgbe_port *);
	void (*kr_training_post)(struct axgbe_port *);
};

struct axgbe_phy_if {
	/* For PHY setup/teardown */
	int (*phy_init)(struct axgbe_port *);
	void (*phy_exit)(struct axgbe_port *);

	/* For PHY support when setting device up/down */
	int (*phy_reset)(struct axgbe_port *);
	int (*phy_start)(struct axgbe_port *);
	void (*phy_stop)(struct axgbe_port *);

	/* For PHY support while device is up */
	void (*phy_status)(struct axgbe_port *);
	int (*phy_config_aneg)(struct axgbe_port *);

	/* For PHY settings validation */
	int (*phy_valid_speed)(struct axgbe_port *, int);
	/* For single interrupt support */
	void (*an_isr)(struct axgbe_port *);
	/* PHY implementation specific services */
	struct axgbe_phy_impl_if phy_impl;
};

struct axgbe_i2c_if {
	/* For initial I2C setup */
	int (*i2c_init)(struct axgbe_port *);

	/* For I2C support when setting device up/down */
	int (*i2c_start)(struct axgbe_port *);
	void (*i2c_stop)(struct axgbe_port *);

	/* For performing I2C operations */
	int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *);
};

/* This structure contains flags that indicate what hardware features
 * or configurations are present in the device.
 */
struct axgbe_hw_features {
	/* HW Version */
	unsigned int version;

	/* HW Feature Register0 */
	unsigned int gmii;		/* 1000 Mbps support */
	unsigned int vlhash;		/* VLAN Hash Filter */
	unsigned int sma;		/* SMA(MDIO) Interface */
	unsigned int rwk;		/* PMT remote wake-up packet */
	unsigned int mgk;		/* PMT magic packet */
	unsigned int mmc;		/* RMON module */
	unsigned int aoe;		/* ARP Offload */
	unsigned int ts;		/* IEEE 1588-2008 Advanced Timestamp */
	unsigned int eee;		/* Energy Efficient Ethernet */
	unsigned int tx_coe;		/* Tx Checksum Offload */
	unsigned int rx_coe;		/* Rx Checksum Offload */
	unsigned int addn_mac;		/* Additional MAC Addresses */
	unsigned int ts_src;		/* Timestamp Source */
	unsigned int sa_vlan_ins;	/* Source Address or VLAN Insertion */

	/* HW Feature Register1 */
	unsigned int rx_fifo_size;	/* MTL Receive FIFO Size */
	unsigned int tx_fifo_size;	/* MTL Transmit FIFO Size */
	unsigned int adv_ts_hi;		/* Advance Timestamping High Word */
	unsigned int dma_width;		/* DMA width */
	unsigned int dcb;		/* DCB Feature */
	unsigned int sph;		/* Split Header Feature */
	unsigned int tso;		/* TCP Segmentation Offload */
	unsigned int dma_debug;		/* DMA Debug Registers */
	unsigned int rss;		/* Receive Side Scaling */
	unsigned int tc_cnt;		/* Number of Traffic Classes */
	unsigned int hash_table_size;	/* Hash Table Size */
	unsigned int l3l4_filter_num;	/* Number of L3-L4 Filters */

	/* HW Feature Register2 */
	unsigned int rx_q_cnt;		/* Number of MTL Receive Queues */
	unsigned int tx_q_cnt;		/* Number of MTL Transmit Queues */
	unsigned int rx_ch_cnt;		/* Number of DMA Receive Channels */
	unsigned int tx_ch_cnt;		/* Number of DMA Transmit Channels */
	unsigned int pps_out_num;	/* Number of PPS outputs */
	unsigned int aux_snap_num;	/* Number of Aux snapshot inputs */
};

struct axgbe_version_data {
	void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *);
	enum axgbe_xpcs_access xpcs_access;
	unsigned int mmc_64bit;
	unsigned int tx_max_fifo_size;
	unsigned int rx_max_fifo_size;
	unsigned int tx_tstamp_workaround;
	unsigned int ecc_support;
	unsigned int i2c_support;
	unsigned int an_cdr_workaround;
};

struct axgbe_mmc_stats {
	/* Tx Stats */
	uint64_t txoctetcount_gb;
	uint64_t txframecount_gb;
	uint64_t txbroadcastframes_g;
	uint64_t txmulticastframes_g;
	uint64_t tx64octets_gb;
	uint64_t tx65to127octets_gb;
	uint64_t tx128to255octets_gb;
	uint64_t tx256to511octets_gb;
	uint64_t tx512to1023octets_gb;
	uint64_t tx1024tomaxoctets_gb;
	uint64_t txunicastframes_gb;
	uint64_t txmulticastframes_gb;
	uint64_t txbroadcastframes_gb;
	uint64_t txunderflowerror;
	uint64_t txoctetcount_g;
	uint64_t txframecount_g;
	uint64_t txpauseframes;
	uint64_t txvlanframes_g;

	/* Rx Stats */
	uint64_t rxframecount_gb;
	uint64_t rxoctetcount_gb;
	uint64_t rxoctetcount_g;
	uint64_t rxbroadcastframes_g;
	uint64_t rxmulticastframes_g;
	uint64_t rxcrcerror;
	uint64_t rxrunterror;
	uint64_t rxjabbererror;
	uint64_t rxundersize_g;
	uint64_t rxoversize_g;
	uint64_t rx64octets_gb;
	uint64_t rx65to127octets_gb;
	uint64_t rx128to255octets_gb;
	uint64_t rx256to511octets_gb;
	uint64_t rx512to1023octets_gb;
	uint64_t rx1024tomaxoctets_gb;
	uint64_t rxunicastframes_g;
	uint64_t rxlengtherror;
	uint64_t rxoutofrangetype;
	uint64_t rxpauseframes;
	uint64_t rxfifooverflow;
	uint64_t rxvlanframes_gb;
	uint64_t rxwatchdogerror;
};

/* Flow control parameters */
struct xgbe_fc_info {
	uint32_t high_water[AXGBE_PRIORITY_QUEUES];
	uint32_t low_water[AXGBE_PRIORITY_QUEUES];
	uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
	uint16_t send_xon;
	enum rte_eth_fc_mode mode;
	uint8_t autoneg;
};

/*
 * Structure to store private data for each port.
 */
struct axgbe_port {
	/*  Ethdev where port belongs*/
	struct rte_eth_dev *eth_dev;
	/* Pci dev info */
	const struct rte_pci_device *pci_dev;
	/* Version related data */
	struct axgbe_version_data *vdata;

	/* AXGMAC/XPCS related mmio registers */
	void *xgmac_regs;	/* AXGMAC CSRs */
	void *xpcs_regs;	/* XPCS MMD registers */
	void *xprop_regs;	/* AXGBE property registers */
	void *xi2c_regs;	/* AXGBE I2C CSRs */

	bool cdr_track_early;
	/* XPCS indirect addressing lock */
	unsigned int xpcs_window_def_reg;
	unsigned int xpcs_window_sel_reg;
	unsigned int xpcs_window;
	unsigned int xpcs_window_size;
	unsigned int xpcs_window_mask;

	/* Flags representing axgbe_state */
	unsigned long dev_state;

	struct axgbe_hw_if hw_if;
	struct axgbe_phy_if phy_if;
	struct axgbe_i2c_if i2c_if;

	/* AXI DMA settings */
	unsigned int coherent;
	unsigned int axdomain;
	unsigned int arcache;
	unsigned int awcache;

	unsigned int tx_max_channel_count;
	unsigned int rx_max_channel_count;
	unsigned int channel_count;
	unsigned int tx_ring_count;
	unsigned int tx_desc_count;
	unsigned int rx_ring_count;
	unsigned int rx_desc_count;

	unsigned int tx_max_q_count;
	unsigned int rx_max_q_count;
	unsigned int tx_q_count;
	unsigned int rx_q_count;

	/* Tx/Rx common settings */
	unsigned int pblx8;

	/* Tx settings */
	unsigned int tx_sf_mode;
	unsigned int tx_threshold;
	unsigned int tx_pbl;
	unsigned int tx_osp_mode;
	unsigned int tx_max_fifo_size;

	/* Rx settings */
	unsigned int rx_sf_mode;
	unsigned int rx_threshold;
	unsigned int rx_pbl;
	unsigned int rx_max_fifo_size;
	unsigned int rx_buf_size;

	/* Device clocks */
	unsigned long sysclk_rate;
	unsigned long ptpclk_rate;

	/* Keeps track of power mode */
	unsigned int power_down;

	/* Current PHY settings */
	int phy_link;
	int phy_speed;

	pthread_mutex_t xpcs_mutex;
	pthread_mutex_t i2c_mutex;
	pthread_mutex_t an_mutex;
	pthread_mutex_t phy_mutex;

	/* Flow control settings */
	unsigned int pause_autoneg;
	unsigned int tx_pause;
	unsigned int rx_pause;
	unsigned int rx_rfa[AXGBE_MAX_QUEUES];
	unsigned int rx_rfd[AXGBE_MAX_QUEUES];
	unsigned int fifo;
	unsigned int pfc_map[AXGBE_MAX_QUEUES];

	/* Receive Side Scaling settings */
	u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
	uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
	uint32_t rss_options;
	int rss_enable;

	/* Hardware features of the device */
	struct axgbe_hw_features hw_feat;

	struct rte_ether_addr mac_addr;

	/* Software Tx/Rx structure pointers*/
	void **rx_queues;
	void **tx_queues;

	/* MDIO/PHY related settings */
	unsigned int phy_started;
	void *phy_data;
	struct axgbe_phy phy;
	int mdio_mmd;
	unsigned long link_check;
	volatile int mdio_completion;

	unsigned int kr_redrv;

	/* Auto-negotiation atate machine support */
	unsigned int an_int;
	unsigned int an_status;
	enum axgbe_an an_result;
	enum axgbe_an an_state;
	enum axgbe_rx kr_state;
	enum axgbe_rx kx_state;
	unsigned int an_supported;
	unsigned int parallel_detect;
	unsigned int fec_ability;
	unsigned long an_start;
	enum axgbe_an_mode an_mode;

	/* I2C support */
	struct axgbe_i2c i2c;
	volatile int i2c_complete;

	/* CRC stripping by H/w for Rx packet*/
	int crc_strip_enable;
	/* csum enable to hardware */
	uint32_t rx_csum_enable;

	struct axgbe_mmc_stats mmc_stats;
	struct xgbe_fc_info fc;

	/* Hash filtering */
	unsigned int hash_table_shift;
	unsigned int hash_table_count;
	unsigned int uc_hash_mac_addr;
	unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
};

void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr,
			     uint32_t index);
void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add);

#endif /* RTE_ETH_AXGBE_H_ */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
	3	* Copyright(c) 2018 Synopsys, Inc. All rights reserved.
	4	*/
	5
	6	#ifndef RTE_ETH_AXGBE_H_
	7	#define RTE_ETH_AXGBE_H_
	8
	9	#include <rte_mempool.h>
	10	#include <rte_lcore.h>
	11	#include "axgbe_common.h"
	12
	13	#define IRQ 0xff
	14	#define VLAN_HLEN 4
	15
	16	#define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
	17	#define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
f67539c2 TL	18	#define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN)
	19	#define AXGBE_MAX_MAC_ADDRS 32
	20	#define AXGBE_MAX_HASH_MAC_ADDRS 256
11fdf7f2 TL	21
	22	#define AXGBE_RX_BUF_ALIGN 64
	23
	24	#define AXGBE_MAX_DMA_CHANNELS 16
	25	#define AXGBE_MAX_QUEUES 16
	26	#define AXGBE_PRIORITY_QUEUES 8
	27	#define AXGBE_DMA_STOP_TIMEOUT 1
	28
	29	/* DMA cache settings - Outer sharable, write-back, write-allocate */
	30	#define AXGBE_DMA_OS_AXDOMAIN 0x2
	31	#define AXGBE_DMA_OS_ARCACHE 0xb
	32	#define AXGBE_DMA_OS_AWCACHE 0xf
	33
	34	/* DMA cache settings - System, no caches used */
	35	#define AXGBE_DMA_SYS_AXDOMAIN 0x3
	36	#define AXGBE_DMA_SYS_ARCACHE 0x0
	37	#define AXGBE_DMA_SYS_AWCACHE 0x0
	38
	39	/* DMA channel interrupt modes */
	40	#define AXGBE_IRQ_MODE_EDGE 0
	41	#define AXGBE_IRQ_MODE_LEVEL 1
	42
	43	#define AXGBE_DMA_INTERRUPT_MASK 0x31c7
	44
	45	#define AXGMAC_MIN_PACKET 60
	46	#define AXGMAC_STD_PACKET_MTU 1500
	47	#define AXGMAC_MAX_STD_PACKET 1518
	48	#define AXGMAC_JUMBO_PACKET_MTU 9000
	49	#define AXGMAC_MAX_JUMBO_PACKET 9018
	50	/* Inter-frame gap + preamble */
	51	#define AXGMAC_ETH_PREAMBLE (12 + 8)
	52
	53	#define AXGMAC_PFC_DATA_LEN 46
	54	#define AXGMAC_PFC_DELAYS 14000
	55
	56	/* PCI BAR mapping */
	57	#define AXGBE_AXGMAC_BAR 0
	58	#define AXGBE_XPCS_BAR 1
	59	#define AXGBE_MAC_PROP_OFFSET 0x1d000
	60	#define AXGBE_I2C_CTRL_OFFSET 0x1e000
	61
	62	/* PCI clock frequencies */
	63	#define AXGBE_V2_DMA_CLOCK_FREQ 500000000
	64	#define AXGBE_V2_PTP_CLOCK_FREQ 125000000
	65
	66	#define AXGMAC_FIFO_MIN_ALLOC 2048
	67	#define AXGMAC_FIFO_UNIT 256
	68	#define AXGMAC_FIFO_ALIGN(_x) \
	69	(((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
	70	#define AXGMAC_FIFO_FC_OFF 2048
	71	#define AXGMAC_FIFO_FC_MIN 4096
	72
	73	#define AXGBE_TC_MIN_QUANTUM 10
	74
	75	/* Flow control queue count */
	76	#define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8
	77
	78	/* Flow control threshold units */
	79	#define AXGMAC_FLOW_CONTROL_UNIT 512
	80	#define AXGMAC_FLOW_CONTROL_ALIGN(_x) \
	81	(((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \
	82	~(AXGMAC_FLOW_CONTROL_UNIT - 1))
	83	#define AXGMAC_FLOW_CONTROL_VALUE(_x) \
	84	(((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
85	#define AXGMAC_FLOW_CONTROL_MAX 33280
86
f67539c2	87	/* Maximum MAC address hash table size (256 bits = 8 dword) */
11fdf7f2 TL	88	#define AXGBE_MAC_HASH_TABLE_SIZE 8
	89
	90	/* Receive Side Scaling */
	91	#define AXGBE_RSS_OFFLOAD ( \
	92	ETH_RSS_IPV4 \| \
	93	ETH_RSS_NONFRAG_IPV4_TCP \| \
	94	ETH_RSS_NONFRAG_IPV4_UDP \| \
	95	ETH_RSS_IPV6 \| \
	96	ETH_RSS_NONFRAG_IPV6_TCP \| \
	97	ETH_RSS_NONFRAG_IPV6_UDP)
	98
	99	#define AXGBE_RSS_HASH_KEY_SIZE 40
	100	#define AXGBE_RSS_MAX_TABLE_SIZE 256
	101	#define AXGBE_RSS_LOOKUP_TABLE_TYPE 0
	102	#define AXGBE_RSS_HASH_KEY_TYPE 1
	103
	104	/* Auto-negotiation */
	105	#define AXGBE_AN_MS_TIMEOUT 500
	106	#define AXGBE_LINK_TIMEOUT 5
	107
	108	#define AXGBE_SGMII_AN_LINK_STATUS BIT(1)
	109	#define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) \| BIT(3))
	110	#define AXGBE_SGMII_AN_LINK_SPEED_100 0x04
	111	#define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08
	112	#define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4)
	113
	114	/* ECC correctable error notification window (seconds) */
	115	#define AXGBE_ECC_LIMIT 60
	116
	117	/* MDIO port types */
	118	#define AXGMAC_MAX_C22_PORT 3
	119
	120	/* Helper macro for descriptor handling
	121	* Always use AXGBE_GET_DESC_DATA to access the descriptor data
	122	* since the index is free-running and needs to be and-ed
	123	* with the descriptor count value of the ring to index to
	124	* the proper descriptor data.
	125	*/
	126	#define AXGBE_GET_DESC_DATA(_ring, _idx) \
	127	((_ring)->rdata + \
	128	((_idx) & ((_ring)->rdesc_count - 1)))
	129
	130	struct axgbe_port;
	131
	132	enum axgbe_state {
	133	AXGBE_DOWN,
	134	AXGBE_LINK_INIT,
	135	AXGBE_LINK_ERR,
	136	AXGBE_STOPPED,
	137	};
	138
	139	enum axgbe_int {
	140	AXGMAC_INT_DMA_CH_SR_TI,
	141	AXGMAC_INT_DMA_CH_SR_TPS,
	142	AXGMAC_INT_DMA_CH_SR_TBU,
	143	AXGMAC_INT_DMA_CH_SR_RI,
	144	AXGMAC_INT_DMA_CH_SR_RBU,
	145	AXGMAC_INT_DMA_CH_SR_RPS,
	146	AXGMAC_INT_DMA_CH_SR_TI_RI,
	147	AXGMAC_INT_DMA_CH_SR_FBE,
	148	AXGMAC_INT_DMA_ALL,
	149	};
	150
	151	enum axgbe_int_state {
152	AXGMAC_INT_STATE_SAVE,
153	AXGMAC_INT_STATE_RESTORE,
154	};
155
156	enum axgbe_ecc_sec {
157	AXGBE_ECC_SEC_TX,
158	AXGBE_ECC_SEC_RX,
159	AXGBE_ECC_SEC_DESC,
160	};
161
162	enum axgbe_speed {
163	AXGBE_SPEED_1000 = 0,
164	AXGBE_SPEED_2500,
165	AXGBE_SPEED_10000,
166	AXGBE_SPEEDS,
167	};
168
169	enum axgbe_xpcs_access {
170	AXGBE_XPCS_ACCESS_V1 = 0,
171	AXGBE_XPCS_ACCESS_V2,
172	};
173
174	enum axgbe_an_mode {
175	AXGBE_AN_MODE_CL73 = 0,
176	AXGBE_AN_MODE_CL73_REDRV,
177	AXGBE_AN_MODE_CL37,
178	AXGBE_AN_MODE_CL37_SGMII,
179	AXGBE_AN_MODE_NONE,
180	};
181
182	enum axgbe_an {
183	AXGBE_AN_READY = 0,
184	AXGBE_AN_PAGE_RECEIVED,
185	AXGBE_AN_INCOMPAT_LINK,
186	AXGBE_AN_COMPLETE,
187	AXGBE_AN_NO_LINK,
188	AXGBE_AN_ERROR,
189	};
190
191	enum axgbe_rx {
192	AXGBE_RX_BPA = 0,
193	AXGBE_RX_XNP,
194	AXGBE_RX_COMPLETE,
195	AXGBE_RX_ERROR,
196	};
197
198	enum axgbe_mode {
199	AXGBE_MODE_KX_1000 = 0,
200	AXGBE_MODE_KX_2500,
201	AXGBE_MODE_KR,
202	AXGBE_MODE_X,
203	AXGBE_MODE_SGMII_100,
204	AXGBE_MODE_SGMII_1000,
205	AXGBE_MODE_SFI,
206	AXGBE_MODE_UNKNOWN,
207	};
208
209	enum axgbe_speedset {
210	AXGBE_SPEEDSET_1000_10000 = 0,
211	AXGBE_SPEEDSET_2500_10000,
212	};
213
214	enum axgbe_mdio_mode {
215	AXGBE_MDIO_MODE_NONE = 0,
216	AXGBE_MDIO_MODE_CL22,
217	AXGBE_MDIO_MODE_CL45,
218	};
219
220	struct axgbe_phy {
221	uint32_t supported;
222	uint32_t advertising;
223	uint32_t lp_advertising;
224
225	int address;
226
227	int autoneg;
228	int speed;
229	int duplex;
230
231	int link;
232
233	int pause_autoneg;
234	int tx_pause;
235	int rx_pause;
236	};
237
238	enum axgbe_i2c_cmd {
239	AXGBE_I2C_CMD_READ = 0,
240	AXGBE_I2C_CMD_WRITE,
241	};
242
243	struct axgbe_i2c_op {
244	enum axgbe_i2c_cmd cmd;
245
246	unsigned int target;
247
248	uint8_t *buf;
249	unsigned int len;
250	};
251
252	struct axgbe_i2c_op_state {
253	struct axgbe_i2c_op *op;
254
255	unsigned int tx_len;
256	unsigned char *tx_buf;
257
258	unsigned int rx_len;
259	unsigned char *rx_buf;
260
261	unsigned int tx_abort_source;
262
263	int ret;
264	};
265
266	struct axgbe_i2c {
267	unsigned int started;
268	unsigned int max_speed_mode;
269	unsigned int rx_fifo_size;
270	unsigned int tx_fifo_size;
271
272	struct axgbe_i2c_op_state op_state;
273	};
274
275	struct axgbe_hw_if {
276	void (config_flow_control)(struct axgbe_port );
277	int (config_rx_mode)(struct axgbe_port );
278
279	int (init)(struct axgbe_port );
280
281	int (read_mmd_regs)(struct axgbe_port , int, int);
282	void (write_mmd_regs)(struct axgbe_port , int, int, int);
283	int (set_speed)(struct axgbe_port , int);
284
285	int (set_ext_mii_mode)(struct axgbe_port , unsigned int,
286	enum axgbe_mdio_mode);
287	int (read_ext_mii_regs)(struct axgbe_port , int, int);
288	int (write_ext_mii_regs)(struct axgbe_port , int, int, uint16_t);
289
290	/* For FLOW ctrl */
291	int (config_tx_flow_control)(struct axgbe_port );
292	int (config_rx_flow_control)(struct axgbe_port );
293
294	int (exit)(struct axgbe_port );
295	};
296
297	/* This structure represents implementation specific routines for an
298	* implementation of a PHY. All routines are required unless noted below.
299	* Optional routines:
300	* kr_training_pre, kr_training_post
301	*/
302	struct axgbe_phy_impl_if {
303	/* Perform Setup/teardown actions */
304	int (init)(struct axgbe_port );
305	void (exit)(struct axgbe_port );
306
307	/* Perform start/stop specific actions */
308	int (reset)(struct axgbe_port );
309	int (start)(struct axgbe_port );
310	void (stop)(struct axgbe_port );
311
312	/* Return the link status */
313	int (link_status)(struct axgbe_port , int *);
314
315	/* Indicate if a particular speed is valid */
316	int (valid_speed)(struct axgbe_port , int);
317
318	/* Check if the specified mode can/should be used */
319	bool (use_mode)(struct axgbe_port , enum axgbe_mode);
320	/* Switch the PHY into various modes */
321	void (set_mode)(struct axgbe_port , enum axgbe_mode);
322	/* Retrieve mode needed for a specific speed */
323	enum axgbe_mode (get_mode)(struct axgbe_port , int);
324	/* Retrieve new/next mode when trying to auto-negotiate */
325	enum axgbe_mode (switch_mode)(struct axgbe_port );
326	/* Retrieve current mode */
327	enum axgbe_mode (cur_mode)(struct axgbe_port );
328
329	/* Retrieve current auto-negotiation mode */
330	enum axgbe_an_mode (an_mode)(struct axgbe_port );
331
332	/* Configure auto-negotiation settings */
333	int (an_config)(struct axgbe_port );
334
335	/* Set/override auto-negotiation advertisement settings */
336	unsigned int (an_advertising)(struct axgbe_port port);
337
338	/* Process results of auto-negotiation */
339	enum axgbe_mode (an_outcome)(struct axgbe_port );
340
341	/* Pre/Post auto-negotiation support */
342	void (an_pre)(struct axgbe_port port);
343	void (an_post)(struct axgbe_port port);
344
345	/* Pre/Post KR training enablement support */
346	void (kr_training_pre)(struct axgbe_port );
347	void (kr_training_post)(struct axgbe_port );
348	};
349
350	struct axgbe_phy_if {
351	/* For PHY setup/teardown */
352	int (phy_init)(struct axgbe_port );
353	void (phy_exit)(struct axgbe_port );
354
355	/* For PHY support when setting device up/down */
356	int (phy_reset)(struct axgbe_port );
357	int (phy_start)(struct axgbe_port );
358	void (phy_stop)(struct axgbe_port );
359
360	/* For PHY support while device is up */
361	void (phy_status)(struct axgbe_port );
362	int (phy_config_aneg)(struct axgbe_port );
363
364	/* For PHY settings validation */
365	int (phy_valid_speed)(struct axgbe_port , int);
366	/* For single interrupt support */
367	void (an_isr)(struct axgbe_port );
368	/* PHY implementation specific services */
369	struct axgbe_phy_impl_if phy_impl;
370	};
371
372	struct axgbe_i2c_if {
373	/* For initial I2C setup */
374	int (i2c_init)(struct axgbe_port );
375
376	/* For I2C support when setting device up/down */
377	int (i2c_start)(struct axgbe_port );
378	void (i2c_stop)(struct axgbe_port );
379
380	/* For performing I2C operations */
381	int (i2c_xfer)(struct axgbe_port , struct axgbe_i2c_op *);
382	};
383
384	/* This structure contains flags that indicate what hardware features
385	* or configurations are present in the device.
386	*/
387	struct axgbe_hw_features {
388	/* HW Version */
389	unsigned int version;
390
391	/* HW Feature Register0 */
392	unsigned int gmii; /* 1000 Mbps support */
393	unsigned int vlhash; /* VLAN Hash Filter */
394	unsigned int sma; /* SMA(MDIO) Interface */
395	unsigned int rwk; /* PMT remote wake-up packet */
396	unsigned int mgk; /* PMT magic packet */
397	unsigned int mmc; /* RMON module */
398	unsigned int aoe; /* ARP Offload */
399	unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
400	unsigned int eee; /* Energy Efficient Ethernet */
401	unsigned int tx_coe; /* Tx Checksum Offload */
402	unsigned int rx_coe; /* Rx Checksum Offload */
403	unsigned int addn_mac; /* Additional MAC Addresses */
404	unsigned int ts_src; /* Timestamp Source */
405	unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
406
407	/* HW Feature Register1 */
408	unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
409	unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
410	unsigned int adv_ts_hi; /* Advance Timestamping High Word */
411	unsigned int dma_width; /* DMA width */
412	unsigned int dcb; /* DCB Feature */
413	unsigned int sph; /* Split Header Feature */
414	unsigned int tso; /* TCP Segmentation Offload */
415	unsigned int dma_debug; /* DMA Debug Registers */
416	unsigned int rss; /* Receive Side Scaling */
417	unsigned int tc_cnt; /* Number of Traffic Classes */
418	unsigned int hash_table_size; /* Hash Table Size */
419	unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
420
421	/* HW Feature Register2 */
422	unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
423	unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
424	unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
425	unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
426	unsigned int pps_out_num; /* Number of PPS outputs */
427	unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
428	};
429
430	struct axgbe_version_data {
431	void (init_function_ptrs_phy_impl)(struct axgbe_phy_if );
432	enum axgbe_xpcs_access xpcs_access;
433	unsigned int mmc_64bit;
434	unsigned int tx_max_fifo_size;
435	unsigned int rx_max_fifo_size;
436	unsigned int tx_tstamp_workaround;
437	unsigned int ecc_support;
438	unsigned int i2c_support;
439	unsigned int an_cdr_workaround;
440	};
441
f67539c2 TL	442	struct axgbe_mmc_stats {
	443	/* Tx Stats */
	444	uint64_t txoctetcount_gb;
	445	uint64_t txframecount_gb;
	446	uint64_t txbroadcastframes_g;
	447	uint64_t txmulticastframes_g;
	448	uint64_t tx64octets_gb;
	449	uint64_t tx65to127octets_gb;
	450	uint64_t tx128to255octets_gb;
	451	uint64_t tx256to511octets_gb;
	452	uint64_t tx512to1023octets_gb;
	453	uint64_t tx1024tomaxoctets_gb;
	454	uint64_t txunicastframes_gb;
	455	uint64_t txmulticastframes_gb;
	456	uint64_t txbroadcastframes_gb;
	457	uint64_t txunderflowerror;
	458	uint64_t txoctetcount_g;
	459	uint64_t txframecount_g;
	460	uint64_t txpauseframes;
	461	uint64_t txvlanframes_g;
	462
	463	/* Rx Stats */
	464	uint64_t rxframecount_gb;
	465	uint64_t rxoctetcount_gb;
	466	uint64_t rxoctetcount_g;
	467	uint64_t rxbroadcastframes_g;
	468	uint64_t rxmulticastframes_g;
	469	uint64_t rxcrcerror;
	470	uint64_t rxrunterror;
	471	uint64_t rxjabbererror;
	472	uint64_t rxundersize_g;
	473	uint64_t rxoversize_g;
	474	uint64_t rx64octets_gb;
	475	uint64_t rx65to127octets_gb;
	476	uint64_t rx128to255octets_gb;
	477	uint64_t rx256to511octets_gb;
	478	uint64_t rx512to1023octets_gb;
	479	uint64_t rx1024tomaxoctets_gb;
	480	uint64_t rxunicastframes_g;
	481	uint64_t rxlengtherror;
	482	uint64_t rxoutofrangetype;
	483	uint64_t rxpauseframes;
	484	uint64_t rxfifooverflow;
	485	uint64_t rxvlanframes_gb;
	486	uint64_t rxwatchdogerror;
	487	};
	488
	489	/* Flow control parameters */
	490	struct xgbe_fc_info {
	491	uint32_t high_water[AXGBE_PRIORITY_QUEUES];
	492	uint32_t low_water[AXGBE_PRIORITY_QUEUES];
	493	uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
	494	uint16_t send_xon;
	495	enum rte_eth_fc_mode mode;
	496	uint8_t autoneg;
	497	};
	498
11fdf7f2 TL	499	/*
	500	* Structure to store private data for each port.
	501	*/
	502	struct axgbe_port {
	503	/* Ethdev where port belongs*/
	504	struct rte_eth_dev *eth_dev;
	505	/* Pci dev info */
	506	const struct rte_pci_device *pci_dev;
	507	/* Version related data */
	508	struct axgbe_version_data *vdata;
	509
	510	/* AXGMAC/XPCS related mmio registers */
	511	void xgmac_regs; / AXGMAC CSRs */
	512	void xpcs_regs; / XPCS MMD registers */
	513	void xprop_regs; / AXGBE property registers */
	514	void xi2c_regs; / AXGBE I2C CSRs */
	515
	516	bool cdr_track_early;
	517	/* XPCS indirect addressing lock */
	518	unsigned int xpcs_window_def_reg;
	519	unsigned int xpcs_window_sel_reg;
	520	unsigned int xpcs_window;
	521	unsigned int xpcs_window_size;
	522	unsigned int xpcs_window_mask;
	523
	524	/* Flags representing axgbe_state */
	525	unsigned long dev_state;
	526
	527	struct axgbe_hw_if hw_if;
	528	struct axgbe_phy_if phy_if;
	529	struct axgbe_i2c_if i2c_if;
	530
	531	/* AXI DMA settings */
	532	unsigned int coherent;
	533	unsigned int axdomain;
	534	unsigned int arcache;
	535	unsigned int awcache;
	536
	537	unsigned int tx_max_channel_count;
	538	unsigned int rx_max_channel_count;
	539	unsigned int channel_count;
	540	unsigned int tx_ring_count;
	541	unsigned int tx_desc_count;
	542	unsigned int rx_ring_count;
	543	unsigned int rx_desc_count;
	544
	545	unsigned int tx_max_q_count;
	546	unsigned int rx_max_q_count;
	547	unsigned int tx_q_count;
	548	unsigned int rx_q_count;
	549
	550	/* Tx/Rx common settings */
	551	unsigned int pblx8;
	552
	553	/* Tx settings */
	554	unsigned int tx_sf_mode;
	555	unsigned int tx_threshold;
	556	unsigned int tx_pbl;
	557	unsigned int tx_osp_mode;
	558	unsigned int tx_max_fifo_size;
	559
	560	/* Rx settings */
	561	unsigned int rx_sf_mode;
	562	unsigned int rx_threshold;
563	unsigned int rx_pbl;
564	unsigned int rx_max_fifo_size;
565	unsigned int rx_buf_size;
566
567	/* Device clocks */
568	unsigned long sysclk_rate;
569	unsigned long ptpclk_rate;
570
571	/* Keeps track of power mode */
572	unsigned int power_down;
573
574	/* Current PHY settings */
575	int phy_link;
576	int phy_speed;
577
578	pthread_mutex_t xpcs_mutex;
579	pthread_mutex_t i2c_mutex;
580	pthread_mutex_t an_mutex;
581	pthread_mutex_t phy_mutex;
582
583	/* Flow control settings */
584	unsigned int pause_autoneg;
585	unsigned int tx_pause;
586	unsigned int rx_pause;
587	unsigned int rx_rfa[AXGBE_MAX_QUEUES];
588	unsigned int rx_rfd[AXGBE_MAX_QUEUES];
589	unsigned int fifo;
f67539c2	590	unsigned int pfc_map[AXGBE_MAX_QUEUES];
11fdf7f2 TL	591
	592	/* Receive Side Scaling settings */
	593	u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
	594	uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
	595	uint32_t rss_options;
	596	int rss_enable;
	597
	598	/* Hardware features of the device */
	599	struct axgbe_hw_features hw_feat;
	600
f67539c2	601	struct rte_ether_addr mac_addr;
11fdf7f2 TL	602
	603	/* Software Tx/Rx structure pointers*/
	604	void **rx_queues;
	605	void **tx_queues;
	606
	607	/* MDIO/PHY related settings */
	608	unsigned int phy_started;
	609	void *phy_data;
	610	struct axgbe_phy phy;
	611	int mdio_mmd;
	612	unsigned long link_check;
	613	volatile int mdio_completion;
	614
	615	unsigned int kr_redrv;
	616
	617	/* Auto-negotiation atate machine support */
	618	unsigned int an_int;
	619	unsigned int an_status;
	620	enum axgbe_an an_result;
	621	enum axgbe_an an_state;
	622	enum axgbe_rx kr_state;
	623	enum axgbe_rx kx_state;
	624	unsigned int an_supported;
	625	unsigned int parallel_detect;
	626	unsigned int fec_ability;
	627	unsigned long an_start;
	628	enum axgbe_an_mode an_mode;
	629
	630	/* I2C support */
	631	struct axgbe_i2c i2c;
	632	volatile int i2c_complete;
	633
	634	/* CRC stripping by H/w for Rx packet*/
	635	int crc_strip_enable;
	636	/* csum enable to hardware */
	637	uint32_t rx_csum_enable;
f67539c2 TL	638
	639	struct axgbe_mmc_stats mmc_stats;
	640	struct xgbe_fc_info fc;
	641
	642	/* Hash filtering */
	643	unsigned int hash_table_shift;
	644	unsigned int hash_table_count;
	645	unsigned int uc_hash_mac_addr;
	646	unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
11fdf7f2 TL	647	};
	648
	649	void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
	650	void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
	651	void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
	652	void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
f67539c2 TL	653	void axgbe_set_mac_addn_addr(struct axgbe_port pdata, u8 addr,
	654	uint32_t index);
	655	void axgbe_set_mac_hash_table(struct axgbe_port pdata, u8 addr, bool add);
11fdf7f2 TL	656
11fdf7f2 TL	657	#endif /* RTE_ETH_AXGBE_H_ */