]>
Commit | Line | Data |
---|---|---|
11fdf7f2 | 1 | /* SPDX-License-Identifier: BSD-3-Clause |
7c673cae FG |
2 | * Copyright (c) 2007-2013 Broadcom Corporation. |
3 | * | |
4 | * Eric Davis <edavis@broadcom.com> | |
5 | * David Christensen <davidch@broadcom.com> | |
6 | * Gary Zambrano <zambrano@broadcom.com> | |
7 | * | |
8 | * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. | |
11fdf7f2 | 9 | * Copyright (c) 2015-2018 Cavium Inc. |
7c673cae | 10 | * All rights reserved. |
11fdf7f2 | 11 | * www.cavium.com |
7c673cae FG |
12 | */ |
13 | ||
14 | #ifndef __BNX2X_H__ | |
15 | #define __BNX2X_H__ | |
16 | ||
17 | #include <rte_byteorder.h> | |
18 | #include <rte_spinlock.h> | |
11fdf7f2 TL |
19 | #include <rte_bus_pci.h> |
20 | #include <rte_io.h> | |
7c673cae | 21 | |
f67539c2 | 22 | #include "bnx2x_osal.h" |
7c673cae FG |
23 | #include "bnx2x_ethdev.h" |
24 | #include "ecore_mfw_req.h" | |
25 | #include "ecore_fw_defs.h" | |
26 | #include "ecore_hsi.h" | |
27 | #include "ecore_reg.h" | |
28 | #include "bnx2x_stats.h" | |
29 | #include "bnx2x_vfpf.h" | |
30 | ||
31 | #include "elink.h" | |
32 | ||
f67539c2 | 33 | #ifndef RTE_EXEC_ENV_FREEBSD |
7c673cae FG |
34 | #include <linux/pci_regs.h> |
35 | ||
36 | #define PCIY_PMG PCI_CAP_ID_PM | |
37 | #define PCIY_MSI PCI_CAP_ID_MSI | |
38 | #define PCIY_EXPRESS PCI_CAP_ID_EXP | |
39 | #define PCIY_MSIX PCI_CAP_ID_MSIX | |
40 | #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC | |
41 | #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND | |
42 | #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA | |
43 | #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW | |
44 | #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS | |
45 | #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL | |
46 | #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD | |
47 | #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ | |
48 | #define PCIR_POWER_STATUS PCI_PM_CTRL | |
49 | #define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK | |
50 | #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS | |
51 | #define PCIM_PSTAT_D3 0x3 | |
52 | #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE | |
53 | #define PCIR_MSIX_CTRL PCI_MSIX_FLAGS | |
54 | #define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE | |
55 | #else | |
56 | #include <dev/pci/pcireg.h> | |
57 | #endif | |
58 | ||
59 | #define IFM_10G_CX4 20 /* 10GBase CX4 copper */ | |
60 | #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */ | |
61 | #define IFM_10G_T 26 /* 10GBase-T - RJ45 */ | |
62 | ||
f67539c2 | 63 | #ifndef RTE_EXEC_ENV_FREEBSD |
7c673cae FG |
64 | #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC |
65 | #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND | |
66 | #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA | |
67 | #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW | |
68 | #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS | |
69 | #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL | |
70 | #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD | |
71 | #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ | |
72 | #else | |
73 | #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA | |
74 | #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND | |
75 | #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA | |
76 | #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH | |
77 | #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED | |
78 | #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL | |
79 | #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD | |
80 | #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST | |
81 | #endif | |
82 | ||
83 | #ifndef ARRAY_SIZE | |
84 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) | |
85 | #endif | |
7c673cae FG |
86 | #ifndef DIV_ROUND_UP |
87 | #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) | |
88 | #endif | |
89 | #ifndef roundup | |
90 | #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) | |
91 | #endif | |
92 | #ifndef ilog2 | |
93 | static inline | |
94 | int bnx2x_ilog2(int x) | |
95 | { | |
96 | int log = 0; | |
97 | x >>= 1; | |
98 | ||
99 | while(x) { | |
100 | log++; | |
101 | x >>= 1; | |
102 | } | |
103 | return log; | |
104 | } | |
105 | #define ilog2(x) bnx2x_ilog2(x) | |
106 | #endif | |
107 | ||
9f95a23c TL |
108 | #define BNX2X_BC_VER 0x040200 |
109 | ||
7c673cae FG |
110 | #include "ecore_sp.h" |
111 | ||
112 | struct bnx2x_device_type { | |
113 | uint16_t bnx2x_vid; | |
114 | uint16_t bnx2x_did; | |
115 | uint16_t bnx2x_svid; | |
116 | uint16_t bnx2x_sdid; | |
117 | char *bnx2x_name; | |
118 | }; | |
119 | ||
120 | #define BNX2X_PAGE_SHIFT 12 | |
121 | #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT) | |
122 | #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1)) | |
123 | #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK) | |
124 | ||
125 | #if BNX2X_PAGE_SIZE != 4096 | |
126 | #error Page sizes other than 4KB are unsupported! | |
127 | #endif | |
128 | ||
129 | #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) | |
130 | #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) | |
131 | #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) | |
132 | ||
133 | /* dropless fc FW/HW related params */ | |
134 | #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) | |
135 | #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2 | |
136 | #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) | |
137 | #define FW_PREFETCH_CNT 16U | |
138 | #define DROPLESS_FC_HEADROOM 100 | |
139 | ||
140 | /* | |
141 | * Transmit Buffer Descriptor (tx_bd) definitions* | |
142 | */ | |
143 | /* NUM_TX_PAGES must be a power of 2. */ | |
f67539c2 | 144 | #define NUM_TX_PAGES 16 |
7c673cae FG |
145 | #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */ |
146 | #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */ | |
147 | ||
148 | #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */ | |
149 | #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */ | |
150 | #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */ | |
f67539c2 | 151 | #define MAX_TX_AVAIL (USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES - 2) |
7c673cae FG |
152 | #define NEXT_TX_BD(x) \ |
153 | ((((x) & USABLE_TX_BD_PER_PAGE) == \ | |
154 | (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
155 | ||
156 | #define TX_BD(x, q) ((x) & MAX_TX_BD(q)) | |
157 | #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) | |
158 | #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) | |
159 | ||
160 | #define BDS_PER_TX_PKT (3) | |
161 | ||
162 | /* | |
163 | * Trigger pending transmits when the number of available BDs is greater | |
164 | * than 1/8 of the total number of usable BDs. | |
165 | */ | |
166 | #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8) | |
167 | #define BNX2X_TX_TIMEOUT 5 | |
168 | ||
169 | /* | |
170 | * Receive Buffer Descriptor (rx_bd) definitions* | |
171 | */ | |
f67539c2 | 172 | #define MAX_RX_PAGES 8 |
7c673cae FG |
173 | #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */ |
174 | #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */ | |
175 | #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */ | |
176 | #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */ | |
177 | #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */ | |
178 | #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */ | |
f67539c2 | 179 | #define MAX_RX_AVAIL (USABLE_RX_BD_PER_PAGE * MAX_RX_PAGES - 2) |
7c673cae FG |
180 | #define RX_BD_NEXT_PAGE_DESC_CNT 2 |
181 | ||
182 | #define NEXT_RX_BD(x) \ | |
183 | ((((x) & RX_BD_PER_PAGE_MASK) == \ | |
184 | (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1) | |
185 | ||
186 | /* x & 0x3ff */ | |
187 | #define RX_BD(x, q) ((x) & MAX_RX_BD(q)) | |
188 | #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) | |
189 | #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) | |
190 | ||
191 | /* | |
192 | * Receive Completion Queue definitions* | |
193 | */ | |
194 | //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4) | |
195 | #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */ | |
196 | #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */ | |
197 | #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */ | |
198 | #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */ | |
199 | #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */ | |
200 | #define RCQ_NEXT_PAGE_DESC_CNT 1 | |
201 | ||
202 | #define NEXT_RCQ_IDX(x) \ | |
203 | ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \ | |
204 | (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
205 | ||
206 | #define CQE_BD_REL \ | |
207 | (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) | |
208 | ||
209 | #define RCQ_BD_PAGES(q) \ | |
210 | (q->nb_rx_pages * CQE_BD_REL) | |
211 | ||
212 | #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q)) | |
213 | #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7) | |
214 | #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE) | |
215 | ||
216 | /* | |
217 | * dropless fc calculations for BDs | |
218 | * Number of BDs should be as number of buffers in BRB: | |
219 | * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT | |
220 | * "next" elements on each page | |
221 | */ | |
222 | #define NUM_BD_REQ(sc) \ | |
223 | BRB_SIZE(sc) | |
224 | #define NUM_BD_PG_REQ(sc) \ | |
225 | ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE) | |
226 | #define BD_TH_LO(sc) \ | |
227 | (NUM_BD_REQ(sc) + \ | |
228 | NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ | |
229 | FW_DROP_LEVEL(sc)) | |
230 | #define BD_TH_HI(sc) \ | |
231 | (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) | |
232 | #define MIN_RX_AVAIL(sc) \ | |
233 | ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) | |
234 | ||
f67539c2 TL |
235 | #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA |
236 | #define MIN_RX_SIZE_NONTPA (RTE_MAX((uint32_t)MIN_RX_SIZE_NONTPA_HW,\ | |
237 | (uint32_t)MIN_RX_AVAIL(sc))) | |
238 | ||
7c673cae FG |
239 | /* |
240 | * dropless fc calculations for RCQs | |
241 | * Number of RCQs should be as number of buffers in BRB: | |
242 | * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT | |
243 | * "next" elements on each page | |
244 | */ | |
245 | #define NUM_RCQ_REQ(sc) \ | |
246 | BRB_SIZE(sc) | |
247 | #define NUM_RCQ_PG_REQ(sc) \ | |
248 | ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE) | |
249 | #define RCQ_TH_LO(sc) \ | |
250 | (NUM_RCQ_REQ(sc) + \ | |
251 | NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ | |
252 | FW_DROP_LEVEL(sc)) | |
253 | #define RCQ_TH_HI(sc) \ | |
254 | (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) | |
255 | ||
256 | /* Load / Unload modes */ | |
257 | #define LOAD_NORMAL 0 | |
258 | #define LOAD_OPEN 1 | |
259 | #define LOAD_DIAG 2 | |
260 | #define LOAD_LOOPBACK_EXT 3 | |
261 | #define UNLOAD_NORMAL 0 | |
262 | #define UNLOAD_CLOSE 1 | |
263 | #define UNLOAD_RECOVERY 2 | |
264 | ||
265 | /* Some constants... */ | |
266 | //#define MAX_PATH_NUM 2 | |
267 | //#define E2_MAX_NUM_OF_VFS 64 | |
268 | //#define E1H_FUNC_MAX 8 | |
269 | //#define E2_FUNC_MAX 4 /* per path */ | |
270 | #define MAX_VNIC_NUM 4 | |
271 | #define MAX_FUNC_NUM 8 /* common to all chips */ | |
272 | //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ | |
273 | #define MAX_RSS_CHAINS 16 /* a constant for HW limit */ | |
274 | #define MAX_MSI_VECTOR 8 /* a constant for HW limit */ | |
275 | ||
276 | #define ILT_NUM_PAGE_ENTRIES 3072 | |
277 | /* | |
278 | * 57711 we use whole table since we have 8 functions. | |
279 | * 57712 we have only 4 functions, but use same size per func, so only half | |
280 | * of the table is used. | |
281 | */ | |
282 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) | |
283 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
284 | /* | |
285 | * the phys address is shifted right 12 bits and has an added | |
286 | * 1=valid bit added to the 53rd bit | |
287 | * then since this is a wide register(TM) | |
288 | * we split it into two 32 bit writes | |
289 | */ | |
290 | #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) | |
291 | #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) | |
292 | ||
293 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ | |
294 | #define ETH_HLEN 14 | |
295 | #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) | |
296 | #define ETH_MIN_PACKET_SIZE 60 | |
297 | #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ | |
298 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
299 | /* TCP with Timestamp Option (32) + IPv6 (40) */ | |
300 | ||
301 | /* max supported alignment is 256 (8 shift) */ | |
302 | #define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2)) | |
303 | ||
304 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) | |
305 | ||
306 | struct bnx2x_bar { | |
307 | void *base_addr; | |
308 | }; | |
309 | ||
310 | /* Used to manage DMA allocations. */ | |
311 | struct bnx2x_dma { | |
312 | struct bnx2x_softc *sc; | |
11fdf7f2 | 313 | rte_iova_t paddr; |
7c673cae FG |
314 | void *vaddr; |
315 | int nseg; | |
9f95a23c | 316 | const void *mzone; |
7c673cae FG |
317 | char msg[RTE_MEMZONE_NAMESIZE - 6]; |
318 | }; | |
319 | ||
320 | /* attn group wiring */ | |
321 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
322 | ||
323 | struct attn_route { | |
324 | uint32_t sig[5]; | |
325 | }; | |
326 | ||
327 | struct iro { | |
328 | uint32_t base; | |
329 | uint16_t m1; | |
330 | uint16_t m2; | |
331 | uint16_t m3; | |
332 | uint16_t size; | |
333 | }; | |
334 | ||
335 | union bnx2x_host_hc_status_block { | |
336 | /* pointer to fp status block e2 */ | |
337 | struct host_hc_status_block_e2 *e2_sb; | |
338 | /* pointer to fp status block e1x */ | |
339 | struct host_hc_status_block_e1x *e1x_sb; | |
340 | }; | |
341 | ||
342 | union bnx2x_db_prod { | |
343 | struct doorbell_set_prod data; | |
344 | uint32_t raw; | |
345 | }; | |
346 | ||
347 | struct bnx2x_sw_tx_bd { | |
348 | struct mbuf *m; | |
349 | uint16_t first_bd; | |
350 | uint8_t flags; | |
351 | /* set on the first BD descriptor when there is a split BD */ | |
352 | #define BNX2X_TSO_SPLIT_BD (1 << 0) | |
353 | }; | |
354 | ||
355 | /* | |
356 | * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN | |
357 | * instances of the fastpath structure when using multiple queues. | |
358 | */ | |
359 | struct bnx2x_fastpath { | |
360 | /* pointer back to parent structure */ | |
361 | struct bnx2x_softc *sc; | |
362 | ||
f67539c2 TL |
363 | /* Used to synchronize fastpath Rx access */ |
364 | rte_spinlock_t rx_mtx; | |
365 | ||
7c673cae FG |
366 | /* status block */ |
367 | struct bnx2x_dma sb_dma; | |
368 | union bnx2x_host_hc_status_block status_block; | |
369 | ||
11fdf7f2 | 370 | rte_iova_t tx_desc_mapping; |
7c673cae | 371 | |
11fdf7f2 TL |
372 | rte_iova_t rx_desc_mapping; |
373 | rte_iova_t rx_comp_mapping; | |
7c673cae FG |
374 | |
375 | uint16_t *sb_index_values; | |
376 | uint16_t *sb_running_index; | |
377 | uint32_t ustorm_rx_prods_offset; | |
378 | ||
379 | uint8_t igu_sb_id; /* status block number in HW */ | |
380 | uint8_t fw_sb_id; /* status block number in FW */ | |
381 | ||
382 | uint32_t rx_buf_size; | |
383 | ||
384 | int state; | |
385 | #define BNX2X_FP_STATE_CLOSED 0x01 | |
386 | #define BNX2X_FP_STATE_IRQ 0x02 | |
387 | #define BNX2X_FP_STATE_OPENING 0x04 | |
388 | #define BNX2X_FP_STATE_OPEN 0x08 | |
389 | #define BNX2X_FP_STATE_HALTING 0x10 | |
390 | #define BNX2X_FP_STATE_HALTED 0x20 | |
391 | ||
392 | /* reference back to this fastpath queue number */ | |
393 | uint8_t index; /* this is also the 'cid' */ | |
394 | #define FP_IDX(fp) (fp->index) | |
395 | ||
396 | /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ | |
397 | uint8_t cl_id; | |
398 | #define FP_CL_ID(fp) (fp->cl_id) | |
399 | uint8_t cl_qzone_id; | |
400 | ||
401 | uint16_t fp_hc_idx; | |
402 | ||
403 | union bnx2x_db_prod tx_db; | |
404 | ||
405 | struct tstorm_per_queue_stats old_tclient; | |
406 | struct ustorm_per_queue_stats old_uclient; | |
407 | struct xstorm_per_queue_stats old_xclient; | |
408 | struct bnx2x_eth_q_stats eth_q_stats; | |
409 | struct bnx2x_eth_q_stats_old eth_q_stats_old; | |
410 | ||
411 | /* Pointer to the receive consumer in the status block */ | |
412 | uint16_t *rx_cq_cons_sb; | |
413 | ||
414 | /* Pointer to the transmit consumer in the status block */ | |
415 | uint16_t *tx_cons_sb; | |
416 | ||
417 | /* transmit timeout until chip reset */ | |
418 | int watchdog_timer; | |
419 | ||
420 | }; /* struct bnx2x_fastpath */ | |
421 | ||
422 | #define BNX2X_MAX_NUM_OF_VFS 64 | |
423 | #define BNX2X_VF_ID_INVALID 0xFF | |
424 | ||
425 | /* maximum number of fast-path interrupt contexts */ | |
426 | #define FP_SB_MAX_E1x 16 | |
427 | #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 | |
428 | ||
429 | union cdu_context { | |
430 | struct eth_context eth; | |
431 | char pad[1024]; | |
432 | }; | |
433 | ||
434 | /* CDU host DB constants */ | |
435 | #define CDU_ILT_PAGE_SZ_HW 2 | |
436 | #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ | |
437 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) | |
438 | ||
439 | #define CNIC_ISCSI_CID_MAX 256 | |
440 | #define CNIC_FCOE_CID_MAX 2048 | |
441 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) | |
442 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) | |
443 | ||
444 | #define QM_ILT_PAGE_SZ_HW 0 | |
445 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ | |
446 | #define QM_CID_ROUND 1024 | |
447 | ||
448 | /* TM (timers) host DB constants */ | |
449 | #define TM_ILT_PAGE_SZ_HW 0 | |
450 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ | |
451 | /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ | |
452 | #define TM_CONN_NUM 1024 | |
453 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
454 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
455 | ||
456 | /* SRC (Searcher) host DB constants */ | |
457 | #define SRC_ILT_PAGE_SZ_HW 0 | |
458 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ | |
459 | #define SRC_HASH_BITS 10 | |
460 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
461 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
462 | #define SRC_T2_SZ SRC_ILT_SZ | |
463 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
464 | ||
465 | struct hw_context { | |
466 | struct bnx2x_dma vcxt_dma; | |
467 | union cdu_context *vcxt; | |
11fdf7f2 | 468 | //rte_iova_t cxt_mapping; |
7c673cae FG |
469 | size_t size; |
470 | }; | |
471 | ||
472 | #define SM_RX_ID 0 | |
473 | #define SM_TX_ID 1 | |
474 | ||
475 | /* defines for multiple tx priority indices */ | |
476 | #define FIRST_TX_ONLY_COS_INDEX 1 | |
477 | #define FIRST_TX_COS_INDEX 0 | |
478 | ||
479 | #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc)) | |
480 | ||
481 | #define HC_INDEX_ETH_RX_CQ_CONS 1 | |
482 | #define HC_INDEX_OOO_TX_CQ_CONS 4 | |
483 | #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 | |
484 | #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 | |
485 | #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 | |
486 | #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 | |
487 | ||
488 | /* congestion management fairness mode */ | |
489 | #define CMNG_FNS_NONE 0 | |
490 | #define CMNG_FNS_MINMAX 1 | |
491 | ||
492 | /* CMNG constants, as derived from system spec calculations */ | |
493 | /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ | |
494 | #define DEF_MIN_RATE 100 | |
495 | /* resolution of the rate shaping timer - 400 usec */ | |
496 | #define RS_PERIODIC_TIMEOUT_USEC 400 | |
497 | /* number of bytes in single QM arbitration cycle - | |
498 | * coefficient for calculating the fairness timer */ | |
499 | #define QM_ARB_BYTES 160000 | |
500 | /* resolution of Min algorithm 1:100 */ | |
501 | #define MIN_RES 100 | |
502 | /* how many bytes above threshold for the minimal credit of Min algorithm*/ | |
503 | #define MIN_ABOVE_THRESH 32768 | |
504 | /* fairness algorithm integration time coefficient - | |
505 | * for calculating the actual Tfair */ | |
506 | #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) | |
507 | /* memory of fairness algorithm - 2 cycles */ | |
508 | #define FAIR_MEM 2 | |
509 | ||
510 | #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ | |
511 | #define HC_SEG_ACCESS_ATTN 4 | |
512 | #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ | |
513 | ||
514 | /* | |
515 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
516 | * control by the number of fast-path status blocks supported by the | |
517 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
518 | * status block represents an independent interrupts context that can | |
519 | * serve a regular L2 networking queue. However special L2 queues such | |
520 | * as the FCoE queue do not require a FP-SB and other components like | |
521 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
522 | * | |
523 | * If the maximum number of FP-SB available is X then: | |
524 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
525 | * regular L2 queues is Y=X-1 | |
526 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) | |
527 | * c. If the FCoE L2 queue is supported the actual number of L2 queues | |
528 | * is Y+1 | |
529 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
530 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
531 | * FP interrupt context for the CNIC). | |
532 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
533 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. | |
534 | * | |
535 | * So this is quite simple for now as no ULPs are supported yet. :-) | |
536 | */ | |
537 | #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues) | |
538 | #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc) | |
539 | #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc) | |
540 | #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc) | |
541 | ||
542 | #define FOR_EACH_QUEUE(sc, var) \ | |
543 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++) | |
544 | ||
545 | #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ | |
546 | for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++) | |
547 | ||
548 | #define FOR_EACH_ETH_QUEUE(sc, var) \ | |
549 | for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++) | |
550 | ||
551 | #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ | |
552 | for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++) | |
553 | ||
554 | #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ | |
555 | for ((var) = 0; (var) < (sc)->max_cos; (var)++) | |
556 | ||
557 | #define FOR_EACH_CNIC_QUEUE(sc, var) \ | |
558 | for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \ | |
559 | (var) < BNX2X_NUM_QUEUES(sc); \ | |
560 | (var)++) | |
561 | ||
562 | enum { | |
563 | OOO_IDX_OFFSET, | |
564 | FCOE_IDX_OFFSET, | |
565 | FWD_IDX_OFFSET, | |
566 | }; | |
567 | ||
568 | #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) | |
569 | #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) | |
570 | #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var) | |
571 | #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) | |
572 | #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var) | |
573 | #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) | |
574 | ||
575 | #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) | |
576 | #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) | |
577 | #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var) | |
578 | #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) | |
579 | #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var) | |
580 | ||
581 | #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) | |
582 | #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) | |
583 | #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var) | |
584 | #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) | |
585 | #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var) | |
586 | #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) | |
587 | ||
588 | #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc)) | |
589 | #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) | |
590 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) | |
591 | #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) | |
592 | #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) | |
593 | #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) | |
594 | #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) | |
595 | ||
596 | enum { | |
597 | BNX2X_PORT_QUERY_IDX, | |
598 | BNX2X_PF_QUERY_IDX, | |
599 | BNX2X_FCOE_QUERY_IDX, | |
600 | BNX2X_FIRST_QUEUE_QUERY_IDX, | |
601 | }; | |
602 | ||
603 | struct bnx2x_fw_stats_req { | |
604 | struct stats_query_header hdr; | |
605 | struct stats_query_entry query[FP_SB_MAX_E1x + | |
606 | BNX2X_FIRST_QUEUE_QUERY_IDX]; | |
607 | }; | |
608 | ||
609 | struct bnx2x_fw_stats_data { | |
610 | struct stats_counter storm_counters; | |
611 | struct per_port_stats port; | |
612 | struct per_pf_stats pf; | |
613 | struct per_queue_stats queue_stats[1]; | |
614 | }; | |
615 | ||
616 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ | |
617 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
618 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
619 | ||
620 | #define MAX_DMAE_C 8 | |
621 | ||
622 | /* | |
623 | * This is the slowpath data structure. It is mapped into non-paged memory | |
624 | * so that the hardware can access it's contents directly and must be page | |
625 | * aligned. | |
626 | */ | |
627 | struct bnx2x_slowpath { | |
628 | ||
629 | /* used by the DMAE command executer */ | |
630 | struct dmae_command dmae[MAX_DMAE_C]; | |
631 | ||
632 | /* statistics completion */ | |
633 | uint32_t stats_comp; | |
634 | ||
635 | /* firmware defined statistics blocks */ | |
636 | union mac_stats mac_stats; | |
637 | struct nig_stats nig_stats; | |
638 | struct host_port_stats port_stats; | |
639 | struct host_func_stats func_stats; | |
640 | ||
641 | /* DMAE completion value and data source/sink */ | |
642 | uint32_t wb_comp; | |
643 | uint32_t wb_data[4]; | |
644 | ||
645 | union { | |
646 | struct mac_configuration_cmd e1x; | |
647 | struct eth_classify_rules_ramrod_data e2; | |
648 | } mac_rdata; | |
649 | ||
650 | union { | |
651 | struct tstorm_eth_mac_filter_config e1x; | |
652 | struct eth_filter_rules_ramrod_data e2; | |
653 | } rx_mode_rdata; | |
654 | ||
655 | struct eth_rss_update_ramrod_data rss_rdata; | |
656 | ||
657 | union { | |
658 | struct mac_configuration_cmd e1; | |
659 | struct eth_multicast_rules_ramrod_data e2; | |
660 | } mcast_rdata; | |
661 | ||
662 | union { | |
663 | struct function_start_data func_start; | |
664 | struct flow_control_configuration pfc_config; /* for DCBX ramrod */ | |
665 | } func_rdata; | |
666 | ||
667 | /* Queue State related ramrods */ | |
668 | union { | |
669 | struct client_init_ramrod_data init_data; | |
670 | struct client_update_ramrod_data update_data; | |
671 | } q_rdata; | |
672 | ||
673 | /* | |
674 | * AFEX ramrod can not be a part of func_rdata union because these | |
675 | * events might arrive in parallel to other events from func_rdata. | |
676 | * If they were defined in the same union the data can get corrupted. | |
677 | */ | |
678 | struct afex_vif_list_ramrod_data func_afex_rdata; | |
679 | ||
680 | union drv_info_to_mcp drv_info_to_mcp; | |
681 | }; /* struct bnx2x_slowpath */ | |
682 | ||
683 | /* | |
684 | * Port specifc data structure. | |
685 | */ | |
686 | struct bnx2x_port { | |
687 | /* | |
688 | * Port Management Function (for 57711E only). | |
689 | * When this field is set the driver instance is | |
690 | * responsible for managing port specifc | |
691 | * configurations such as handling link attentions. | |
692 | */ | |
693 | uint32_t pmf; | |
694 | ||
695 | /* Ethernet maximum transmission unit. */ | |
696 | uint16_t ether_mtu; | |
697 | ||
698 | uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; | |
699 | ||
700 | uint32_t ext_phy_config; | |
701 | ||
702 | /* Port feature config.*/ | |
703 | uint32_t config; | |
704 | ||
705 | /* Defines the features supported by the PHY. */ | |
706 | uint32_t supported[ELINK_LINK_CONFIG_SIZE]; | |
707 | ||
708 | /* Defines the features advertised by the PHY. */ | |
709 | uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; | |
710 | #define ADVERTISED_10baseT_Half (1 << 1) | |
711 | #define ADVERTISED_10baseT_Full (1 << 2) | |
712 | #define ADVERTISED_100baseT_Half (1 << 3) | |
713 | #define ADVERTISED_100baseT_Full (1 << 4) | |
714 | #define ADVERTISED_1000baseT_Half (1 << 5) | |
715 | #define ADVERTISED_1000baseT_Full (1 << 6) | |
716 | #define ADVERTISED_TP (1 << 7) | |
717 | #define ADVERTISED_FIBRE (1 << 8) | |
718 | #define ADVERTISED_Autoneg (1 << 9) | |
719 | #define ADVERTISED_Asym_Pause (1 << 10) | |
720 | #define ADVERTISED_Pause (1 << 11) | |
721 | #define ADVERTISED_2500baseX_Full (1 << 15) | |
722 | #define ADVERTISED_10000baseT_Full (1 << 16) | |
723 | ||
724 | uint32_t phy_addr; | |
725 | ||
9f95a23c TL |
726 | /* Used to synchronize phy accesses. */ |
727 | rte_spinlock_t phy_mtx; | |
728 | char phy_mtx_name[32]; | |
729 | ||
730 | #define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx) | |
731 | #define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx) | |
732 | ||
7c673cae FG |
733 | /* |
734 | * MCP scratchpad address for port specific statistics. | |
735 | * The device is responsible for writing statistcss | |
736 | * back to the MCP for use with management firmware such | |
737 | * as UMP/NC-SI. | |
738 | */ | |
739 | uint32_t port_stx; | |
740 | ||
741 | struct nig_stats old_nig_stats; | |
742 | }; /* struct bnx2x_port */ | |
743 | ||
744 | struct bnx2x_mf_info { | |
745 | uint32_t mf_config[E1HVN_MAX]; | |
746 | ||
747 | uint32_t vnics_per_port; /* 1, 2 or 4 */ | |
748 | uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ | |
749 | uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ | |
750 | ||
751 | #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) | |
752 | #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) | |
753 | #define VNICS_PER_PATH(sc) \ | |
754 | ((sc)->devinfo.mf_info.vnics_per_port * \ | |
755 | ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) | |
756 | ||
757 | uint8_t min_bw[MAX_VNIC_NUM]; | |
758 | uint8_t max_bw[MAX_VNIC_NUM]; | |
759 | ||
760 | uint16_t ext_id; /* vnic outer vlan or VIF ID */ | |
761 | #define VALID_OVLAN(ovlan) ((ovlan) <= 4096) | |
762 | #define INVALID_VIF_ID 0xFFFF | |
763 | #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) | |
764 | #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) | |
765 | ||
766 | uint16_t default_vlan; | |
767 | #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) | |
768 | ||
769 | uint8_t niv_allowed_priorities; | |
770 | #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) | |
771 | ||
772 | uint8_t niv_default_cos; | |
773 | #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) | |
774 | ||
775 | uint8_t niv_mba_enabled; | |
776 | ||
777 | enum mf_cfg_afex_vlan_mode afex_vlan_mode; | |
778 | #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) | |
779 | int afex_def_vlan_tag; | |
780 | uint32_t pending_max; | |
781 | ||
782 | uint16_t flags; | |
783 | #define MF_INFO_VALID_MAC 0x0001 | |
784 | ||
785 | uint16_t mf_ov; | |
786 | uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ | |
787 | #define IS_MF(sc) \ | |
788 | (IS_MULTI_VNIC(sc) && \ | |
789 | ((sc)->devinfo.mf_info.mf_mode != 0)) | |
790 | #define IS_MF_SD(sc) \ | |
791 | (IS_MULTI_VNIC(sc) && \ | |
792 | ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) | |
793 | #define IS_MF_SI(sc) \ | |
794 | (IS_MULTI_VNIC(sc) && \ | |
795 | ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) | |
796 | #define IS_MF_AFEX(sc) \ | |
797 | (IS_MULTI_VNIC(sc) && \ | |
798 | ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) | |
799 | #define IS_MF_SD_MODE(sc) IS_MF_SD(sc) | |
800 | #define IS_MF_SI_MODE(sc) IS_MF_SI(sc) | |
801 | #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) | |
802 | ||
803 | uint32_t mf_protos_supported; | |
804 | #define MF_PROTO_SUPPORT_ETHERNET 0x1 | |
805 | #define MF_PROTO_SUPPORT_ISCSI 0x2 | |
806 | #define MF_PROTO_SUPPORT_FCOE 0x4 | |
807 | }; /* struct bnx2x_mf_info */ | |
808 | ||
809 | /* Device information data structure. */ | |
810 | struct bnx2x_devinfo { | |
9f95a23c TL |
811 | #if 1 |
812 | #define NAME_SIZE 128 | |
813 | char name[NAME_SIZE]; | |
814 | #endif | |
7c673cae FG |
815 | /* PCIe info */ |
816 | uint16_t vendor_id; | |
817 | uint16_t device_id; | |
818 | uint16_t subvendor_id; | |
819 | uint16_t subdevice_id; | |
820 | ||
821 | /* | |
822 | * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' | |
823 | * C = Chip Number (bits 16-31) | |
824 | * R = Chip Revision (bits 12-15) | |
825 | * M = Chip Metal (bits 4-11) | |
826 | * B = Chip Bond ID (bits 0-3) | |
827 | */ | |
828 | uint32_t chip_id; | |
829 | #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) | |
830 | #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) | |
831 | /* device ids */ | |
9f95a23c | 832 | #define CHIP_NUM_57710 0x164e |
7c673cae FG |
833 | #define CHIP_NUM_57711 0x164f |
834 | #define CHIP_NUM_57711E 0x1650 | |
835 | #define CHIP_NUM_57712 0x1662 | |
836 | #define CHIP_NUM_57712_MF 0x1663 | |
837 | #define CHIP_NUM_57712_VF 0x166f | |
838 | #define CHIP_NUM_57800 0x168a | |
839 | #define CHIP_NUM_57800_MF 0x16a5 | |
840 | #define CHIP_NUM_57800_VF 0x16a9 | |
841 | #define CHIP_NUM_57810 0x168e | |
842 | #define CHIP_NUM_57810_MF 0x16ae | |
843 | #define CHIP_NUM_57810_VF 0x16af | |
844 | #define CHIP_NUM_57811 0x163d | |
845 | #define CHIP_NUM_57811_MF 0x163e | |
846 | #define CHIP_NUM_57811_VF 0x163f | |
847 | #define CHIP_NUM_57840_OBS 0x168d | |
848 | #define CHIP_NUM_57840_OBS_MF 0x16ab | |
849 | #define CHIP_NUM_57840_4_10 0x16a1 | |
850 | #define CHIP_NUM_57840_2_20 0x16a2 | |
851 | #define CHIP_NUM_57840_MF 0x16a4 | |
852 | #define CHIP_NUM_57840_VF 0x16ad | |
853 | ||
854 | #define CHIP_REV_SHIFT 12 | |
855 | #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) | |
856 | #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) | |
857 | ||
858 | #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) | |
859 | #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) | |
860 | #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) | |
861 | ||
862 | #define CHIP_REV_IS_SLOW(sc) \ | |
863 | (CHIP_REV(sc) > 0x00005000) | |
864 | #define CHIP_REV_IS_FPGA(sc) \ | |
865 | (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) | |
866 | #define CHIP_REV_IS_EMUL(sc) \ | |
867 | (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) | |
868 | #define CHIP_REV_IS_ASIC(sc) \ | |
869 | (!CHIP_REV_IS_SLOW(sc)) | |
870 | ||
871 | #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) | |
872 | #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) | |
873 | ||
9f95a23c TL |
874 | #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) |
875 | #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) | |
7c673cae FG |
876 | #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) |
877 | #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) | |
878 | #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ | |
879 | (CHIP_IS_57711E(sc))) | |
880 | #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc) | |
881 | ||
882 | #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) | |
883 | #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) | |
884 | #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) | |
885 | #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ | |
886 | CHIP_IS_57712_MF(sc)) | |
887 | ||
888 | #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) | |
889 | #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) | |
890 | #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) | |
891 | #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) | |
892 | #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) | |
893 | #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) | |
894 | #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) | |
895 | #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) | |
896 | #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) | |
897 | #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ | |
898 | (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ | |
899 | (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) | |
900 | #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ | |
901 | (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) | |
902 | #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) | |
903 | ||
904 | #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ | |
905 | CHIP_IS_57800_MF(sc) || \ | |
906 | CHIP_IS_57800_VF(sc) || \ | |
907 | CHIP_IS_57810(sc) || \ | |
908 | CHIP_IS_57810_MF(sc) || \ | |
909 | CHIP_IS_57810_VF(sc) || \ | |
910 | CHIP_IS_57811(sc) || \ | |
911 | CHIP_IS_57811_MF(sc) || \ | |
912 | CHIP_IS_57811_VF(sc) || \ | |
913 | CHIP_IS_57840(sc) || \ | |
914 | CHIP_IS_57840_MF(sc) || \ | |
915 | CHIP_IS_57840_VF(sc)) | |
916 | #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ | |
917 | (CHIP_REV(sc) == CHIP_REV_Ax)) | |
918 | #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ | |
919 | (CHIP_REV(sc) == CHIP_REV_Bx)) | |
920 | ||
921 | #define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) | |
922 | #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ | |
923 | CHIP_IS_E3(sc)) | |
924 | ||
925 | #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ | |
926 | CHIP_IS_57712_MF(sc) || \ | |
927 | CHIP_IS_E3(sc)) | |
928 | ||
929 | #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG) | |
930 | #define IS_PF(sc) (!IS_VF(sc)) | |
931 | ||
932 | /* | |
933 | * This define is used in two main places: | |
934 | * 1. In the early stages of nic_load, to know if to configure Parser/Searcher | |
935 | * to nic-only mode or to offload mode. Offload mode is configured if either | |
936 | * the chip is E1x (where NIC_MODE register is not applicable), or if cnic | |
937 | * already registered for this port (which means that the user wants storage | |
938 | * services). | |
939 | * 2. During cnic-related load, to know if offload mode is already configured | |
940 | * in the HW or needs to be configrued. Since the transition from nic-mode to | |
941 | * offload-mode in HW causes traffic coruption, nic-mode is configured only | |
942 | * in ports on which storage services where never requested. | |
943 | */ | |
944 | #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) | |
945 | ||
946 | uint8_t chip_port_mode; | |
947 | #define CHIP_4_PORT_MODE 0x0 | |
948 | #define CHIP_2_PORT_MODE 0x1 | |
949 | #define CHIP_PORT_MODE_NONE 0x2 | |
950 | #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) | |
951 | #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) | |
952 | ||
953 | uint8_t int_block; | |
954 | #define INT_BLOCK_HC 0 | |
955 | #define INT_BLOCK_IGU 1 | |
956 | #define INT_BLOCK_MODE_NORMAL 0 | |
957 | #define INT_BLOCK_MODE_BW_COMP 2 | |
958 | #define CHIP_INT_MODE_IS_NBC(sc) \ | |
959 | (!CHIP_IS_E1x(sc) && \ | |
960 | !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) | |
961 | #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) | |
962 | ||
963 | uint32_t shmem_base; | |
964 | uint32_t shmem2_base; | |
965 | uint32_t bc_ver; | |
966 | char bc_ver_str[32]; | |
967 | uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ | |
968 | struct bnx2x_mf_info mf_info; | |
969 | ||
970 | uint32_t flash_size; | |
971 | #define NVRAM_1MB_SIZE 0x20000 | |
972 | #define NVRAM_TIMEOUT_COUNT 30000 | |
973 | #define NVRAM_PAGE_SIZE 256 | |
974 | ||
975 | /* PCIe capability information */ | |
976 | uint32_t pcie_cap_flags; | |
977 | #define BNX2X_PM_CAPABLE_FLAG 0x00000001 | |
978 | #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002 | |
979 | #define BNX2X_MSI_CAPABLE_FLAG 0x00000004 | |
980 | #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008 | |
981 | uint16_t pcie_pm_cap_reg; | |
982 | uint16_t pcie_link_width; | |
983 | uint16_t pcie_link_speed; | |
984 | uint16_t pcie_msi_cap_reg; | |
985 | uint16_t pcie_msix_cap_reg; | |
986 | ||
987 | /* device configuration read from bootcode shared memory */ | |
988 | uint32_t hw_config; | |
989 | uint32_t hw_config2; | |
990 | }; /* struct bnx2x_devinfo */ | |
991 | ||
992 | struct bnx2x_sp_objs { | |
993 | struct ecore_vlan_mac_obj mac_obj; /* MACs object */ | |
994 | struct ecore_queue_sp_obj q_obj; /* Queue State object */ | |
995 | }; /* struct bnx2x_sp_objs */ | |
996 | ||
997 | /* | |
998 | * Data that will be used to create a link report message. We will keep the | |
999 | * data used for the last link report in order to prevent reporting the same | |
1000 | * link parameters twice. | |
1001 | */ | |
1002 | struct bnx2x_link_report_data { | |
1003 | uint16_t line_speed; /* Effective line speed */ | |
1004 | unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */ | |
1005 | }; | |
1006 | ||
1007 | enum { | |
1008 | BNX2X_LINK_REPORT_FULL_DUPLEX, | |
1009 | BNX2X_LINK_REPORT_LINK_DOWN, | |
1010 | BNX2X_LINK_REPORT_RX_FC_ON, | |
1011 | BNX2X_LINK_REPORT_TX_FC_ON | |
1012 | }; | |
1013 | ||
1014 | #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE | |
1015 | ||
1016 | struct bnx2x_pci_cap { | |
1017 | struct bnx2x_pci_cap *next; | |
1018 | uint16_t id; | |
1019 | uint16_t type; | |
1020 | uint16_t addr; | |
1021 | }; | |
1022 | ||
f67539c2 TL |
1023 | struct ecore_ilt; |
1024 | ||
7c673cae FG |
1025 | struct bnx2x_vfdb; |
1026 | ||
1027 | /* Top level device private data structure. */ | |
1028 | struct bnx2x_softc { | |
1029 | ||
1030 | void **rx_queues; | |
1031 | void **tx_queues; | |
1032 | uint32_t max_tx_queues; | |
1033 | uint32_t max_rx_queues; | |
1034 | const struct rte_pci_device *pci_dev; | |
1035 | uint32_t pci_val; | |
1036 | struct bnx2x_pci_cap *pci_caps; | |
1037 | #define BNX2X_INTRS_POLL_PERIOD 1 | |
1038 | ||
1039 | void *firmware; | |
1040 | uint64_t fw_len; | |
1041 | ||
1042 | /* MAC address operations */ | |
1043 | struct bnx2x_mac_ops mac_ops; | |
1044 | ||
1045 | /* structures for VF mbox/response/bulletin */ | |
1046 | struct bnx2x_vf_mbx_msg *vf2pf_mbox; | |
1047 | struct bnx2x_dma vf2pf_mbox_mapping; | |
1048 | struct vf_acquire_resp_tlv acquire_resp; | |
1049 | struct bnx2x_vf_bulletin *pf2vf_bulletin; | |
1050 | struct bnx2x_dma pf2vf_bulletin_mapping; | |
1051 | struct bnx2x_vf_bulletin old_bulletin; | |
1052 | rte_spinlock_t vf2pf_lock; | |
1053 | ||
1054 | int media; | |
1055 | ||
1056 | int state; /* device state */ | |
1057 | #define BNX2X_STATE_CLOSED 0x0000 | |
1058 | #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000 | |
1059 | #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000 | |
1060 | #define BNX2X_STATE_OPEN 0x3000 | |
1061 | #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000 | |
1062 | #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000 | |
1063 | #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000 | |
1064 | #define BNX2X_STATE_DISABLED 0xD000 | |
1065 | #define BNX2X_STATE_DIAG 0xE000 | |
1066 | #define BNX2X_STATE_ERROR 0xF000 | |
1067 | ||
1068 | int flags; | |
1069 | #define BNX2X_ONE_PORT_FLAG 0x1 | |
1070 | #define BNX2X_NO_FCOE_FLAG 0x2 | |
1071 | #define BNX2X_NO_WOL_FLAG 0x4 | |
1072 | #define BNX2X_NO_MCP_FLAG 0x8 | |
1073 | #define BNX2X_NO_ISCSI_OOO_FLAG 0x10 | |
1074 | #define BNX2X_NO_ISCSI_FLAG 0x20 | |
1075 | #define BNX2X_MF_FUNC_DIS 0x40 | |
1076 | #define BNX2X_TX_SWITCHING 0x80 | |
1077 | #define BNX2X_IS_VF_FLAG 0x100 | |
1078 | ||
1079 | #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG) | |
1080 | #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG) | |
1081 | #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG) | |
1082 | ||
1083 | #define MAX_BARS 5 | |
1084 | struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ | |
1085 | ||
1086 | uint16_t doorbell_size; | |
1087 | ||
1088 | /* periodic timer callout */ | |
1089 | #define PERIODIC_STOP 0 | |
1090 | #define PERIODIC_GO 1 | |
1091 | volatile unsigned long periodic_flags; | |
9f95a23c | 1092 | rte_atomic32_t scan_fp; |
7c673cae FG |
1093 | struct bnx2x_fastpath fp[MAX_RSS_CHAINS]; |
1094 | struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS]; | |
1095 | ||
1096 | uint8_t unit; /* driver instance number */ | |
1097 | ||
1098 | int pcie_bus; /* PCIe bus number */ | |
1099 | int pcie_device; /* PCIe device/slot number */ | |
1100 | int pcie_func; /* PCIe function number */ | |
1101 | ||
1102 | uint8_t pfunc_rel; /* function relative */ | |
1103 | uint8_t pfunc_abs; /* function absolute */ | |
1104 | uint8_t path_id; /* function absolute */ | |
1105 | #define SC_PATH(sc) (sc->path_id) | |
1106 | #define SC_PORT(sc) (sc->pfunc_rel & 1) | |
1107 | #define SC_FUNC(sc) (sc->pfunc_rel) | |
1108 | #define SC_ABS_FUNC(sc) (sc->pfunc_abs) | |
1109 | #define SC_VN(sc) (sc->pfunc_rel >> 1) | |
1110 | #define SC_L_ID(sc) (SC_VN(sc) << 2) | |
1111 | #define PORT_ID(sc) SC_PORT(sc) | |
1112 | #define PATH_ID(sc) SC_PATH(sc) | |
1113 | #define VNIC_ID(sc) SC_VN(sc) | |
1114 | #define FUNC_ID(sc) SC_FUNC(sc) | |
1115 | #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) | |
1116 | #define SC_FW_MB_IDX_VN(sc, vn) \ | |
1117 | (SC_PORT(sc) + (vn) * \ | |
1118 | ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) | |
1119 | #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) | |
1120 | ||
1121 | int if_capen; /* enabled interface capabilities */ | |
1122 | ||
1123 | struct bnx2x_devinfo devinfo; | |
1124 | char fw_ver_str[32]; | |
1125 | char mf_mode_str[32]; | |
1126 | char pci_link_str[32]; | |
1127 | ||
1128 | struct iro *iro_array; | |
1129 | ||
1130 | int dmae_ready; | |
1131 | #define DMAE_READY(sc) (sc->dmae_ready) | |
1132 | ||
1133 | struct ecore_credit_pool_obj vlans_pool; | |
1134 | struct ecore_credit_pool_obj macs_pool; | |
1135 | struct ecore_rx_mode_obj rx_mode_obj; | |
1136 | struct ecore_mcast_obj mcast_obj; | |
1137 | struct ecore_rss_config_obj rss_conf_obj; | |
1138 | struct ecore_func_sp_obj func_obj; | |
1139 | ||
1140 | uint16_t fw_seq; | |
1141 | uint16_t fw_drv_pulse_wr_seq; | |
1142 | uint32_t func_stx; | |
1143 | ||
1144 | struct elink_params link_params; | |
1145 | struct elink_vars link_vars; | |
1146 | uint32_t link_cnt; | |
1147 | struct bnx2x_link_report_data last_reported_link; | |
1148 | char mac_addr_str[32]; | |
1149 | ||
1150 | uint32_t tx_ring_size; | |
1151 | uint32_t rx_ring_size; | |
1152 | int wol; | |
1153 | ||
1154 | int is_leader; | |
1155 | int recovery_state; | |
1156 | #define BNX2X_RECOVERY_DONE 1 | |
1157 | #define BNX2X_RECOVERY_INIT 2 | |
1158 | #define BNX2X_RECOVERY_WAIT 3 | |
1159 | #define BNX2X_RECOVERY_FAILED 4 | |
1160 | #define BNX2X_RECOVERY_NIC_LOADING 5 | |
1161 | ||
1162 | uint32_t rx_mode; | |
11fdf7f2 TL |
1163 | #define BNX2X_RX_MODE_NONE 0 |
1164 | #define BNX2X_RX_MODE_NORMAL 1 | |
1165 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1166 | #define BNX2X_RX_MODE_ALLMULTI_PROMISC 3 | |
1167 | #define BNX2X_RX_MODE_PROMISC 4 | |
1168 | #define BNX2X_MAX_MULTICAST 64 | |
7c673cae FG |
1169 | |
1170 | struct bnx2x_port port; | |
1171 | ||
1172 | struct cmng_init cmng; | |
1173 | ||
1174 | /* user configs */ | |
1175 | uint8_t num_queues; | |
1176 | int hc_rx_ticks; | |
1177 | int hc_tx_ticks; | |
1178 | uint32_t rx_budget; | |
1179 | int interrupt_mode; | |
1180 | #define INTR_MODE_INTX 0 | |
1181 | #define INTR_MODE_MSI 1 | |
1182 | #define INTR_MODE_MSIX 2 | |
1183 | #define INTR_MODE_SINGLE_MSIX 3 | |
1184 | int udp_rss; | |
1185 | ||
1186 | uint8_t igu_dsb_id; | |
1187 | uint8_t igu_base_sb; | |
1188 | uint8_t igu_sb_cnt; | |
1189 | uint32_t igu_base_addr; | |
1190 | uint8_t base_fw_ndsb; | |
1191 | #define DEF_SB_IGU_ID 16 | |
1192 | #define DEF_SB_ID HC_SP_SB_ID | |
1193 | ||
1194 | /* default status block */ | |
1195 | struct bnx2x_dma def_sb_dma; | |
1196 | struct host_sp_status_block *def_sb; | |
1197 | uint16_t def_idx; | |
1198 | uint16_t def_att_idx; | |
1199 | uint32_t attn_state; | |
1200 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
1201 | ||
1202 | /* general SP events - stats query, cfc delete, etc */ | |
1203 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
1204 | /* EQ completions */ | |
1205 | #define HC_SP_INDEX_EQ_CONS 7 | |
1206 | /* FCoE L2 connection completions */ | |
1207 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 | |
1208 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 | |
1209 | /* iSCSI L2 */ | |
1210 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
1211 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
1212 | ||
1213 | /* event queue */ | |
1214 | struct bnx2x_dma eq_dma; | |
1215 | union event_ring_elem *eq; | |
1216 | uint16_t eq_prod; | |
1217 | uint16_t eq_cons; | |
1218 | uint16_t *eq_cons_sb; | |
1219 | #define NUM_EQ_PAGES 1 /* must be a power of 2 */ | |
1220 | #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem)) | |
1221 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
1222 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
1223 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
1224 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
1225 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
1226 | #define NEXT_EQ_IDX(x) \ | |
1227 | ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ | |
1228 | ((x) + 2) : ((x) + 1)) | |
1229 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
1230 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
1231 | ||
1232 | /* slow path */ | |
1233 | struct bnx2x_dma sp_dma; | |
1234 | struct bnx2x_slowpath *sp; | |
1235 | unsigned long sp_state; | |
1236 | ||
1237 | /* slow path queue */ | |
1238 | struct bnx2x_dma spq_dma; | |
1239 | struct eth_spe *spq; | |
1240 | #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe)) | |
1241 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1242 | #define MAX_SPQ_PENDING 8 | |
1243 | ||
1244 | uint16_t spq_prod_idx; | |
1245 | struct eth_spe *spq_prod_bd; | |
1246 | struct eth_spe *spq_last_bd; | |
1247 | uint16_t *dsb_sp_prod; | |
1248 | ||
1249 | volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ | |
1250 | volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ | |
1251 | ||
1252 | /* fw decompression buffer */ | |
1253 | struct bnx2x_dma gz_buf_dma; | |
1254 | void *gz_buf; | |
1255 | uint32_t gz_outlen; | |
1256 | #define GUNZIP_BUF(sc) (sc->gz_buf) | |
1257 | #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) | |
11fdf7f2 | 1258 | #define GUNZIP_PHYS(sc) (rte_iova_t)(sc->gz_buf_dma.paddr) |
7c673cae FG |
1259 | #define FW_BUF_SIZE 0x40000 |
1260 | ||
1261 | struct raw_op *init_ops; | |
1262 | uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ | |
1263 | uint32_t *init_data; /* data blob, 32 bit granularity */ | |
1264 | uint32_t init_mode_flags; | |
1265 | #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) | |
1266 | /* PRAM blobs - raw data */ | |
1267 | const uint8_t *tsem_int_table_data; | |
1268 | const uint8_t *tsem_pram_data; | |
1269 | const uint8_t *usem_int_table_data; | |
1270 | const uint8_t *usem_pram_data; | |
1271 | const uint8_t *xsem_int_table_data; | |
1272 | const uint8_t *xsem_pram_data; | |
1273 | const uint8_t *csem_int_table_data; | |
1274 | const uint8_t *csem_pram_data; | |
1275 | #define INIT_OPS(sc) (sc->init_ops) | |
1276 | #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) | |
1277 | #define INIT_DATA(sc) (sc->init_data) | |
1278 | #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) | |
1279 | #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) | |
1280 | #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) | |
1281 | #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) | |
1282 | #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) | |
1283 | #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) | |
1284 | #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) | |
1285 | #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) | |
1286 | ||
1287 | #define PHY_FW_VER_LEN 20 | |
1288 | char fw_ver[32]; | |
1289 | ||
1290 | /* ILT | |
1291 | * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB | |
1292 | * context size we need 8 ILT entries. | |
1293 | */ | |
1294 | #define ILT_MAX_L2_LINES 8 | |
1295 | struct hw_context context[ILT_MAX_L2_LINES]; | |
1296 | struct ecore_ilt *ilt; | |
1297 | #define ILT_MAX_LINES 256 | |
1298 | ||
1299 | /* max supported number of RSS queues: IGU SBs minus one for CNIC */ | |
1300 | #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) | |
1301 | /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ | |
1302 | #define BNX2X_L2_MAX_CID(sc) \ | |
1303 | (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) | |
1304 | #define BNX2X_L2_CID_COUNT(sc) \ | |
1305 | (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) | |
1306 | #define L2_ILT_LINES(sc) \ | |
1307 | (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) | |
1308 | ||
1309 | int qm_cid_count; | |
1310 | ||
1311 | uint8_t dropless_fc; | |
1312 | ||
1313 | /* total number of FW statistics requests */ | |
1314 | uint8_t fw_stats_num; | |
1315 | /* | |
1316 | * This is a memory buffer that will contain both statistics ramrod | |
1317 | * request and data. | |
1318 | */ | |
1319 | struct bnx2x_dma fw_stats_dma; | |
1320 | /* | |
1321 | * FW statistics request shortcut (points at the beginning of fw_stats | |
1322 | * buffer). | |
1323 | */ | |
1324 | int fw_stats_req_size; | |
1325 | struct bnx2x_fw_stats_req *fw_stats_req; | |
11fdf7f2 | 1326 | rte_iova_t fw_stats_req_mapping; |
7c673cae FG |
1327 | /* |
1328 | * FW statistics data shortcut (points at the beginning of fw_stats | |
1329 | * buffer + fw_stats_req_size). | |
1330 | */ | |
1331 | int fw_stats_data_size; | |
1332 | struct bnx2x_fw_stats_data *fw_stats_data; | |
11fdf7f2 | 1333 | rte_iova_t fw_stats_data_mapping; |
7c673cae FG |
1334 | |
1335 | /* tracking a pending STAT_QUERY ramrod */ | |
1336 | uint16_t stats_pending; | |
1337 | /* number of completed statistics ramrods */ | |
1338 | uint16_t stats_comp; | |
1339 | uint16_t stats_counter; | |
1340 | uint8_t stats_init; | |
1341 | int stats_state; | |
1342 | ||
1343 | struct bnx2x_eth_stats eth_stats; | |
1344 | struct host_func_stats func_stats; | |
1345 | struct bnx2x_eth_stats_old eth_stats_old; | |
1346 | struct bnx2x_net_stats_old net_stats_old; | |
1347 | struct bnx2x_fw_port_stats_old fw_stats_old; | |
1348 | ||
1349 | struct dmae_command stats_dmae; /* used by dmae command loader */ | |
1350 | int executer_idx; | |
1351 | ||
1352 | int mtu; | |
1353 | ||
1354 | /* DCB support on/off */ | |
1355 | int dcb_state; | |
1356 | #define BNX2X_DCB_STATE_OFF 0 | |
1357 | #define BNX2X_DCB_STATE_ON 1 | |
1358 | /* DCBX engine mode */ | |
1359 | int dcbx_enabled; | |
1360 | #define BNX2X_DCBX_ENABLED_OFF 0 | |
1361 | #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 | |
1362 | #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 | |
1363 | #define BNX2X_DCBX_ENABLED_INVALID -1 | |
1364 | ||
1365 | uint8_t cnic_support; | |
1366 | uint8_t cnic_enabled; | |
1367 | uint8_t cnic_loaded; | |
1368 | #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ | |
1369 | #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ | |
1370 | #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ | |
1371 | ||
1372 | /* multiple tx classes of service */ | |
1373 | uint8_t max_cos; | |
1374 | #define BNX2X_MAX_PRIORITY 8 | |
1375 | /* priority to cos mapping */ | |
1376 | uint8_t prio_to_cos[BNX2X_MAX_PRIORITY]; | |
1377 | ||
1378 | int panic; | |
f67539c2 TL |
1379 | /* Array of Multicast addrs */ |
1380 | struct rte_ether_addr mc_addrs[VF_MAX_MULTICAST_PER_VF]; | |
1381 | /* Multicast mac addresses number */ | |
1382 | uint16_t mc_addrs_num; | |
7c673cae FG |
1383 | }; /* struct bnx2x_softc */ |
1384 | ||
1385 | /* IOCTL sub-commands for edebug and firmware upgrade */ | |
1386 | #define BNX2X_IOC_RD_NVRAM 1 | |
1387 | #define BNX2X_IOC_WR_NVRAM 2 | |
1388 | #define BNX2X_IOC_STATS_SHOW_NUM 3 | |
1389 | #define BNX2X_IOC_STATS_SHOW_STR 4 | |
1390 | #define BNX2X_IOC_STATS_SHOW_CNT 5 | |
1391 | ||
1392 | struct bnx2x_nvram_data { | |
1393 | uint32_t op; /* ioctl sub-command */ | |
1394 | uint32_t offset; | |
1395 | uint32_t len; | |
1396 | uint32_t value[1]; /* variable */ | |
1397 | }; | |
1398 | ||
1399 | union bnx2x_stats_show_data { | |
1400 | uint32_t op; /* ioctl sub-command */ | |
1401 | ||
1402 | struct { | |
1403 | uint32_t num; /* return number of stats */ | |
1404 | uint32_t len; /* length of each string item */ | |
1405 | } desc; | |
1406 | ||
1407 | /* variable length... */ | |
1408 | char str[1]; /* holds names of desc.num stats, each desc.len in length */ | |
1409 | ||
1410 | /* variable length... */ | |
1411 | uint64_t stats[1]; /* holds all stats */ | |
1412 | }; | |
1413 | ||
1414 | /* function init flags */ | |
1415 | #define FUNC_FLG_RSS 0x0001 | |
1416 | #define FUNC_FLG_STATS 0x0002 | |
1417 | /* FUNC_FLG_UNMATCHED 0x0004 */ | |
1418 | #define FUNC_FLG_SPQ 0x0010 | |
1419 | #define FUNC_FLG_LEADING 0x0020 /* PF only */ | |
1420 | ||
1421 | struct bnx2x_func_init_params { | |
11fdf7f2 TL |
1422 | rte_iova_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ |
1423 | rte_iova_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ | |
7c673cae FG |
1424 | uint16_t func_flgs; |
1425 | uint16_t func_id; /* abs function id */ | |
1426 | uint16_t pf_id; | |
1427 | uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ | |
1428 | }; | |
1429 | ||
1430 | /* memory resources reside at BARs 0, 2, 4 */ | |
1431 | /* Run `pciconf -lb` to see mappings */ | |
1432 | #define BAR0 0 | |
1433 | #define BAR1 2 | |
1434 | #define BAR2 4 | |
1435 | ||
1436 | static inline void | |
1437 | bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) | |
1438 | { | |
9f95a23c | 1439 | PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x", |
7c673cae | 1440 | (unsigned long)offset, val); |
11fdf7f2 | 1441 | rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); |
7c673cae FG |
1442 | } |
1443 | ||
1444 | static inline void | |
1445 | bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) | |
1446 | { | |
1447 | #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC | |
1448 | if ((offset % 2) != 0) | |
9f95a23c | 1449 | PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx", |
7c673cae FG |
1450 | (unsigned long)offset); |
1451 | #endif | |
9f95a23c | 1452 | PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x", |
7c673cae | 1453 | (unsigned long)offset, val); |
11fdf7f2 TL |
1454 | rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); |
1455 | ||
7c673cae FG |
1456 | } |
1457 | ||
1458 | static inline void | |
1459 | bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) | |
1460 | { | |
1461 | #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC | |
1462 | if ((offset % 4) != 0) | |
9f95a23c | 1463 | PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx", |
7c673cae FG |
1464 | (unsigned long)offset); |
1465 | #endif | |
1466 | ||
9f95a23c | 1467 | PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", |
7c673cae | 1468 | (unsigned long)offset, val); |
11fdf7f2 | 1469 | rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); |
7c673cae FG |
1470 | } |
1471 | ||
1472 | static inline uint8_t | |
1473 | bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) | |
1474 | { | |
1475 | uint8_t val; | |
1476 | ||
11fdf7f2 | 1477 | val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset); |
9f95a23c | 1478 | PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x", |
7c673cae FG |
1479 | (unsigned long)offset, val); |
1480 | ||
1481 | return val; | |
1482 | } | |
1483 | ||
1484 | static inline uint16_t | |
1485 | bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) | |
1486 | { | |
1487 | uint16_t val; | |
1488 | ||
1489 | #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC | |
1490 | if ((offset % 2) != 0) | |
9f95a23c | 1491 | PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx", |
7c673cae FG |
1492 | (unsigned long)offset); |
1493 | #endif | |
1494 | ||
11fdf7f2 | 1495 | val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset)); |
9f95a23c | 1496 | PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", |
7c673cae FG |
1497 | (unsigned long)offset, val); |
1498 | ||
1499 | return val; | |
1500 | } | |
1501 | ||
1502 | static inline uint32_t | |
1503 | bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) | |
1504 | { | |
1505 | uint32_t val; | |
1506 | ||
1507 | #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC | |
1508 | if ((offset % 4) != 0) | |
9f95a23c | 1509 | PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx", |
7c673cae FG |
1510 | (unsigned long)offset); |
1511 | #endif | |
1512 | ||
11fdf7f2 | 1513 | val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset)); |
9f95a23c | 1514 | PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", |
7c673cae FG |
1515 | (unsigned long)offset, val); |
1516 | ||
1517 | return val; | |
1518 | } | |
1519 | ||
1520 | #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset)) | |
1521 | ||
1522 | #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset)) | |
1523 | #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset)) | |
1524 | #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset)) | |
1525 | ||
1526 | #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val) | |
1527 | #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val) | |
1528 | #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val) | |
1529 | ||
1530 | #define REG_RD(sc, offset) REG_RD32(sc, offset) | |
1531 | #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) | |
1532 | ||
1533 | #define BNX2X_SP(sc, var) (&(sc)->sp->var) | |
1534 | #define BNX2X_SP_MAPPING(sc, var) \ | |
1535 | (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var)) | |
1536 | ||
1537 | #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var) | |
1538 | #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) | |
1539 | ||
1540 | #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var) | |
1541 | ||
1542 | #define REG_RD_DMAE(sc, offset, valp, len32) \ | |
1543 | do { \ | |
1544 | (void)bnx2x_read_dmae(sc, offset, len32); \ | |
11fdf7f2 | 1545 | rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \ |
7c673cae FG |
1546 | } while (0) |
1547 | ||
1548 | #define REG_WR_DMAE(sc, offset, valp, len32) \ | |
1549 | do { \ | |
11fdf7f2 | 1550 | rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \ |
7c673cae FG |
1551 | (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \ |
1552 | } while (0) | |
1553 | ||
1554 | #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ | |
1555 | REG_WR_DMAE(sc, offset, valp, len32) | |
1556 | ||
1557 | #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ | |
1558 | REG_RD_DMAE(sc, offset, valp, len32) | |
1559 | ||
1560 | #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ | |
1561 | do { \ | |
1562 | /* if (le32_swap) { */ \ | |
1563 | /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \ | |
1564 | /* } */ \ | |
1565 | rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ | |
1566 | ecore_write_big_buf_wb(sc, addr, len32); \ | |
1567 | } while (0) | |
1568 | ||
1569 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ | |
1570 | #define BNX2X_DB_SHIFT 7 /* 128 bytes */ | |
1571 | #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) | |
1572 | #error "Minimum DB doorbell stride is 8" | |
1573 | #endif | |
1574 | #define DPM_TRIGGER_TYPE 0x40 | |
1575 | ||
1576 | /* Doorbell macro */ | |
11fdf7f2 | 1577 | #define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar)) |
7c673cae | 1578 | |
11fdf7f2 | 1579 | #define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar) |
7c673cae FG |
1580 | |
1581 | #define DOORBELL_ADDR(sc, offset) \ | |
1582 | (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset))) | |
1583 | ||
1584 | #define DOORBELL(sc, cid, val) \ | |
1585 | if (IS_PF(sc)) \ | |
1586 | BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \ | |
1587 | else \ | |
1588 | BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \ | |
1589 | ||
1590 | #define SHMEM_ADDR(sc, field) \ | |
1591 | (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) | |
1592 | #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) | |
1593 | #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) | |
1594 | #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) | |
1595 | ||
1596 | #define SHMEM2_ADDR(sc, field) \ | |
1597 | (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) | |
1598 | #define SHMEM2_HAS(sc, field) \ | |
1599 | (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ | |
1600 | offsetof(struct shmem2_region, field))) | |
1601 | #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) | |
1602 | #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) | |
1603 | ||
1604 | #define MFCFG_ADDR(sc, field) \ | |
1605 | (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) | |
1606 | #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) | |
1607 | #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) | |
1608 | #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) | |
1609 | ||
1610 | /* DMAE command defines */ | |
1611 | ||
1612 | #define DMAE_TIMEOUT -1 | |
1613 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1614 | #define DMAE_NOT_RDY -3 | |
1615 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1616 | ||
1617 | #define DMAE_SRC_PCI 0 | |
1618 | #define DMAE_SRC_GRC 1 | |
1619 | ||
1620 | #define DMAE_DST_NONE 0 | |
1621 | #define DMAE_DST_PCI 1 | |
1622 | #define DMAE_DST_GRC 2 | |
1623 | ||
1624 | #define DMAE_COMP_PCI 0 | |
1625 | #define DMAE_COMP_GRC 1 | |
1626 | ||
1627 | #define DMAE_COMP_REGULAR 0 | |
1628 | #define DMAE_COM_SET_ERR 1 | |
1629 | ||
1630 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT) | |
1631 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT) | |
1632 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT) | |
1633 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT) | |
1634 | ||
1635 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT) | |
1636 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT) | |
1637 | ||
1638 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1639 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1640 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1641 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1642 | ||
1643 | #define DMAE_CMD_PORT_0 0 | |
1644 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
1645 | ||
1646 | #define DMAE_SRC_PF 0 | |
1647 | #define DMAE_SRC_VF 1 | |
1648 | ||
1649 | #define DMAE_DST_PF 0 | |
1650 | #define DMAE_DST_VF 1 | |
1651 | ||
1652 | #define DMAE_C_SRC 0 | |
1653 | #define DMAE_C_DST 1 | |
1654 | ||
1655 | #define DMAE_LEN32_RD_MAX 0x80 | |
1656 | #define DMAE_LEN32_WR_MAX(sc) 0x2000 | |
1657 | ||
1658 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ | |
1659 | ||
1660 | #define MAX_DMAE_C_PER_PORT 8 | |
1661 | #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) | |
1662 | #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) | |
1663 | ||
1664 | static const uint32_t dmae_reg_go_c[] = { | |
1665 | DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, | |
1666 | DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, | |
1667 | DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, | |
1668 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 | |
1669 | }; | |
1670 | ||
1671 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1672 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1673 | #define GPIO_2_FUNC (1L << 10) | |
1674 | #define GPIO_3_FUNC (1L << 11) | |
1675 | #define GPIO_4_FUNC (1L << 12) | |
1676 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1677 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1678 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1679 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1680 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1681 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1682 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1683 | #define ATTENTION_ID 4 | |
1684 | ||
1685 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ | |
1686 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
1687 | ||
1688 | #define MAX_IGU_ATTN_ACK_TO 100 | |
1689 | ||
1690 | #define STORM_ASSERT_ARRAY_SIZE 50 | |
1691 | ||
1692 | #define BNX2X_PMF_LINK_ASSERT(sc) \ | |
1693 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) | |
1694 | ||
1695 | #define BNX2X_MC_ASSERT_BITS \ | |
1696 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1697 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1698 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1699 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1700 | ||
1701 | #define BNX2X_MCP_ASSERT \ | |
1702 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1703 | ||
1704 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) | |
1705 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1706 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1707 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1708 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1709 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1710 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1711 | ||
f67539c2 TL |
1712 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1713 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1714 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1715 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1716 | AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ | |
1717 | AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) | |
1718 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ | |
1719 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ | |
1720 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1721 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1722 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ | |
1723 | AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ | |
1724 | AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) | |
1725 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1726 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1727 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1728 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1729 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1730 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1731 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1732 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1733 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1734 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1735 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1736 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
1737 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ | |
1738 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ | |
1739 | AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ | |
1740 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1741 | AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ | |
1742 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
1743 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ | |
1744 | AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ | |
1745 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
1746 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ | |
1747 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1748 | AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ | |
1749 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1750 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1751 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ | |
1752 | AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) | |
1753 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1754 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1755 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1756 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1757 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1758 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
1759 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ | |
1760 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ | |
1761 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1762 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1763 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1764 | AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ | |
1765 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1766 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1767 | ||
1768 | #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \ | |
1769 | (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ | |
1770 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
1771 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) | |
1772 | ||
1773 | #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \ | |
1774 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
1775 | ||
1776 | #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ | |
1777 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) | |
1778 | ||
7c673cae FG |
1779 | #define MULTI_MASK 0x7f |
1780 | ||
1781 | #define PFS_PER_PORT(sc) \ | |
1782 | ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) | |
1783 | #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) | |
1784 | ||
1785 | #define FIRST_ABS_FUNC_IN_PORT(sc) \ | |
1786 | ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ | |
1787 | PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) | |
1788 | ||
1789 | #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ | |
1790 | for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ | |
1791 | (i) < MAX_FUNC_NUM; \ | |
1792 | (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) | |
1793 | ||
1794 | #define BNX2X_SWCID_SHIFT 17 | |
1795 | #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) | |
1796 | ||
1797 | #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK) | |
1798 | #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
1799 | ||
1800 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) | |
1801 | #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) | |
1802 | #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) | |
1803 | #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) | |
1804 | #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) | |
1805 | ||
1806 | /* must be used on a CID before placing it on a HW ring */ | |
1807 | #define HW_CID(sc, x) \ | |
1808 | ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x)) | |
1809 | ||
1810 | #define SPEED_10 10 | |
1811 | #define SPEED_100 100 | |
1812 | #define SPEED_1000 1000 | |
1813 | #define SPEED_2500 2500 | |
1814 | #define SPEED_10000 10000 | |
1815 | ||
1816 | #define PCI_PM_D0 1 | |
1817 | #define PCI_PM_D3hot 2 | |
1818 | ||
1819 | int bnx2x_test_bit(int nr, volatile unsigned long * addr); | |
1820 | void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr); | |
1821 | void bnx2x_clear_bit(int nr, volatile unsigned long * addr); | |
1822 | int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr); | |
1823 | int bnx2x_cmpxchg(volatile int *addr, int old, int new); | |
1824 | ||
1825 | int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, | |
1826 | struct bnx2x_dma *dma, const char *msg, uint32_t align); | |
9f95a23c | 1827 | void bnx2x_dma_free(struct bnx2x_dma *dma); |
7c673cae FG |
1828 | uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); |
1829 | uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode); | |
1830 | uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type, | |
1831 | uint8_t dst_type, uint8_t with_comp, | |
1832 | uint8_t comp_type); | |
1833 | void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx); | |
1834 | void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32); | |
11fdf7f2 | 1835 | void bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, |
7c673cae FG |
1836 | uint32_t dst_addr, uint32_t len32); |
1837 | void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt, | |
1838 | uint32_t cid); | |
1839 | void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id, | |
1840 | uint8_t sb_index, uint8_t disable, | |
1841 | uint16_t usec); | |
1842 | ||
1843 | int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, | |
1844 | uint32_t data_hi, uint32_t data_lo, int cmd_type); | |
1845 | ||
1846 | void ecore_init_e1h_firmware(struct bnx2x_softc *sc); | |
1847 | void ecore_init_e2_firmware(struct bnx2x_softc *sc); | |
1848 | ||
1849 | void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, | |
1850 | size_t size, uint32_t *data); | |
1851 | ||
1852 | #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); | |
1853 | #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) | |
1854 | ||
1855 | #define BNX2X_MAC_FMT "%pM" | |
1856 | #define BNX2X_MAC_PRN_LIST(mac) (mac) | |
1857 | ||
1858 | /***********/ | |
1859 | /* INLINES */ | |
1860 | /***********/ | |
1861 | ||
1862 | static inline uint32_t | |
1863 | reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait) | |
1864 | { | |
1865 | uint32_t val; | |
1866 | do { | |
1867 | val = REG_RD(sc, reg); | |
1868 | if (val == expected) { | |
1869 | break; | |
1870 | } | |
1871 | ms -= wait; | |
1872 | DELAY(wait * 1000); | |
1873 | } while (ms > 0); | |
1874 | ||
1875 | return val; | |
1876 | } | |
1877 | ||
1878 | static inline void | |
1879 | bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp) | |
1880 | { | |
1881 | mb(); /* status block is written to by the chip */ | |
1882 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; | |
1883 | } | |
1884 | ||
1885 | static inline void | |
1886 | bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment, | |
1887 | uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr) | |
1888 | { | |
1889 | struct igu_regular cmd_data = {0}; | |
1890 | ||
1891 | cmd_data.sb_id_and_flags = | |
1892 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
1893 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
1894 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
1895 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
1896 | ||
1897 | REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); | |
1898 | ||
1899 | /* Make sure that ACK is written */ | |
1900 | mb(); | |
1901 | } | |
1902 | ||
1903 | static inline void | |
1904 | bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm, | |
1905 | uint16_t index, uint8_t op, uint8_t update) | |
1906 | { | |
1907 | uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 + | |
1908 | COMMAND_REG_INT_ACK); | |
f67539c2 TL |
1909 | struct igu_ack_register igu_ack; |
1910 | uint32_t *val = NULL; | |
7c673cae | 1911 | |
f67539c2 TL |
1912 | igu_ack.status_block_index = index; |
1913 | igu_ack.sb_id_and_flags = | |
7c673cae FG |
1914 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | |
1915 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
1916 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
1917 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
1918 | ||
f67539c2 TL |
1919 | val = (uint32_t *)&igu_ack; |
1920 | REG_WR(sc, hc_addr, *val); | |
7c673cae FG |
1921 | |
1922 | /* Make sure that ACK is written */ | |
1923 | mb(); | |
1924 | } | |
1925 | ||
1926 | static inline uint32_t | |
1927 | bnx2x_hc_ack_int(struct bnx2x_softc *sc) | |
1928 | { | |
1929 | uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 + | |
1930 | COMMAND_REG_SIMD_MASK); | |
1931 | uint32_t result = REG_RD(sc, hc_addr); | |
1932 | ||
1933 | mb(); | |
1934 | return result; | |
1935 | } | |
1936 | ||
1937 | static inline uint32_t | |
1938 | bnx2x_igu_ack_int(struct bnx2x_softc *sc) | |
1939 | { | |
1940 | uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8); | |
1941 | uint32_t result = REG_RD(sc, igu_addr); | |
1942 | ||
1943 | /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x", | |
1944 | result, igu_addr); */ | |
1945 | ||
1946 | mb(); | |
1947 | return result; | |
1948 | } | |
1949 | ||
1950 | static inline uint32_t | |
1951 | bnx2x_ack_int(struct bnx2x_softc *sc) | |
1952 | { | |
1953 | mb(); | |
1954 | if (sc->devinfo.int_block == INT_BLOCK_HC) { | |
1955 | return bnx2x_hc_ack_int(sc); | |
1956 | } else { | |
1957 | return bnx2x_igu_ack_int(sc); | |
1958 | } | |
1959 | } | |
1960 | ||
1961 | static inline int | |
1962 | func_by_vn(struct bnx2x_softc *sc, int vn) | |
1963 | { | |
1964 | return 2 * vn + SC_PORT(sc); | |
1965 | } | |
1966 | ||
1967 | /* | |
1968 | * send notification to other functions. | |
1969 | */ | |
1970 | static inline void | |
1971 | bnx2x_link_sync_notify(struct bnx2x_softc *sc) | |
1972 | { | |
1973 | int func, vn; | |
1974 | ||
1975 | /* Set the attention towards other drivers on the same port */ | |
1976 | for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { | |
1977 | if (vn == SC_VN(sc)) | |
1978 | continue; | |
1979 | ||
1980 | func = func_by_vn(sc, vn); | |
1981 | REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1982 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1); | |
1983 | } | |
1984 | } | |
1985 | ||
1986 | /* | |
1987 | * Statistics ID are global per chip/path, while Client IDs for E1x | |
1988 | * are per port. | |
1989 | */ | |
1990 | static inline uint8_t | |
1991 | bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
1992 | { | |
1993 | struct bnx2x_softc *sc = fp->sc; | |
1994 | ||
1995 | if (!CHIP_IS_E1x(sc)) { | |
1996 | return fp->cl_id; | |
1997 | } | |
1998 | ||
1999 | return fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x; | |
2000 | } | |
2001 | ||
2002 | int bnx2x_init(struct bnx2x_softc *sc); | |
2003 | void bnx2x_load_firmware(struct bnx2x_softc *sc); | |
2004 | int bnx2x_attach(struct bnx2x_softc *sc); | |
2005 | int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link); | |
2006 | int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc); | |
2007 | int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc); | |
2008 | void bnx2x_free_ilt_mem(struct bnx2x_softc *sc); | |
2009 | void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count); | |
2010 | int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0); | |
2011 | uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp); | |
2012 | void bnx2x_print_adapter_info(struct bnx2x_softc *sc); | |
9f95a23c TL |
2013 | void bnx2x_print_device_info(struct bnx2x_softc *sc); |
2014 | int bnx2x_intr_legacy(struct bnx2x_softc *sc); | |
7c673cae FG |
2015 | void bnx2x_link_status_update(struct bnx2x_softc *sc); |
2016 | int bnx2x_complete_sp(struct bnx2x_softc *sc); | |
2017 | int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc); | |
2018 | void bnx2x_periodic_callout(struct bnx2x_softc *sc); | |
11fdf7f2 | 2019 | void bnx2x_periodic_stop(void *param); |
7c673cae FG |
2020 | |
2021 | int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count); | |
2022 | void bnx2x_vf_close(struct bnx2x_softc *sc); | |
2023 | int bnx2x_vf_init(struct bnx2x_softc *sc); | |
2024 | void bnx2x_vf_unload(struct bnx2x_softc *sc); | |
2025 | int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, | |
2026 | int leading); | |
2027 | void bnx2x_free_hsi_mem(struct bnx2x_softc *sc); | |
2028 | int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc); | |
2029 | int bnx2x_check_bull(struct bnx2x_softc *sc); | |
2030 | ||
2031 | //#define BNX2X_PULSE | |
2032 | ||
2033 | #define BNX2X_PCI_CAP 1 | |
2034 | #define BNX2X_PCI_ECAP 2 | |
2035 | ||
2036 | static inline struct bnx2x_pci_cap* | |
2037 | pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type) | |
2038 | { | |
2039 | struct bnx2x_pci_cap *cap = sc->pci_caps; | |
2040 | ||
2041 | while (cap) { | |
2042 | if (cap->id == id && cap->type == type) | |
2043 | return cap; | |
2044 | cap = cap->next; | |
2045 | } | |
2046 | ||
2047 | return NULL; | |
2048 | } | |
2049 | ||
2050 | static inline void | |
2051 | bnx2x_set_rx_mode(struct bnx2x_softc *sc) | |
2052 | { | |
2053 | if (sc->state == BNX2X_STATE_OPEN) { | |
2054 | if (IS_PF(sc)) { | |
2055 | bnx2x_set_storm_rx_mode(sc); | |
2056 | } else { | |
2057 | sc->rx_mode = BNX2X_RX_MODE_PROMISC; | |
2058 | bnx2x_vf_set_rx_mode(sc); | |
2059 | } | |
2060 | } else { | |
9f95a23c | 2061 | PMD_DRV_LOG(INFO, sc, "Card is not ready to change mode"); |
7c673cae FG |
2062 | } |
2063 | } | |
2064 | ||
2065 | static inline int pci_read(struct bnx2x_softc *sc, size_t addr, | |
2066 | void *val, uint8_t size) | |
2067 | { | |
11fdf7f2 | 2068 | if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) { |
9f95a23c | 2069 | PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space"); |
7c673cae FG |
2070 | return ENXIO; |
2071 | } | |
2072 | ||
2073 | return 0; | |
2074 | } | |
2075 | ||
2076 | static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val) | |
2077 | { | |
2078 | uint16_t val16 = val; | |
2079 | ||
11fdf7f2 | 2080 | if (rte_pci_write_config(sc->pci_dev, &val16, |
7c673cae | 2081 | sizeof(val16), addr) <= 0) { |
9f95a23c | 2082 | PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space"); |
7c673cae FG |
2083 | return ENXIO; |
2084 | } | |
2085 | ||
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val) | |
2090 | { | |
2091 | uint32_t val32 = val; | |
11fdf7f2 | 2092 | if (rte_pci_write_config(sc->pci_dev, &val32, |
7c673cae | 2093 | sizeof(val32), addr) <= 0) { |
9f95a23c | 2094 | PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space"); |
7c673cae FG |
2095 | return ENXIO; |
2096 | } | |
2097 | ||
2098 | return 0; | |
2099 | } | |
2100 | ||
2101 | #endif /* __BNX2X_H__ */ |