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1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(c) 2001 - 2015 Intel Corporation | |
3 | */ | |
7c673cae FG |
4 | |
5 | #ifndef _E1000_82575_H_ | |
6 | #define _E1000_82575_H_ | |
7 | ||
8 | #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ | |
9 | (ID_LED_DEF1_DEF2 << 8) | \ | |
10 | (ID_LED_DEF1_DEF2 << 4) | \ | |
11 | (ID_LED_OFF1_ON2)) | |
12 | /* | |
13 | * Receive Address Register Count | |
14 | * Number of high/low register pairs in the RAR. The RAR (Receive Address | |
15 | * Registers) holds the directed and multicast addresses that we monitor. | |
16 | * These entries are also used for MAC-based filtering. | |
17 | */ | |
18 | /* | |
19 | * For 82576, there are an additional set of RARs that begin at an offset | |
20 | * separate from the first set of RARs. | |
21 | */ | |
22 | #define E1000_RAR_ENTRIES_82575 16 | |
23 | #define E1000_RAR_ENTRIES_82576 24 | |
24 | #define E1000_RAR_ENTRIES_82580 24 | |
25 | #define E1000_RAR_ENTRIES_I350 32 | |
26 | #define E1000_SW_SYNCH_MB 0x00000100 | |
27 | #define E1000_STAT_DEV_RST_SET 0x00100000 | |
28 | #define E1000_CTRL_DEV_RST 0x20000000 | |
29 | ||
30 | #ifdef E1000_BIT_FIELDS | |
31 | struct e1000_adv_data_desc { | |
32 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ | |
33 | union { | |
34 | u32 data; | |
35 | struct { | |
36 | u32 datalen:16; /* Data buffer length */ | |
37 | u32 rsvd:4; | |
38 | u32 dtyp:4; /* Descriptor type */ | |
39 | u32 dcmd:8; /* Descriptor command */ | |
40 | } config; | |
41 | } lower; | |
42 | union { | |
43 | u32 data; | |
44 | struct { | |
45 | u32 status:4; /* Descriptor status */ | |
46 | u32 idx:4; | |
47 | u32 popts:6; /* Packet Options */ | |
48 | u32 paylen:18; /* Payload length */ | |
49 | } options; | |
50 | } upper; | |
51 | }; | |
52 | ||
53 | #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ | |
54 | #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ | |
55 | #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ | |
56 | #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ | |
57 | #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ | |
58 | #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ | |
59 | #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ | |
60 | #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ | |
61 | #define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ | |
62 | #define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ | |
63 | #define E1000_ADV_DCMD_RS 0x8 /* Report Status */ | |
64 | #define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ | |
65 | #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ | |
66 | /* Extended Device Control */ | |
67 | #define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ | |
68 | ||
69 | struct e1000_adv_context_desc { | |
70 | union { | |
71 | u32 ip_config; | |
72 | struct { | |
73 | u32 iplen:9; | |
74 | u32 maclen:7; | |
75 | u32 vlan_tag:16; | |
76 | } fields; | |
77 | } ip_setup; | |
78 | u32 seq_num; | |
79 | union { | |
80 | u64 l4_config; | |
81 | struct { | |
82 | u32 mkrloc:9; | |
83 | u32 tucmd:11; | |
84 | u32 dtyp:4; | |
85 | u32 adv:8; | |
86 | u32 rsvd:4; | |
87 | u32 idx:4; | |
88 | u32 l4len:8; | |
89 | u32 mss:16; | |
90 | } fields; | |
91 | } l4_setup; | |
92 | }; | |
93 | #endif | |
94 | ||
95 | /* SRRCTL bit definitions */ | |
96 | #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ | |
97 | #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 | |
98 | #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ | |
99 | #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 | |
100 | #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 | |
101 | #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 | |
102 | #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 | |
103 | #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 | |
104 | #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 | |
105 | #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 | |
106 | #define E1000_SRRCTL_TIMESTAMP 0x40000000 | |
107 | #define E1000_SRRCTL_DROP_EN 0x80000000 | |
108 | ||
109 | #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F | |
110 | #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 | |
111 | ||
112 | #define E1000_TX_HEAD_WB_ENABLE 0x1 | |
113 | #define E1000_TX_SEQNUM_WB_ENABLE 0x2 | |
114 | ||
115 | #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 | |
116 | #define E1000_MRQC_ENABLE_VMDQ 0x00000003 | |
117 | #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 | |
118 | #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 | |
119 | #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 | |
120 | #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 | |
121 | #define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 | |
122 | ||
123 | #define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 | |
124 | #define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \ | |
125 | E1000_VMRCTL_MIRROR_PORT_SHIFT) | |
126 | #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) | |
127 | #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) | |
128 | #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) | |
129 | ||
130 | #define E1000_EICR_TX_QUEUE ( \ | |
131 | E1000_EICR_TX_QUEUE0 | \ | |
132 | E1000_EICR_TX_QUEUE1 | \ | |
133 | E1000_EICR_TX_QUEUE2 | \ | |
134 | E1000_EICR_TX_QUEUE3) | |
135 | ||
136 | #define E1000_EICR_RX_QUEUE ( \ | |
137 | E1000_EICR_RX_QUEUE0 | \ | |
138 | E1000_EICR_RX_QUEUE1 | \ | |
139 | E1000_EICR_RX_QUEUE2 | \ | |
140 | E1000_EICR_RX_QUEUE3) | |
141 | ||
142 | #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE | |
143 | #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE | |
144 | ||
145 | #define EIMS_ENABLE_MASK ( \ | |
146 | E1000_EIMS_RX_QUEUE | \ | |
147 | E1000_EIMS_TX_QUEUE | \ | |
148 | E1000_EIMS_TCP_TIMER | \ | |
149 | E1000_EIMS_OTHER) | |
150 | ||
151 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ | |
152 | #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ | |
153 | #define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ | |
154 | #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ | |
155 | #define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ | |
156 | #define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ | |
157 | #define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ | |
158 | #define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ | |
159 | #define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ | |
160 | #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ | |
161 | #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ | |
162 | ||
163 | /* Receive Descriptor - Advanced */ | |
164 | union e1000_adv_rx_desc { | |
165 | struct { | |
166 | __le64 pkt_addr; /* Packet buffer address */ | |
167 | __le64 hdr_addr; /* Header buffer address */ | |
168 | } read; | |
169 | struct { | |
170 | struct { | |
171 | union { | |
172 | __le32 data; | |
173 | struct { | |
174 | __le16 pkt_info; /*RSS type, Pkt type*/ | |
175 | /* Split Header, header buffer len */ | |
176 | __le16 hdr_info; | |
177 | } hs_rss; | |
178 | } lo_dword; | |
179 | union { | |
180 | __le32 rss; /* RSS Hash */ | |
181 | struct { | |
182 | __le16 ip_id; /* IP id */ | |
183 | __le16 csum; /* Packet Checksum */ | |
184 | } csum_ip; | |
185 | } hi_dword; | |
186 | } lower; | |
187 | struct { | |
188 | __le32 status_error; /* ext status/error */ | |
189 | __le16 length; /* Packet length */ | |
190 | __le16 vlan; /* VLAN tag */ | |
191 | } upper; | |
192 | } wb; /* writeback */ | |
193 | }; | |
194 | ||
195 | #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F | |
196 | #define E1000_RXDADV_RSSTYPE_SHIFT 12 | |
197 | #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 | |
198 | #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 | |
199 | #define E1000_RXDADV_SPLITHEADER_EN 0x00001000 | |
200 | #define E1000_RXDADV_SPH 0x8000 | |
201 | #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ | |
202 | #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ | |
203 | #define E1000_RXDADV_ERR_HBO 0x00800000 | |
204 | ||
205 | /* RSS Hash results */ | |
206 | #define E1000_RXDADV_RSSTYPE_NONE 0x00000000 | |
207 | #define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 | |
208 | #define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 | |
209 | #define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 | |
210 | #define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 | |
211 | #define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 | |
212 | #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 | |
213 | #define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 | |
214 | #define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 | |
215 | #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 | |
216 | ||
217 | /* RSS Packet Types as indicated in the receive descriptor */ | |
218 | #define E1000_RXDADV_PKTTYPE_ILMASK 0x000000F0 | |
219 | #define E1000_RXDADV_PKTTYPE_TLMASK 0x00000F00 | |
220 | #define E1000_RXDADV_PKTTYPE_NONE 0x00000000 | |
221 | #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ | |
222 | #define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ | |
223 | #define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ | |
224 | #define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ | |
225 | #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ | |
226 | #define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ | |
227 | #define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ | |
228 | #define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ | |
229 | ||
230 | #define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ | |
231 | #define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ | |
232 | #define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ | |
233 | #define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ | |
234 | #define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ | |
235 | #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ | |
236 | ||
237 | /* LinkSec results */ | |
238 | /* Security Processing bit Indication */ | |
239 | #define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 | |
240 | #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 | |
241 | #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 | |
242 | #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 | |
243 | #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 | |
244 | ||
245 | #define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 | |
246 | #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 | |
247 | #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 | |
248 | #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 | |
249 | #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 | |
250 | ||
251 | /* Transmit Descriptor - Advanced */ | |
252 | union e1000_adv_tx_desc { | |
253 | struct { | |
254 | __le64 buffer_addr; /* Address of descriptor's data buf */ | |
255 | __le32 cmd_type_len; | |
256 | __le32 olinfo_status; | |
257 | } read; | |
258 | struct { | |
259 | __le64 rsvd; /* Reserved */ | |
260 | __le32 nxtseq_seed; | |
261 | __le32 status; | |
262 | } wb; | |
263 | }; | |
264 | ||
265 | /* Adv Transmit Descriptor Config Masks */ | |
266 | #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ | |
267 | #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ | |
268 | #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ | |
269 | #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
270 | #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ | |
271 | #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ | |
272 | #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ | |
273 | #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ | |
274 | #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ | |
275 | #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ | |
276 | #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ | |
277 | #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ | |
278 | #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ | |
279 | #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ | |
280 | #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ | |
281 | #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ | |
282 | /* 1st & Last TSO-full iSCSI PDU*/ | |
283 | #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 | |
284 | #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ | |
285 | #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ | |
286 | ||
287 | /* Context descriptors */ | |
288 | struct e1000_adv_tx_context_desc { | |
289 | __le32 vlan_macip_lens; | |
290 | __le32 seqnum_seed; | |
291 | __le32 type_tucmd_mlhl; | |
292 | __le32 mss_l4len_idx; | |
293 | }; | |
294 | ||
295 | #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ | |
296 | #define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ | |
297 | #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ | |
298 | #define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ | |
299 | #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ | |
300 | #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ | |
301 | #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ | |
302 | #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ | |
303 | /* IPSec Encrypt Enable for ESP */ | |
304 | #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 | |
305 | /* Req requires Markers and CRC */ | |
306 | #define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 | |
307 | #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ | |
308 | #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ | |
309 | /* Adv ctxt IPSec SA IDX mask */ | |
310 | #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF | |
311 | /* Adv ctxt IPSec ESP len mask */ | |
312 | #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF | |
313 | ||
314 | /* Additional Transmit Descriptor Control definitions */ | |
315 | #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ | |
316 | #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ | |
317 | /* Tx Queue Arbitration Priority 0=low, 1=high */ | |
318 | #define E1000_TXDCTL_PRIORITY 0x08000000 | |
319 | ||
320 | /* Additional Receive Descriptor Control definitions */ | |
321 | #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ | |
322 | #define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ | |
323 | ||
324 | /* Direct Cache Access (DCA) definitions */ | |
325 | #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ | |
326 | #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ | |
327 | ||
328 | #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ | |
329 | #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ | |
330 | ||
331 | #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ | |
332 | #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ | |
333 | #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ | |
334 | #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ | |
335 | #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ | |
336 | ||
337 | #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ | |
338 | #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ | |
339 | #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ | |
340 | #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ | |
341 | #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ | |
342 | ||
343 | #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ | |
344 | #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ | |
345 | #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ | |
346 | #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ | |
347 | ||
348 | /* Additional interrupt register bit definitions */ | |
349 | #define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ | |
350 | #define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ | |
351 | #define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ | |
352 | ||
353 | /* ETQF register bit definitions */ | |
354 | #define E1000_ETQF_FILTER_ENABLE (1 << 26) | |
355 | #define E1000_ETQF_IMM_INT (1 << 29) | |
356 | #define E1000_ETQF_1588 (1 << 30) | |
9f95a23c | 357 | #define E1000_ETQF_QUEUE_ENABLE (1U << 31) |
7c673cae FG |
358 | /* |
359 | * ETQF filter list: one static filter per filter consumer. This is | |
360 | * to avoid filter collisions later. Add new filters | |
361 | * here!! | |
362 | * | |
363 | * Current filters: | |
364 | * EAPOL 802.1x (0x888e): Filter 0 | |
365 | */ | |
366 | #define E1000_ETQF_FILTER_EAPOL 0 | |
367 | ||
368 | #define E1000_FTQF_VF_BP 0x00008000 | |
369 | #define E1000_FTQF_1588_TIME_STAMP 0x08000000 | |
370 | #define E1000_FTQF_MASK 0xF0000000 | |
371 | #define E1000_FTQF_MASK_PROTO_BP 0x10000000 | |
372 | #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 | |
373 | #define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 | |
374 | #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 | |
375 | ||
376 | #define E1000_NVM_APME_82575 0x0400 | |
377 | #define MAX_NUM_VFS 7 | |
378 | ||
379 | #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */ | |
380 | #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */ | |
381 | #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ | |
382 | #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 | |
383 | #define E1000_DTXSWC_LLE_SHIFT 16 | |
9f95a23c | 384 | #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */ |
7c673cae FG |
385 | |
386 | /* Easy defines for setting default pool, would normally be left a zero */ | |
387 | #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 | |
388 | #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) | |
389 | ||
390 | /* Other useful VMD_CTL register defines */ | |
391 | #define E1000_VT_CTL_IGNORE_MAC (1 << 28) | |
392 | #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) | |
393 | #define E1000_VT_CTL_VM_REPL_EN (1 << 30) | |
394 | ||
395 | /* Per VM Offload register setup */ | |
396 | #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ | |
397 | #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ | |
398 | #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ | |
399 | #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ | |
400 | #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ | |
401 | #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ | |
402 | #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ | |
403 | #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ | |
404 | #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ | |
405 | #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ | |
406 | ||
407 | #define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */ | |
408 | #define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */ | |
409 | #define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */ | |
410 | #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ | |
411 | #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ | |
412 | ||
413 | #define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */ | |
414 | #define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */ | |
415 | ||
416 | #define E1000_VLVF_ARRAY_SIZE 32 | |
417 | #define E1000_VLVF_VLANID_MASK 0x00000FFF | |
418 | #define E1000_VLVF_POOLSEL_SHIFT 12 | |
419 | #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) | |
420 | #define E1000_VLVF_LVLAN 0x00100000 | |
421 | #define E1000_VLVF_VLANID_ENABLE 0x80000000 | |
422 | ||
423 | #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ | |
424 | #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ | |
425 | ||
426 | #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ | |
427 | ||
428 | #define E1000_IOVCTL 0x05BBC | |
429 | #define E1000_IOVCTL_REUSE_VFQ 0x00000001 | |
430 | ||
431 | #define E1000_RPLOLR_STRVLAN 0x40000000 | |
432 | #define E1000_RPLOLR_STRCRC 0x80000000 | |
433 | ||
434 | #define E1000_TCTL_EXT_COLD 0x000FFC00 | |
435 | #define E1000_TCTL_EXT_COLD_SHIFT 10 | |
436 | ||
437 | #define E1000_DTXCTL_8023LL 0x0004 | |
438 | #define E1000_DTXCTL_VLAN_ADDED 0x0008 | |
439 | #define E1000_DTXCTL_OOS_ENABLE 0x0010 | |
440 | #define E1000_DTXCTL_MDP_EN 0x0020 | |
441 | #define E1000_DTXCTL_SPOOF_INT 0x0040 | |
442 | ||
443 | #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) | |
444 | ||
445 | #define ALL_QUEUES 0xFFFF | |
446 | ||
447 | /* Rx packet buffer size defines */ | |
448 | #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F | |
449 | void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); | |
450 | void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf); | |
451 | void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); | |
452 | s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); | |
453 | s32 e1000_init_hw_82575(struct e1000_hw *hw); | |
454 | ||
455 | enum e1000_promisc_type { | |
456 | e1000_promisc_disabled = 0, /* all promisc modes disabled */ | |
457 | e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ | |
458 | e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ | |
459 | e1000_promisc_enabled = 3, /* both uni and multicast promisc */ | |
460 | e1000_num_promisc_types | |
461 | }; | |
462 | ||
463 | void e1000_vfta_set_vf(struct e1000_hw *, u16, bool); | |
464 | void e1000_rlpml_set_vf(struct e1000_hw *, u16); | |
465 | s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type); | |
11fdf7f2 | 466 | void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); |
7c673cae FG |
467 | u16 e1000_rxpbs_adjust_82580(u32 data); |
468 | s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data); | |
469 | s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M); | |
470 | s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M); | |
471 | s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *); | |
472 | s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw); | |
473 | s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw); | |
474 | ||
475 | /* I2C SDA and SCL timing parameters for standard mode */ | |
476 | #define E1000_I2C_T_HD_STA 4 | |
477 | #define E1000_I2C_T_LOW 5 | |
478 | #define E1000_I2C_T_HIGH 4 | |
479 | #define E1000_I2C_T_SU_STA 5 | |
480 | #define E1000_I2C_T_HD_DATA 5 | |
481 | #define E1000_I2C_T_SU_DATA 1 | |
482 | #define E1000_I2C_T_RISE 1 | |
483 | #define E1000_I2C_T_FALL 1 | |
484 | #define E1000_I2C_T_SU_STO 4 | |
485 | #define E1000_I2C_T_BUF 5 | |
486 | ||
487 | s32 e1000_set_i2c_bb(struct e1000_hw *hw); | |
488 | s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, | |
489 | u8 dev_addr, u8 *data); | |
490 | s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, | |
491 | u8 dev_addr, u8 data); | |
492 | void e1000_i2c_bus_clear(struct e1000_hw *hw); | |
493 | #endif /* _E1000_82575_H_ */ |