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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / e1000 / base / e1000_hw.h
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f67539c2
TL		 1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
3 */
7c673cae
FG		 4
5#ifndef _E1000_HW_H_
6#define _E1000_HW_H_
7
8#include "e1000_osdep.h"
9#include "e1000_regs.h"
10#include "e1000_defines.h"
11
12struct e1000_hw;
13
14#define E1000_DEV_ID_82542 0x1000
15#define E1000_DEV_ID_82543GC_FIBER 0x1001
16#define E1000_DEV_ID_82543GC_COPPER 0x1004
17#define E1000_DEV_ID_82544EI_COPPER 0x1008
18#define E1000_DEV_ID_82544EI_FIBER 0x1009
19#define E1000_DEV_ID_82544GC_COPPER 0x100C
20#define E1000_DEV_ID_82544GC_LOM 0x100D
21#define E1000_DEV_ID_82540EM 0x100E
22#define E1000_DEV_ID_82540EM_LOM 0x1015
23#define E1000_DEV_ID_82540EP_LOM 0x1016
24#define E1000_DEV_ID_82540EP 0x1017
25#define E1000_DEV_ID_82540EP_LP 0x101E
26#define E1000_DEV_ID_82545EM_COPPER 0x100F
27#define E1000_DEV_ID_82545EM_FIBER 0x1011
28#define E1000_DEV_ID_82545GM_COPPER 0x1026
29#define E1000_DEV_ID_82545GM_FIBER 0x1027
30#define E1000_DEV_ID_82545GM_SERDES 0x1028
31#define E1000_DEV_ID_82546EB_COPPER 0x1010
32#define E1000_DEV_ID_82546EB_FIBER 0x1012
33#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
34#define E1000_DEV_ID_82546GB_COPPER 0x1079
35#define E1000_DEV_ID_82546GB_FIBER 0x107A
36#define E1000_DEV_ID_82546GB_SERDES 0x107B
37#define E1000_DEV_ID_82546GB_PCIE 0x108A
38#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
39#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
40#define E1000_DEV_ID_82541EI 0x1013
41#define E1000_DEV_ID_82541EI_MOBILE 0x1018
42#define E1000_DEV_ID_82541ER_LOM 0x1014
43#define E1000_DEV_ID_82541ER 0x1078
44#define E1000_DEV_ID_82541GI 0x1076
45#define E1000_DEV_ID_82541GI_LF 0x107C
46#define E1000_DEV_ID_82541GI_MOBILE 0x1077
47#define E1000_DEV_ID_82547EI 0x1019
48#define E1000_DEV_ID_82547EI_MOBILE 0x101A
49#define E1000_DEV_ID_82547GI 0x1075
50#define E1000_DEV_ID_82571EB_COPPER 0x105E
51#define E1000_DEV_ID_82571EB_FIBER 0x105F
52#define E1000_DEV_ID_82571EB_SERDES 0x1060
53#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
54#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
55#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
56#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
57#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
58#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
59#define E1000_DEV_ID_82572EI_COPPER 0x107D
60#define E1000_DEV_ID_82572EI_FIBER 0x107E
61#define E1000_DEV_ID_82572EI_SERDES 0x107F
62#define E1000_DEV_ID_82572EI 0x10B9
63#define E1000_DEV_ID_82573E 0x108B
64#define E1000_DEV_ID_82573E_IAMT 0x108C
65#define E1000_DEV_ID_82573L 0x109A
66#define E1000_DEV_ID_82574L 0x10D3
67#define E1000_DEV_ID_82574LA 0x10F6
68#define E1000_DEV_ID_82583V 0x150C
69#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
70#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
71#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
72#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
73#define E1000_DEV_ID_ICH8_82567V_3 0x1501
74#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
75#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
76#define E1000_DEV_ID_ICH8_IGP_C 0x104B
77#define E1000_DEV_ID_ICH8_IFE 0x104C
78#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
79#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
80#define E1000_DEV_ID_ICH8_IGP_M 0x104D
81#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
82#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
83#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
84#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
85#define E1000_DEV_ID_ICH9_BM 0x10E5
86#define E1000_DEV_ID_ICH9_IGP_C 0x294C
87#define E1000_DEV_ID_ICH9_IFE 0x10C0
88#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
89#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
90#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
91#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
92#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
93#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
94#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
95#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
96#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
97#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
98#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
99#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
100#define E1000_DEV_ID_PCH2_LV_LM 0x1502
101#define E1000_DEV_ID_PCH2_LV_V 0x1503
102#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
103#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
104#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
105#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
106#define E1000_DEV_ID_PCH_I218_LM2 0x15A0
107#define E1000_DEV_ID_PCH_I218_V2 0x15A1
108#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
109#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
11fdf7f2
TL		 110#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
111#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
112#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
113#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
114#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
115#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
116#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
117#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
118#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
119#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
120#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
121#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
122#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
7c673cae
FG		 123#define E1000_DEV_ID_82576 0x10C9
124#define E1000_DEV_ID_82576_FIBER 0x10E6
125#define E1000_DEV_ID_82576_SERDES 0x10E7
126#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
127#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
128#define E1000_DEV_ID_82576_NS 0x150A
129#define E1000_DEV_ID_82576_NS_SERDES 0x1518
130#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
131#define E1000_DEV_ID_82576_VF 0x10CA
132#define E1000_DEV_ID_82576_VF_HV 0x152D
133#define E1000_DEV_ID_I350_VF 0x1520
134#define E1000_DEV_ID_I350_VF_HV 0x152F
135#define E1000_DEV_ID_82575EB_COPPER 0x10A7
136#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
137#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
138#define E1000_DEV_ID_82580_COPPER 0x150E
139#define E1000_DEV_ID_82580_FIBER 0x150F
140#define E1000_DEV_ID_82580_SERDES 0x1510
141#define E1000_DEV_ID_82580_SGMII 0x1511
142#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
143#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
144#define E1000_DEV_ID_I350_COPPER 0x1521
145#define E1000_DEV_ID_I350_FIBER 0x1522
146#define E1000_DEV_ID_I350_SERDES 0x1523
147#define E1000_DEV_ID_I350_SGMII 0x1524
148#define E1000_DEV_ID_I350_DA4 0x1546
149#define E1000_DEV_ID_I210_COPPER 0x1533
150#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
151#define E1000_DEV_ID_I210_COPPER_IT 0x1535
152#define E1000_DEV_ID_I210_FIBER 0x1536
153#define E1000_DEV_ID_I210_SERDES 0x1537
154#define E1000_DEV_ID_I210_SGMII 0x1538
155#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
156#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
157#define E1000_DEV_ID_I211_COPPER 0x1539
158#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
159#define E1000_DEV_ID_I354_SGMII 0x1F41
160#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
161#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
162#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
163#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
164#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
165
166#define E1000_REVISION_0 0
167#define E1000_REVISION_1 1
168#define E1000_REVISION_2 2
169#define E1000_REVISION_3 3
170#define E1000_REVISION_4 4
171
172#define E1000_FUNC_0 0
173#define E1000_FUNC_1 1
174#define E1000_FUNC_2 2
175#define E1000_FUNC_3 3
176
177#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
178#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
179#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
180#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
181
182enum e1000_mac_type {
183 e1000_undefined = 0,
184 e1000_82542,
185 e1000_82543,
186 e1000_82544,
187 e1000_82540,
188 e1000_82545,
189 e1000_82545_rev_3,
190 e1000_82546,
191 e1000_82546_rev_3,
192 e1000_82541,
193 e1000_82541_rev_2,
194 e1000_82547,
195 e1000_82547_rev_2,
196 e1000_82571,
197 e1000_82572,
198 e1000_82573,
199 e1000_82574,
200 e1000_82583,
201 e1000_80003es2lan,
202 e1000_ich8lan,
203 e1000_ich9lan,
204 e1000_ich10lan,
205 e1000_pchlan,
206 e1000_pch2lan,
207 e1000_pch_lpt,
11fdf7f2
TL		 208 e1000_pch_spt,
209 e1000_pch_cnp,
7c673cae
FG		 210 e1000_82575,
211 e1000_82576,
212 e1000_82580,
213 e1000_i350,
214 e1000_i354,
215 e1000_i210,
216 e1000_i211,
217 e1000_vfadapt,
218 e1000_vfadapt_i350,
219 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
220};
221
222enum e1000_media_type {
223 e1000_media_type_unknown = 0,
224 e1000_media_type_copper = 1,
225 e1000_media_type_fiber = 2,
226 e1000_media_type_internal_serdes = 3,
227 e1000_num_media_types
228};
229
230enum e1000_nvm_type {
231 e1000_nvm_unknown = 0,
232 e1000_nvm_none,
233 e1000_nvm_eeprom_spi,
234 e1000_nvm_eeprom_microwire,
235 e1000_nvm_flash_hw,
236 e1000_nvm_invm,
237 e1000_nvm_flash_sw
238};
239
240enum e1000_nvm_override {
241 e1000_nvm_override_none = 0,
242 e1000_nvm_override_spi_small,
243 e1000_nvm_override_spi_large,
244 e1000_nvm_override_microwire_small,
245 e1000_nvm_override_microwire_large
246};
247
248enum e1000_phy_type {
249 e1000_phy_unknown = 0,
250 e1000_phy_none,
251 e1000_phy_m88,
252 e1000_phy_igp,
253 e1000_phy_igp_2,
254 e1000_phy_gg82563,
255 e1000_phy_igp_3,
256 e1000_phy_ife,
257 e1000_phy_bm,
258 e1000_phy_82578,
259 e1000_phy_82577,
260 e1000_phy_82579,
261 e1000_phy_i217,
262 e1000_phy_82580,
263 e1000_phy_vf,
264 e1000_phy_i210,
265};
266
267enum e1000_bus_type {
268 e1000_bus_type_unknown = 0,
269 e1000_bus_type_pci,
270 e1000_bus_type_pcix,
271 e1000_bus_type_pci_express,
272 e1000_bus_type_reserved
273};
274
275enum e1000_bus_speed {
276 e1000_bus_speed_unknown = 0,
277 e1000_bus_speed_33,
278 e1000_bus_speed_66,
279 e1000_bus_speed_100,
280 e1000_bus_speed_120,
281 e1000_bus_speed_133,
282 e1000_bus_speed_2500,
283 e1000_bus_speed_5000,
284 e1000_bus_speed_reserved
285};
286
287enum e1000_bus_width {
288 e1000_bus_width_unknown = 0,
289 e1000_bus_width_pcie_x1,
290 e1000_bus_width_pcie_x2,
291 e1000_bus_width_pcie_x4 = 4,
292 e1000_bus_width_pcie_x8 = 8,
293 e1000_bus_width_32,
294 e1000_bus_width_64,
295 e1000_bus_width_reserved
296};
297
298enum e1000_1000t_rx_status {
299 e1000_1000t_rx_status_not_ok = 0,
300 e1000_1000t_rx_status_ok,
301 e1000_1000t_rx_status_undefined = 0xFF
302};
303
304enum e1000_rev_polarity {
305 e1000_rev_polarity_normal = 0,
306 e1000_rev_polarity_reversed,
307 e1000_rev_polarity_undefined = 0xFF
308};
309
310enum e1000_fc_mode {
311 e1000_fc_none = 0,
312 e1000_fc_rx_pause,
313 e1000_fc_tx_pause,
314 e1000_fc_full,
315 e1000_fc_default = 0xFF
316};
317
318enum e1000_ffe_config {
319 e1000_ffe_config_enabled = 0,
320 e1000_ffe_config_active,
321 e1000_ffe_config_blocked
322};
323
324enum e1000_dsp_config {
325 e1000_dsp_config_disabled = 0,
326 e1000_dsp_config_enabled,
327 e1000_dsp_config_activated,
328 e1000_dsp_config_undefined = 0xFF
329};
330
331enum e1000_ms_type {
332 e1000_ms_hw_default = 0,
333 e1000_ms_force_master,
334 e1000_ms_force_slave,
335 e1000_ms_auto
336};
337
338enum e1000_smart_speed {
339 e1000_smart_speed_default = 0,
340 e1000_smart_speed_on,
341 e1000_smart_speed_off
342};
343
344enum e1000_serdes_link_state {
345 e1000_serdes_link_down = 0,
346 e1000_serdes_link_autoneg_progress,
347 e1000_serdes_link_autoneg_complete,
348 e1000_serdes_link_forced_up
349};
350
351#define __le16 u16
352#define __le32 u32
353#define __le64 u64
354/* Receive Descriptor */
355struct e1000_rx_desc {
356 __le64 buffer_addr; /* Address of the descriptor's data buffer */
357 __le16 length; /* Length of data DMAed into data buffer */
358 __le16 csum; /* Packet checksum */
359 u8 status; /* Descriptor status */
360 u8 errors; /* Descriptor Errors */
361 __le16 special;
362};
363
364/* Receive Descriptor - Extended */
365union e1000_rx_desc_extended {
366 struct {
367 __le64 buffer_addr;
368 __le64 reserved;
369 } read;
370 struct {
371 struct {
372 __le32 mrq; /* Multiple Rx Queues */
373 union {
374 __le32 rss; /* RSS Hash */
375 struct {
376 __le16 ip_id; /* IP id */
377 __le16 csum; /* Packet Checksum */
378 } csum_ip;
379 } hi_dword;
380 } lower;
381 struct {
382 __le32 status_error; /* ext status/error */
383 __le16 length;
384 __le16 vlan; /* VLAN tag */
385 } upper;
386 } wb; /* writeback */
387};
388
389#define MAX_PS_BUFFERS 4
390
391/* Number of packet split data buffers (not including the header buffer) */
392#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
393
394/* Receive Descriptor - Packet Split */
395union e1000_rx_desc_packet_split {
396 struct {
397 /* one buffer for protocol header(s), three data buffers */
398 __le64 buffer_addr[MAX_PS_BUFFERS];
399 } read;
400 struct {
401 struct {
402 __le32 mrq; /* Multiple Rx Queues */
403 union {
404 __le32 rss; /* RSS Hash */
405 struct {
406 __le16 ip_id; /* IP id */
407 __le16 csum; /* Packet Checksum */
408 } csum_ip;
409 } hi_dword;
410 } lower;
411 struct {
412 __le32 status_error; /* ext status/error */
413 __le16 length0; /* length of buffer 0 */
414 __le16 vlan; /* VLAN tag */
415 } middle;
416 struct {
417 __le16 header_status;
418 /* length of buffers 1-3 */
419 __le16 length[PS_PAGE_BUFFERS];
420 } upper;
421 __le64 reserved;
422 } wb; /* writeback */
423};
424
425/* Transmit Descriptor */
426struct e1000_tx_desc {
427 __le64 buffer_addr; /* Address of the descriptor's data buffer */
428 union {
429 __le32 data;
430 struct {
431 __le16 length; /* Data buffer length */
432 u8 cso; /* Checksum offset */
433 u8 cmd; /* Descriptor control */
434 } flags;
435 } lower;
436 union {
437 __le32 data;
438 struct {
439 u8 status; /* Descriptor status */
440 u8 css; /* Checksum start */
441 __le16 special;
442 } fields;
443 } upper;
444};
445
446/* Offload Context Descriptor */
447struct e1000_context_desc {
448 union {
449 __le32 ip_config;
450 struct {
451 u8 ipcss; /* IP checksum start */
452 u8 ipcso; /* IP checksum offset */
453 __le16 ipcse; /* IP checksum end */
454 } ip_fields;
455 } lower_setup;
456 union {
457 __le32 tcp_config;
458 struct {
459 u8 tucss; /* TCP checksum start */
460 u8 tucso; /* TCP checksum offset */
461 __le16 tucse; /* TCP checksum end */
462 } tcp_fields;
463 } upper_setup;
464 __le32 cmd_and_length;
465 union {
466 __le32 data;
467 struct {
468 u8 status; /* Descriptor status */
469 u8 hdr_len; /* Header length */
470 __le16 mss; /* Maximum segment size */
471 } fields;
472 } tcp_seg_setup;
473};
474
475/* Offload data descriptor */
476struct e1000_data_desc {
477 __le64 buffer_addr; /* Address of the descriptor's buffer address */
478 union {
479 __le32 data;
480 struct {
481 __le16 length; /* Data buffer length */
482 u8 typ_len_ext;
483 u8 cmd;
484 } flags;
485 } lower;
486 union {
487 __le32 data;
488 struct {
489 u8 status; /* Descriptor status */
490 u8 popts; /* Packet Options */
491 __le16 special;
492 } fields;
493 } upper;
494};
495
496/* Statistics counters collected by the MAC */
497struct e1000_hw_stats {
498 u64 crcerrs;
499 u64 algnerrc;
500 u64 symerrs;
501 u64 rxerrc;
502 u64 mpc;
503 u64 scc;
504 u64 ecol;
505 u64 mcc;
506 u64 latecol;
507 u64 colc;
508 u64 dc;
509 u64 tncrs;
510 u64 sec;
511 u64 cexterr;
512 u64 rlec;
513 u64 xonrxc;
514 u64 xontxc;
515 u64 xoffrxc;
516 u64 xofftxc;
517 u64 fcruc;
518 u64 prc64;
519 u64 prc127;
520 u64 prc255;
521 u64 prc511;
522 u64 prc1023;
523 u64 prc1522;
524 u64 gprc;
525 u64 bprc;
526 u64 mprc;
527 u64 gptc;
528 u64 gorc;
529 u64 gotc;
530 u64 rnbc;
531 u64 ruc;
532 u64 rfc;
533 u64 roc;
534 u64 rjc;
535 u64 mgprc;
536 u64 mgpdc;
537 u64 mgptc;
538 u64 tor;
539 u64 tot;
540 u64 tpr;
541 u64 tpt;
542 u64 ptc64;
543 u64 ptc127;
544 u64 ptc255;
545 u64 ptc511;
546 u64 ptc1023;
547 u64 ptc1522;
548 u64 mptc;
549 u64 bptc;
550 u64 tsctc;
551 u64 tsctfc;
552 u64 iac;
553 u64 icrxptc;
554 u64 icrxatc;
555 u64 ictxptc;
556 u64 ictxatc;
557 u64 ictxqec;
558 u64 ictxqmtc;
559 u64 icrxdmtc;
560 u64 icrxoc;
561 u64 cbtmpc;
562 u64 htdpmc;
563 u64 cbrdpc;
564 u64 cbrmpc;
565 u64 rpthc;
566 u64 hgptc;
567 u64 htcbdpc;
568 u64 hgorc;
569 u64 hgotc;
570 u64 lenerrs;
571 u64 scvpc;
572 u64 hrmpc;
573 u64 doosync;
574 u64 o2bgptc;
575 u64 o2bspc;
576 u64 b2ospc;
577 u64 b2ogprc;
578};
579
580struct e1000_vf_stats {
581 u64 base_gprc;
582 u64 base_gptc;
583 u64 base_gorc;
584 u64 base_gotc;
585 u64 base_mprc;
586 u64 base_gotlbc;
587 u64 base_gptlbc;
588 u64 base_gorlbc;
589 u64 base_gprlbc;
590
591 u32 last_gprc;
592 u32 last_gptc;
593 u32 last_gorc;
594 u32 last_gotc;
595 u32 last_mprc;
596 u32 last_gotlbc;
597 u32 last_gptlbc;
598 u32 last_gorlbc;
599 u32 last_gprlbc;
600
601 u64 gprc;
602 u64 gptc;
603 u64 gorc;
604 u64 gotc;
605 u64 mprc;
606 u64 gotlbc;
607 u64 gptlbc;
608 u64 gorlbc;
609 u64 gprlbc;
610};
611
612struct e1000_phy_stats {
613 u32 idle_errors;
614 u32 receive_errors;
615};
616
617struct e1000_host_mng_dhcp_cookie {
618 u32 signature;
619 u8 status;
620 u8 reserved0;
621 u16 vlan_id;
622 u32 reserved1;
623 u16 reserved2;
624 u8 reserved3;
625 u8 checksum;
626};
627
628/* Host Interface "Rev 1" */
629struct e1000_host_command_header {
630 u8 command_id;
631 u8 command_length;
632 u8 command_options;
633 u8 checksum;
634};
635
636#define E1000_HI_MAX_DATA_LENGTH 252
637struct e1000_host_command_info {
638 struct e1000_host_command_header command_header;
639 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
640};
641
642/* Host Interface "Rev 2" */
643struct e1000_host_mng_command_header {
644 u8 command_id;
645 u8 checksum;
646 u16 reserved1;
647 u16 reserved2;
648 u16 command_length;
649};
650
651#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
652struct e1000_host_mng_command_info {
653 struct e1000_host_mng_command_header command_header;
654 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
655};
656
657#include "e1000_mac.h"
658#include "e1000_phy.h"
659#include "e1000_nvm.h"
660#include "e1000_manage.h"
661#include "e1000_mbx.h"
662
663/* Function pointers for the MAC. */
664struct e1000_mac_operations {
665 s32 (*init_params)(struct e1000_hw *);
666 s32 (*id_led_init)(struct e1000_hw *);
667 s32 (*blink_led)(struct e1000_hw *);
668 bool (*check_mng_mode)(struct e1000_hw *);
669 s32 (*check_for_link)(struct e1000_hw *);
670 s32 (*cleanup_led)(struct e1000_hw *);
671 void (*clear_hw_cntrs)(struct e1000_hw *);
672 void (*clear_vfta)(struct e1000_hw *);
673 s32 (*get_bus_info)(struct e1000_hw *);
674 void (*set_lan_id)(struct e1000_hw *);
675 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
676 s32 (*led_on)(struct e1000_hw *);
677 s32 (*led_off)(struct e1000_hw *);
678 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
679 s32 (*reset_hw)(struct e1000_hw *);
680 s32 (*init_hw)(struct e1000_hw *);
681 void (*shutdown_serdes)(struct e1000_hw *);
682 void (*power_up_serdes)(struct e1000_hw *);
683 s32 (*setup_link)(struct e1000_hw *);
684 s32 (*setup_physical_interface)(struct e1000_hw *);
685 s32 (*setup_led)(struct e1000_hw *);
686 void (*write_vfta)(struct e1000_hw *, u32, u32);
687 void (*config_collision_dist)(struct e1000_hw *);
688 int (*rar_set)(struct e1000_hw *, u8*, u32);
689 s32 (*read_mac_addr)(struct e1000_hw *);
690 s32 (*validate_mdi_setting)(struct e1000_hw *);
691 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
692 void (*release_swfw_sync)(struct e1000_hw *, u16);
693};
694
695/* When to use various PHY register access functions:
696 *
697 * Func Caller
698 * Function Does Does When to use
699 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
700 * X_reg L,P,A n/a for simple PHY reg accesses
701 * X_reg_locked P,A L for multiple accesses of different regs
702 * on different pages
703 * X_reg_page A L,P for multiple accesses of different regs
704 * on the same page
705 *
706 * Where X=[read|write], L=locking, P=sets page, A=register access
707 *
708 */
709struct e1000_phy_operations {
710 s32 (*init_params)(struct e1000_hw *);
711 s32 (*acquire)(struct e1000_hw *);
712 s32 (*cfg_on_link_up)(struct e1000_hw *);
713 s32 (*check_polarity)(struct e1000_hw *);
714 s32 (*check_reset_block)(struct e1000_hw *);
715 s32 (*commit)(struct e1000_hw *);
716 s32 (*force_speed_duplex)(struct e1000_hw *);
717 s32 (*get_cfg_done)(struct e1000_hw *hw);
718 s32 (*get_cable_length)(struct e1000_hw *);
719 s32 (*get_info)(struct e1000_hw *);
720 s32 (*set_page)(struct e1000_hw *, u16);
721 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
722 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
723 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
724 void (*release)(struct e1000_hw *);
725 s32 (*reset)(struct e1000_hw *);
726 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
727 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
728 s32 (*write_reg)(struct e1000_hw *, u32, u16);
729 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
730 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
731 void (*power_up)(struct e1000_hw *);
732 void (*power_down)(struct e1000_hw *);
733 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
734 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
735};
736
737/* Function pointers for the NVM. */
738struct e1000_nvm_operations {
739 s32 (*init_params)(struct e1000_hw *);
740 s32 (*acquire)(struct e1000_hw *);
741 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
742 void (*release)(struct e1000_hw *);
743 void (*reload)(struct e1000_hw *);
744 s32 (*update)(struct e1000_hw *);
745 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
746 s32 (*validate)(struct e1000_hw *);
747 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
748};
749
750struct e1000_mac_info {
751 struct e1000_mac_operations ops;
752 u8 addr[ETH_ADDR_LEN];
753 u8 perm_addr[ETH_ADDR_LEN];
754
755 enum e1000_mac_type type;
756
757 u32 collision_delta;
758 u32 ledctl_default;
759 u32 ledctl_mode1;
760 u32 ledctl_mode2;
761 u32 mc_filter_type;
762 u32 tx_packet_delta;
763 u32 txcw;
764
765 u16 current_ifs_val;
766 u16 ifs_max_val;
767 u16 ifs_min_val;
768 u16 ifs_ratio;
769 u16 ifs_step_size;
770 u16 mta_reg_count;
771 u16 uta_reg_count;
772
773 /* Maximum size of the MTA register table in all supported adapters */
774#define MAX_MTA_REG 128
775 u32 mta_shadow[MAX_MTA_REG];
776 u16 rar_entry_count;
777
778 u8 forced_speed_duplex;
779
780 bool adaptive_ifs;
781 bool has_fwsm;
782 bool arc_subsystem_valid;
783 bool asf_firmware_present;
784 bool autoneg;
785 bool autoneg_failed;
786 bool get_link_status;
787 bool in_ifs_mode;
788 bool report_tx_early;
789 enum e1000_serdes_link_state serdes_link_state;
790 bool serdes_has_link;
791 bool tx_pkt_filtering;
792};
793
794struct e1000_phy_info {
795 struct e1000_phy_operations ops;
796 enum e1000_phy_type type;
797
798 enum e1000_1000t_rx_status local_rx;
799 enum e1000_1000t_rx_status remote_rx;
800 enum e1000_ms_type ms_type;
801 enum e1000_ms_type original_ms_type;
802 enum e1000_rev_polarity cable_polarity;
803 enum e1000_smart_speed smart_speed;
804
805 u32 addr;
806 u32 id;
807 u32 reset_delay_us; /* in usec */
808 u32 revision;
809
810 enum e1000_media_type media_type;
811
812 u16 autoneg_advertised;
813 u16 autoneg_mask;
814 u16 cable_length;
815 u16 max_cable_length;
816 u16 min_cable_length;
817
818 u8 mdix;
819
820 bool disable_polarity_correction;
821 bool is_mdix;
822 bool polarity_correction;
823 bool speed_downgraded;
824 bool autoneg_wait_to_complete;
825};
826
827struct e1000_nvm_info {
828 struct e1000_nvm_operations ops;
829 enum e1000_nvm_type type;
830 enum e1000_nvm_override override;
831
832 u32 flash_bank_size;
833 u32 flash_base_addr;
834
835 u16 word_size;
836 u16 delay_usec;
837 u16 address_bits;
838 u16 opcode_bits;
839 u16 page_size;
840};
841
842struct e1000_bus_info {
843 enum e1000_bus_type type;
844 enum e1000_bus_speed speed;
845 enum e1000_bus_width width;
846
847 u16 func;
848 u16 pci_cmd_word;
849};
850
851struct e1000_fc_info {
852 u32 high_water; /* Flow control high-water mark */
853 u32 low_water; /* Flow control low-water mark */
854 u16 pause_time; /* Flow control pause timer */
855 u16 refresh_time; /* Flow control refresh timer */
856 bool send_xon; /* Flow control send XON */
857 bool strict_ieee; /* Strict IEEE mode */
858 enum e1000_fc_mode current_mode; /* FC mode in effect */
859 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
860};
861
862struct e1000_mbx_operations {
863 s32 (*init_params)(struct e1000_hw *hw);
864 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
865 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
866 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
867 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
868 s32 (*check_for_msg)(struct e1000_hw *, u16);
869 s32 (*check_for_ack)(struct e1000_hw *, u16);
870 s32 (*check_for_rst)(struct e1000_hw *, u16);
871};
872
873struct e1000_mbx_stats {
874 u32 msgs_tx;
875 u32 msgs_rx;
876
877 u32 acks;
878 u32 reqs;
879 u32 rsts;
880};
881
882struct e1000_mbx_info {
883 struct e1000_mbx_operations ops;
884 struct e1000_mbx_stats stats;
885 u32 timeout;
886 u32 usec_delay;
887 u16 size;
888};
889
890struct e1000_dev_spec_82541 {
891 enum e1000_dsp_config dsp_config;
892 enum e1000_ffe_config ffe_config;
893 u16 spd_default;
894 bool phy_init_script;
895};
896
897struct e1000_dev_spec_82542 {
898 bool dma_fairness;
899};
900
901struct e1000_dev_spec_82543 {
902 u32 tbi_compatibility;
903 bool dma_fairness;
904 bool init_phy_disabled;
905};
906
907struct e1000_dev_spec_82571 {
908 bool laa_is_present;
909 u32 smb_counter;
910 E1000_MUTEX swflag_mutex;
911};
912
913struct e1000_dev_spec_80003es2lan {
914 bool mdic_wa_enable;
915};
916
917struct e1000_shadow_ram {
918 u16 value;
919 bool modified;
920};
921
922#define E1000_SHADOW_RAM_WORDS 2048
923
924#ifdef ULP_SUPPORT
925/* I218 PHY Ultra Low Power (ULP) states */
926enum e1000_ulp_state {
927 e1000_ulp_state_unknown,
928 e1000_ulp_state_off,
929 e1000_ulp_state_on,
930};
931
932#endif /* ULP_SUPPORT */
933struct e1000_dev_spec_ich8lan {
934 bool kmrn_lock_loss_workaround_enabled;
935 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
936 E1000_MUTEX nvm_mutex;
937 E1000_MUTEX swflag_mutex;
938 bool nvm_k1_enabled;
11fdf7f2 939 bool disable_k1_off;
7c673cae
FG		 940 bool eee_disable;
941 u16 eee_lp_ability;
942#ifdef ULP_SUPPORT
943 enum e1000_ulp_state ulp_state;
11fdf7f2
TL		 944 bool ulp_capability_disabled;
945 bool during_suspend_flow;
946 bool during_dpg_exit;
947#endif /* ULP_SUPPORT */
7c673cae
FG		 948 u16 lat_enc;
949 u16 max_ltr_enc;
950 bool smbus_disable;
951};
952
953struct e1000_dev_spec_82575 {
954 bool sgmii_active;
955 bool global_device_reset;
956 bool eee_disable;
957 bool module_plugged;
958 bool clear_semaphore_once;
959 u32 mtu;
960 struct sfp_e1000_flags eth_flags;
961 u8 media_port;
962 bool media_changed;
963};
964
965struct e1000_dev_spec_vf {
966 u32 vf_number;
967 u32 v2p_mailbox;
968};
969
970struct e1000_hw {
971 void *back;
972
973 u8 *hw_addr;
974 u8 *flash_address;
975 unsigned long io_base;
976
977 struct e1000_mac_info mac;
978 struct e1000_fc_info fc;
979 struct e1000_phy_info phy;
980 struct e1000_nvm_info nvm;
981 struct e1000_bus_info bus;
982 struct e1000_mbx_info mbx;
983 struct e1000_host_mng_dhcp_cookie mng_cookie;
984
985 union {
986 struct e1000_dev_spec_82541 _82541;
987 struct e1000_dev_spec_82542 _82542;
988 struct e1000_dev_spec_82543 _82543;
989 struct e1000_dev_spec_82571 _82571;
990 struct e1000_dev_spec_80003es2lan _80003es2lan;
991 struct e1000_dev_spec_ich8lan ich8lan;
992 struct e1000_dev_spec_82575 _82575;
993 struct e1000_dev_spec_vf vf;
994 } dev_spec;
995
996 u16 device_id;
997 u16 subsystem_vendor_id;
998 u16 subsystem_device_id;
999 u16 vendor_id;
1000
1001 u8 revision_id;
1002};
1003
1004#include "e1000_82541.h"
1005#include "e1000_82543.h"
1006#include "e1000_82571.h"
1007#include "e1000_80003es2lan.h"
1008#include "e1000_ich8lan.h"
1009#include "e1000_82575.h"
1010#include "e1000_i210.h"
1011
1012/* These functions must be implemented by drivers */
1013void e1000_pci_clear_mwi(struct e1000_hw *hw);
1014void e1000_pci_set_mwi(struct e1000_hw *hw);
1015s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1016s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1017void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1018void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1019
1020#endif
Ceph