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f67539c2 TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. | |
3 | * All rights reserved. | |
4 | */ | |
5 | ||
11fdf7f2 TL |
6 | #ifndef _ENA_ETH_IO_H_ |
7 | #define _ENA_ETH_IO_H_ | |
8 | ||
9 | enum ena_eth_io_l3_proto_index { | |
9f95a23c TL |
10 | ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, |
11 | ENA_ETH_IO_L3_PROTO_IPV4 = 8, | |
12 | ENA_ETH_IO_L3_PROTO_IPV6 = 11, | |
13 | ENA_ETH_IO_L3_PROTO_FCOE = 21, | |
14 | ENA_ETH_IO_L3_PROTO_ROCE = 22, | |
11fdf7f2 TL |
15 | }; |
16 | ||
17 | enum ena_eth_io_l4_proto_index { | |
9f95a23c TL |
18 | ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, |
19 | ENA_ETH_IO_L4_PROTO_TCP = 12, | |
20 | ENA_ETH_IO_L4_PROTO_UDP = 13, | |
21 | ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, | |
11fdf7f2 TL |
22 | }; |
23 | ||
24 | struct ena_eth_io_tx_desc { | |
25 | /* 15:0 : length - Buffer length in bytes, must | |
26 | * include any packet trailers that the ENA supposed | |
27 | * to update like End-to-End CRC, Authentication GMAC | |
28 | * etc. This length must not include the | |
29 | * 'Push_Buffer' length. This length must not include | |
30 | * the 4-byte added in the end for 802.3 Ethernet FCS | |
31 | * 21:16 : req_id_hi - Request ID[15:10] | |
32 | * 22 : reserved22 - MBZ | |
33 | * 23 : meta_desc - MBZ | |
34 | * 24 : phase | |
35 | * 25 : reserved1 - MBZ | |
36 | * 26 : first - Indicates first descriptor in | |
37 | * transaction | |
38 | * 27 : last - Indicates last descriptor in | |
39 | * transaction | |
40 | * 28 : comp_req - Indicates whether completion | |
41 | * should be posted, after packet is transmitted. | |
42 | * Valid only for first descriptor | |
43 | * 30:29 : reserved29 - MBZ | |
44 | * 31 : reserved31 - MBZ | |
45 | */ | |
46 | uint32_t len_ctrl; | |
47 | ||
48 | /* 3:0 : l3_proto_idx - L3 protocol. This field | |
49 | * required when l3_csum_en,l3_csum or tso_en are set. | |
50 | * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and | |
51 | * DF flags of the IPv4 header is 0. Otherwise must | |
52 | * be set to 1 | |
53 | * 6:5 : reserved5 | |
54 | * 7 : tso_en - Enable TSO, For TCP only. | |
55 | * 12:8 : l4_proto_idx - L4 protocol. This field need | |
56 | * to be set when l4_csum_en or tso_en are set. | |
57 | * 13 : l3_csum_en - enable IPv4 header checksum. | |
58 | * 14 : l4_csum_en - enable TCP/UDP checksum. | |
59 | * 15 : ethernet_fcs_dis - when set, the controller | |
60 | * will not append the 802.3 Ethernet Frame Check | |
61 | * Sequence to the packet | |
62 | * 16 : reserved16 | |
63 | * 17 : l4_csum_partial - L4 partial checksum. when | |
64 | * set to 0, the ENA calculates the L4 checksum, | |
65 | * where the Destination Address required for the | |
66 | * TCP/UDP pseudo-header is taken from the actual | |
67 | * packet L3 header. when set to 1, the ENA doesn't | |
68 | * calculate the sum of the pseudo-header, instead, | |
69 | * the checksum field of the L4 is used instead. When | |
70 | * TSO enabled, the checksum of the pseudo-header | |
71 | * must not include the tcp length field. L4 partial | |
72 | * checksum should be used for IPv6 packet that | |
73 | * contains Routing Headers. | |
74 | * 20:18 : reserved18 - MBZ | |
75 | * 21 : reserved21 - MBZ | |
76 | * 31:22 : req_id_lo - Request ID[9:0] | |
77 | */ | |
78 | uint32_t meta_ctrl; | |
79 | ||
80 | uint32_t buff_addr_lo; | |
81 | ||
82 | /* address high and header size | |
83 | * 15:0 : addr_hi - Buffer Pointer[47:32] | |
84 | * 23:16 : reserved16_w2 | |
85 | * 31:24 : header_length - Header length. For Low | |
86 | * Latency Queues, this fields indicates the number | |
87 | * of bytes written to the headers' memory. For | |
88 | * normal queues, if packet is TCP or UDP, and longer | |
89 | * than max_header_size, then this field should be | |
90 | * set to the sum of L4 header offset and L4 header | |
91 | * size(without options), otherwise, this field | |
92 | * should be set to 0. For both modes, this field | |
93 | * must not exceed the max_header_size. | |
94 | * max_header_size value is reported by the Max | |
95 | * Queues Feature descriptor | |
96 | */ | |
97 | uint32_t buff_addr_hi_hdr_sz; | |
98 | }; | |
99 | ||
100 | struct ena_eth_io_tx_meta_desc { | |
101 | /* 9:0 : req_id_lo - Request ID[9:0] | |
102 | * 11:10 : reserved10 - MBZ | |
103 | * 12 : reserved12 - MBZ | |
104 | * 13 : reserved13 - MBZ | |
105 | * 14 : ext_valid - if set, offset fields in Word2 | |
106 | * are valid Also MSS High in Word 0 and bits [31:24] | |
107 | * in Word 3 | |
108 | * 15 : reserved15 | |
109 | * 19:16 : mss_hi | |
110 | * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: | |
111 | * Extended Metadata Descriptor | |
112 | * 21 : meta_store - Store extended metadata in queue | |
113 | * cache | |
114 | * 22 : reserved22 - MBZ | |
115 | * 23 : meta_desc - MBO | |
116 | * 24 : phase | |
117 | * 25 : reserved25 - MBZ | |
118 | * 26 : first - Indicates first descriptor in | |
119 | * transaction | |
120 | * 27 : last - Indicates last descriptor in | |
121 | * transaction | |
122 | * 28 : comp_req - Indicates whether completion | |
123 | * should be posted, after packet is transmitted. | |
124 | * Valid only for first descriptor | |
125 | * 30:29 : reserved29 - MBZ | |
126 | * 31 : reserved31 - MBZ | |
127 | */ | |
128 | uint32_t len_ctrl; | |
129 | ||
130 | /* 5:0 : req_id_hi | |
131 | * 31:6 : reserved6 - MBZ | |
132 | */ | |
133 | uint32_t word1; | |
134 | ||
135 | /* 7:0 : l3_hdr_len | |
136 | * 15:8 : l3_hdr_off | |
137 | * 21:16 : l4_hdr_len_in_words - counts the L4 header | |
138 | * length in words. there is an explicit assumption | |
139 | * that L4 header appears right after L3 header and | |
140 | * L4 offset is based on l3_hdr_off+l3_hdr_len | |
141 | * 31:22 : mss_lo | |
142 | */ | |
143 | uint32_t word2; | |
144 | ||
145 | uint32_t reserved; | |
146 | }; | |
147 | ||
148 | struct ena_eth_io_tx_cdesc { | |
149 | /* Request ID[15:0] */ | |
150 | uint16_t req_id; | |
151 | ||
152 | uint8_t status; | |
153 | ||
154 | /* flags | |
155 | * 0 : phase | |
156 | * 7:1 : reserved1 | |
157 | */ | |
158 | uint8_t flags; | |
159 | ||
160 | uint16_t sub_qid; | |
161 | ||
162 | uint16_t sq_head_idx; | |
163 | }; | |
164 | ||
165 | struct ena_eth_io_rx_desc { | |
166 | /* In bytes. 0 means 64KB */ | |
167 | uint16_t length; | |
168 | ||
169 | /* MBZ */ | |
170 | uint8_t reserved2; | |
171 | ||
172 | /* 0 : phase | |
173 | * 1 : reserved1 - MBZ | |
174 | * 2 : first - Indicates first descriptor in | |
175 | * transaction | |
176 | * 3 : last - Indicates last descriptor in transaction | |
177 | * 4 : comp_req | |
178 | * 5 : reserved5 - MBO | |
179 | * 7:6 : reserved6 - MBZ | |
180 | */ | |
181 | uint8_t ctrl; | |
182 | ||
183 | uint16_t req_id; | |
184 | ||
185 | /* MBZ */ | |
186 | uint16_t reserved6; | |
187 | ||
188 | uint32_t buff_addr_lo; | |
189 | ||
190 | uint16_t buff_addr_hi; | |
191 | ||
192 | /* MBZ */ | |
193 | uint16_t reserved16_w3; | |
194 | }; | |
195 | ||
196 | /* 4-word format Note: all ethernet parsing information are valid only when | |
197 | * last=1 | |
198 | */ | |
199 | struct ena_eth_io_rx_cdesc_base { | |
200 | /* 4:0 : l3_proto_idx | |
201 | * 6:5 : src_vlan_cnt | |
202 | * 7 : reserved7 - MBZ | |
203 | * 12:8 : l4_proto_idx | |
204 | * 13 : l3_csum_err - when set, either the L3 | |
205 | * checksum error detected, or, the controller didn't | |
206 | * validate the checksum. This bit is valid only when | |
207 | * l3_proto_idx indicates IPv4 packet | |
208 | * 14 : l4_csum_err - when set, either the L4 | |
209 | * checksum error detected, or, the controller didn't | |
210 | * validate the checksum. This bit is valid only when | |
211 | * l4_proto_idx indicates TCP/UDP packet, and, | |
9f95a23c TL |
212 | * ipv4_frag is not set. This bit is valid only when |
213 | * l4_csum_checked below is set. | |
11fdf7f2 | 214 | * 15 : ipv4_frag - Indicates IPv4 fragmented packet |
9f95a23c TL |
215 | * 16 : l4_csum_checked - L4 checksum was verified |
216 | * (could be OK or error), when cleared the status of | |
217 | * checksum is unknown | |
f67539c2 | 218 | * 23:17 : reserved17 - MBZ |
11fdf7f2 TL |
219 | * 24 : phase |
220 | * 25 : l3_csum2 - second checksum engine result | |
221 | * 26 : first - Indicates first descriptor in | |
222 | * transaction | |
223 | * 27 : last - Indicates last descriptor in | |
224 | * transaction | |
225 | * 29:28 : reserved28 | |
226 | * 30 : buffer - 0: Metadata descriptor. 1: Buffer | |
227 | * Descriptor was used | |
228 | * 31 : reserved31 | |
229 | */ | |
230 | uint32_t status; | |
231 | ||
232 | uint16_t length; | |
233 | ||
234 | uint16_t req_id; | |
235 | ||
236 | /* 32-bit hash result */ | |
237 | uint32_t hash; | |
238 | ||
239 | uint16_t sub_qid; | |
240 | ||
f67539c2 TL |
241 | uint8_t offset; |
242 | ||
243 | uint8_t reserved; | |
11fdf7f2 TL |
244 | }; |
245 | ||
246 | /* 8-word format */ | |
247 | struct ena_eth_io_rx_cdesc_ext { | |
248 | struct ena_eth_io_rx_cdesc_base base; | |
249 | ||
250 | uint32_t buff_addr_lo; | |
251 | ||
252 | uint16_t buff_addr_hi; | |
253 | ||
254 | uint16_t reserved16; | |
255 | ||
256 | uint32_t reserved_w6; | |
257 | ||
258 | uint32_t reserved_w7; | |
259 | }; | |
260 | ||
261 | struct ena_eth_io_intr_reg { | |
262 | /* 14:0 : rx_intr_delay | |
263 | * 29:15 : tx_intr_delay | |
264 | * 30 : intr_unmask | |
265 | * 31 : reserved | |
266 | */ | |
267 | uint32_t intr_control; | |
268 | }; | |
269 | ||
270 | struct ena_eth_io_numa_node_cfg_reg { | |
271 | /* 7:0 : numa | |
272 | * 30:8 : reserved | |
273 | * 31 : enabled | |
274 | */ | |
275 | uint32_t numa_cfg; | |
276 | }; | |
277 | ||
278 | /* tx_desc */ | |
9f95a23c TL |
279 | #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) |
280 | #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 | |
281 | #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) | |
282 | #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 | |
283 | #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) | |
284 | #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 | |
285 | #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) | |
286 | #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 | |
287 | #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) | |
288 | #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 | |
289 | #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) | |
290 | #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 | |
291 | #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) | |
292 | #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) | |
293 | #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 | |
294 | #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) | |
295 | #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 | |
296 | #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) | |
297 | #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 | |
298 | #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) | |
299 | #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 | |
300 | #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) | |
301 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 | |
302 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) | |
303 | #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 | |
304 | #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) | |
305 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 | |
306 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) | |
307 | #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 | |
308 | #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) | |
309 | #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) | |
310 | #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 | |
311 | #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) | |
11fdf7f2 TL |
312 | |
313 | /* tx_meta_desc */ | |
9f95a23c TL |
314 | #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) |
315 | #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 | |
316 | #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) | |
317 | #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 | |
318 | #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) | |
319 | #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 | |
320 | #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) | |
321 | #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 | |
322 | #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) | |
323 | #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 | |
324 | #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) | |
325 | #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 | |
326 | #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) | |
327 | #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 | |
328 | #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) | |
329 | #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 | |
330 | #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) | |
331 | #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 | |
332 | #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) | |
333 | #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) | |
334 | #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) | |
335 | #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 | |
336 | #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) | |
337 | #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 | |
338 | #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) | |
339 | #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 | |
340 | #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) | |
11fdf7f2 TL |
341 | |
342 | /* tx_cdesc */ | |
9f95a23c | 343 | #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) |
11fdf7f2 TL |
344 | |
345 | /* rx_desc */ | |
9f95a23c TL |
346 | #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) |
347 | #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 | |
348 | #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) | |
349 | #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 | |
350 | #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) | |
351 | #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 | |
352 | #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) | |
11fdf7f2 TL |
353 | |
354 | /* rx_cdesc_base */ | |
9f95a23c TL |
355 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) |
356 | #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 | |
357 | #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) | |
358 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 | |
359 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) | |
360 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 | |
361 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) | |
362 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 | |
363 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) | |
364 | #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 | |
365 | #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) | |
366 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 | |
367 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) | |
368 | #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 | |
369 | #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) | |
370 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 | |
371 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) | |
372 | #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 | |
373 | #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) | |
374 | #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 | |
375 | #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) | |
376 | #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 | |
377 | #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) | |
11fdf7f2 TL |
378 | |
379 | /* intr_reg */ | |
9f95a23c TL |
380 | #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) |
381 | #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 | |
382 | #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) | |
383 | #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 | |
384 | #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) | |
11fdf7f2 TL |
385 | |
386 | /* numa_node_cfg_reg */ | |
9f95a23c TL |
387 | #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) |
388 | #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 | |
389 | #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) | |
11fdf7f2 | 390 | |
9f95a23c | 391 | #if !defined(DEFS_LINUX_MAINLINE) |
11fdf7f2 TL |
392 | static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p) |
393 | { | |
394 | return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK; | |
395 | } | |
396 | ||
397 | static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val) | |
398 | { | |
399 | p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK; | |
400 | } | |
401 | ||
402 | static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p) | |
403 | { | |
404 | return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT; | |
405 | } | |
406 | ||
407 | static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val) | |
408 | { | |
409 | p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK; | |
410 | } | |
411 | ||
412 | static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p) | |
413 | { | |
414 | return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT; | |
415 | } | |
416 | ||
417 | static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val) | |
418 | { | |
419 | p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK; | |
420 | } | |
421 | ||
422 | static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p) | |
423 | { | |
424 | return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT; | |
425 | } | |
426 | ||
427 | static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val) | |
428 | { | |
429 | p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK; | |
430 | } | |
431 | ||
432 | static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p) | |
433 | { | |
434 | return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT; | |
435 | } | |
436 | ||
437 | static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val) | |
438 | { | |
439 | p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK; | |
440 | } | |
441 | ||
442 | static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p) | |
443 | { | |
444 | return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT; | |
445 | } | |
446 | ||
447 | static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val) | |
448 | { | |
449 | p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK; | |
450 | } | |
451 | ||
452 | static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p) | |
453 | { | |
454 | return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT; | |
455 | } | |
456 | ||
457 | static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val) | |
458 | { | |
459 | p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; | |
460 | } | |
461 | ||
462 | static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p) | |
463 | { | |
464 | return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; | |
465 | } | |
466 | ||
467 | static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) | |
468 | { | |
469 | p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; | |
470 | } | |
471 | ||
472 | static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p) | |
473 | { | |
474 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT; | |
475 | } | |
476 | ||
477 | static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val) | |
478 | { | |
479 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK; | |
480 | } | |
481 | ||
482 | static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p) | |
483 | { | |
484 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT; | |
485 | } | |
486 | ||
487 | static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val) | |
488 | { | |
489 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK; | |
490 | } | |
491 | ||
492 | static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p) | |
493 | { | |
494 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT; | |
495 | } | |
496 | ||
497 | static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) | |
498 | { | |
499 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK; | |
500 | } | |
501 | ||
502 | static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p) | |
503 | { | |
504 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT; | |
505 | } | |
506 | ||
507 | static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) | |
508 | { | |
509 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK; | |
510 | } | |
511 | ||
512 | static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p) | |
513 | { | |
514 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT; | |
515 | } | |
516 | ||
517 | static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) | |
518 | { | |
519 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK; | |
520 | } | |
521 | ||
522 | static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p) | |
523 | { | |
524 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT; | |
525 | } | |
526 | ||
527 | static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val) | |
528 | { | |
529 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK; | |
530 | } | |
531 | ||
532 | static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p) | |
533 | { | |
534 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT; | |
535 | } | |
536 | ||
537 | static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val) | |
538 | { | |
539 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK; | |
540 | } | |
541 | ||
542 | static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p) | |
543 | { | |
544 | return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT; | |
545 | } | |
546 | ||
547 | static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val) | |
548 | { | |
549 | p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK; | |
550 | } | |
551 | ||
552 | static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p) | |
553 | { | |
554 | return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; | |
555 | } | |
556 | ||
557 | static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val) | |
558 | { | |
559 | p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; | |
560 | } | |
561 | ||
562 | static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p) | |
563 | { | |
564 | return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT; | |
565 | } | |
566 | ||
567 | static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val) | |
568 | { | |
569 | p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK; | |
570 | } | |
571 | ||
572 | static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p) | |
573 | { | |
574 | return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; | |
575 | } | |
576 | ||
577 | static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
578 | { | |
579 | p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; | |
580 | } | |
581 | ||
582 | static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p) | |
583 | { | |
584 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT; | |
585 | } | |
586 | ||
587 | static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
588 | { | |
589 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; | |
590 | } | |
591 | ||
592 | static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p) | |
593 | { | |
594 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT; | |
595 | } | |
596 | ||
597 | static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
598 | { | |
599 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK; | |
600 | } | |
601 | ||
602 | static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p) | |
603 | { | |
604 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT; | |
605 | } | |
606 | ||
607 | static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
608 | { | |
609 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; | |
610 | } | |
611 | ||
612 | static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p) | |
613 | { | |
614 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT; | |
615 | } | |
616 | ||
617 | static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
618 | { | |
619 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; | |
620 | } | |
621 | ||
622 | static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p) | |
623 | { | |
624 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT; | |
625 | } | |
626 | ||
627 | static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
628 | { | |
629 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK; | |
630 | } | |
631 | ||
632 | static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p) | |
633 | { | |
634 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT; | |
635 | } | |
636 | ||
637 | static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
638 | { | |
639 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK; | |
640 | } | |
641 | ||
642 | static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p) | |
643 | { | |
644 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT; | |
645 | } | |
646 | ||
647 | static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
648 | { | |
649 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK; | |
650 | } | |
651 | ||
652 | static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p) | |
653 | { | |
654 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT; | |
655 | } | |
656 | ||
657 | static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
658 | { | |
659 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK; | |
660 | } | |
661 | ||
662 | static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p) | |
663 | { | |
664 | return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT; | |
665 | } | |
666 | ||
667 | static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
668 | { | |
669 | p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK; | |
670 | } | |
671 | ||
672 | static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p) | |
673 | { | |
674 | return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; | |
675 | } | |
676 | ||
677 | static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
678 | { | |
679 | p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; | |
680 | } | |
681 | ||
682 | static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p) | |
683 | { | |
684 | return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; | |
685 | } | |
686 | ||
687 | static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
688 | { | |
689 | p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; | |
690 | } | |
691 | ||
692 | static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p) | |
693 | { | |
694 | return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT; | |
695 | } | |
696 | ||
697 | static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
698 | { | |
699 | p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK; | |
700 | } | |
701 | ||
702 | static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p) | |
703 | { | |
704 | return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT; | |
705 | } | |
706 | ||
707 | static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
708 | { | |
709 | p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; | |
710 | } | |
711 | ||
712 | static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p) | |
713 | { | |
714 | return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT; | |
715 | } | |
716 | ||
717 | static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) | |
718 | { | |
719 | p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK; | |
720 | } | |
721 | ||
722 | static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p) | |
723 | { | |
724 | return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; | |
725 | } | |
726 | ||
727 | static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val) | |
728 | { | |
729 | p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; | |
730 | } | |
731 | ||
732 | static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p) | |
733 | { | |
734 | return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; | |
735 | } | |
736 | ||
737 | static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val) | |
738 | { | |
739 | p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; | |
740 | } | |
741 | ||
742 | static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p) | |
743 | { | |
744 | return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT; | |
745 | } | |
746 | ||
747 | static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val) | |
748 | { | |
749 | p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK; | |
750 | } | |
751 | ||
752 | static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p) | |
753 | { | |
754 | return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT; | |
755 | } | |
756 | ||
757 | static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val) | |
758 | { | |
759 | p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK; | |
760 | } | |
761 | ||
762 | static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p) | |
763 | { | |
764 | return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT; | |
765 | } | |
766 | ||
767 | static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val) | |
768 | { | |
769 | p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; | |
770 | } | |
771 | ||
772 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) | |
773 | { | |
774 | return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; | |
775 | } | |
776 | ||
777 | static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
778 | { | |
779 | p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; | |
780 | } | |
781 | ||
782 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p) | |
783 | { | |
784 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT; | |
785 | } | |
786 | ||
787 | static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
788 | { | |
789 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK; | |
790 | } | |
791 | ||
792 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) | |
793 | { | |
794 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; | |
795 | } | |
796 | ||
797 | static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
798 | { | |
799 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK; | |
800 | } | |
801 | ||
802 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p) | |
803 | { | |
804 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT; | |
805 | } | |
806 | ||
807 | static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
808 | { | |
809 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK; | |
810 | } | |
811 | ||
812 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p) | |
813 | { | |
814 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT; | |
815 | } | |
816 | ||
817 | static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
818 | { | |
819 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK; | |
820 | } | |
821 | ||
822 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p) | |
823 | { | |
824 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; | |
825 | } | |
826 | ||
827 | static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
828 | { | |
829 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK; | |
830 | } | |
831 | ||
9f95a23c TL |
832 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p) |
833 | { | |
834 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT; | |
835 | } | |
836 | ||
837 | static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
838 | { | |
839 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK; | |
840 | } | |
841 | ||
11fdf7f2 TL |
842 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p) |
843 | { | |
844 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; | |
845 | } | |
846 | ||
847 | static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
848 | { | |
849 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK; | |
850 | } | |
851 | ||
852 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p) | |
853 | { | |
854 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT; | |
855 | } | |
856 | ||
857 | static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
858 | { | |
859 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK; | |
860 | } | |
861 | ||
862 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p) | |
863 | { | |
864 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT; | |
865 | } | |
866 | ||
867 | static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
868 | { | |
869 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK; | |
870 | } | |
871 | ||
872 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p) | |
873 | { | |
874 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; | |
875 | } | |
876 | ||
877 | static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
878 | { | |
879 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK; | |
880 | } | |
881 | ||
882 | static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p) | |
883 | { | |
884 | return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT; | |
885 | } | |
886 | ||
887 | static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) | |
888 | { | |
889 | p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK; | |
890 | } | |
891 | ||
892 | static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p) | |
893 | { | |
894 | return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; | |
895 | } | |
896 | ||
897 | static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) | |
898 | { | |
899 | p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; | |
900 | } | |
901 | ||
902 | static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p) | |
903 | { | |
904 | return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT; | |
905 | } | |
906 | ||
907 | static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) | |
908 | { | |
909 | p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; | |
910 | } | |
911 | ||
912 | static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p) | |
913 | { | |
914 | return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT; | |
915 | } | |
916 | ||
917 | static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val) | |
918 | { | |
919 | p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; | |
920 | } | |
921 | ||
922 | static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p) | |
923 | { | |
924 | return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; | |
925 | } | |
926 | ||
927 | static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) | |
928 | { | |
929 | p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; | |
930 | } | |
931 | ||
932 | static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p) | |
933 | { | |
934 | return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT; | |
935 | } | |
936 | ||
937 | static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) | |
938 | { | |
939 | p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; | |
940 | } | |
941 | ||
9f95a23c | 942 | #endif /* !defined(DEFS_LINUX_MAINLINE) */ |
f67539c2 | 943 | #endif /* _ENA_ETH_IO_H_ */ |