[ceph.git] / ceph / src / spdk / dpdk / drivers / net / i40e / base / i40e_dcb.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2001-2018
 */

#ifndef _I40E_DCB_H_
#define _I40E_DCB_H_

#include "i40e_type.h"

#define I40E_DCBX_OFFLOAD_DISABLED	0
#define I40E_DCBX_OFFLOAD_ENABLED	1

#define I40E_DCBX_STATUS_NOT_STARTED	0
#define I40E_DCBX_STATUS_IN_PROGRESS	1
#define I40E_DCBX_STATUS_DONE		2
#define I40E_DCBX_STATUS_MULTIPLE_PEERS	3
#define I40E_DCBX_STATUS_DISABLED	7

#define I40E_TLV_TYPE_END		0
#define I40E_TLV_TYPE_ORG		127

#define I40E_IEEE_8021QAZ_OUI		0x0080C2
#define I40E_IEEE_SUBTYPE_ETS_CFG	9
#define I40E_IEEE_SUBTYPE_ETS_REC	10
#define I40E_IEEE_SUBTYPE_PFC_CFG	11
#define I40E_IEEE_SUBTYPE_APP_PRI	12

#define I40E_CEE_DCBX_OUI		0x001b21
#define I40E_CEE_DCBX_TYPE		2

#define I40E_CEE_SUBTYPE_CTRL		1
#define I40E_CEE_SUBTYPE_PG_CFG		2
#define I40E_CEE_SUBTYPE_PFC_CFG	3
#define I40E_CEE_SUBTYPE_APP_PRI	4

#define I40E_CEE_MAX_FEAT_TYPE		3
#define I40E_LLDP_ADMINSTATUS_DISABLED		0
#define I40E_LLDP_ADMINSTATUS_ENABLED_RX	1
#define I40E_LLDP_ADMINSTATUS_ENABLED_TX	2
#define I40E_LLDP_ADMINSTATUS_ENABLED_RXTX	3

/* Defines for LLDP TLV header */
#define I40E_LLDP_MIB_HLEN		14
#define I40E_LLDP_TLV_LEN_SHIFT		0
#define I40E_LLDP_TLV_LEN_MASK		(0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
#define I40E_LLDP_TLV_TYPE_SHIFT	9
#define I40E_LLDP_TLV_TYPE_MASK		(0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
#define I40E_LLDP_TLV_SUBTYPE_SHIFT	0
#define I40E_LLDP_TLV_SUBTYPE_MASK	(0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
#define I40E_LLDP_TLV_OUI_SHIFT		8
#define I40E_LLDP_TLV_OUI_MASK		(0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)

/* Defines for IEEE ETS TLV */
#define I40E_IEEE_ETS_MAXTC_SHIFT	0
#define I40E_IEEE_ETS_MAXTC_MASK	(0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
#define I40E_IEEE_ETS_CBS_SHIFT		6
#define I40E_IEEE_ETS_CBS_MASK		BIT(I40E_IEEE_ETS_CBS_SHIFT)
#define I40E_IEEE_ETS_WILLING_SHIFT	7
#define I40E_IEEE_ETS_WILLING_MASK	BIT(I40E_IEEE_ETS_WILLING_SHIFT)
#define I40E_IEEE_ETS_PRIO_0_SHIFT	0
#define I40E_IEEE_ETS_PRIO_0_MASK	(0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
#define I40E_IEEE_ETS_PRIO_1_SHIFT	4
#define I40E_IEEE_ETS_PRIO_1_MASK	(0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
#define I40E_CEE_PGID_PRIO_0_SHIFT	0
#define I40E_CEE_PGID_PRIO_0_MASK	(0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
#define I40E_CEE_PGID_PRIO_1_SHIFT	4
#define I40E_CEE_PGID_PRIO_1_MASK	(0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
#define I40E_CEE_PGID_STRICT		15

/* Defines for IEEE TSA types */
#define I40E_IEEE_TSA_STRICT		0
#define I40E_IEEE_TSA_CBS		1
#define I40E_IEEE_TSA_ETS		2
#define I40E_IEEE_TSA_VENDOR		255

/* Defines for IEEE PFC TLV */
#define I40E_IEEE_PFC_CAP_SHIFT		0
#define I40E_IEEE_PFC_CAP_MASK		(0xF << I40E_IEEE_PFC_CAP_SHIFT)
#define I40E_IEEE_PFC_MBC_SHIFT		6
#define I40E_IEEE_PFC_MBC_MASK		BIT(I40E_IEEE_PFC_MBC_SHIFT)
#define I40E_IEEE_PFC_WILLING_SHIFT	7
#define I40E_IEEE_PFC_WILLING_MASK	BIT(I40E_IEEE_PFC_WILLING_SHIFT)

/* Defines for IEEE APP TLV */
#define I40E_IEEE_APP_SEL_SHIFT		0
#define I40E_IEEE_APP_SEL_MASK		(0x7 << I40E_IEEE_APP_SEL_SHIFT)
#define I40E_IEEE_APP_PRIO_SHIFT	5
#define I40E_IEEE_APP_PRIO_MASK		(0x7 << I40E_IEEE_APP_PRIO_SHIFT)

/* TLV definitions for preparing MIB */
#define I40E_TLV_ID_CHASSIS_ID		0
#define I40E_TLV_ID_PORT_ID		1
#define I40E_TLV_ID_TIME_TO_LIVE	2
#define I40E_IEEE_TLV_ID_ETS_CFG	3
#define I40E_IEEE_TLV_ID_ETS_REC	4
#define I40E_IEEE_TLV_ID_PFC_CFG	5
#define I40E_IEEE_TLV_ID_APP_PRI	6
#define I40E_TLV_ID_END_OF_LLDPPDU	7
#define I40E_TLV_ID_START		I40E_IEEE_TLV_ID_ETS_CFG

#define I40E_IEEE_ETS_TLV_LENGTH	25
#define I40E_IEEE_PFC_TLV_LENGTH	6
#define I40E_IEEE_APP_TLV_LENGTH	11

#pragma pack(1)

/* IEEE 802.1AB LLDP TLV structure */
struct i40e_lldp_generic_tlv {
	__be16 typelength;
	u8 tlvinfo[1];
};

/* IEEE 802.1AB LLDP Organization specific TLV */
struct i40e_lldp_org_tlv {
	__be16 typelength;
	__be32 ouisubtype;
	u8 tlvinfo[1];
};

struct i40e_cee_tlv_hdr {
	__be16 typelen;
	u8 operver;
	u8 maxver;
};

struct i40e_cee_ctrl_tlv {
	struct i40e_cee_tlv_hdr hdr;
	__be32 seqno;
	__be32 ackno;
};

struct i40e_cee_feat_tlv {
	struct i40e_cee_tlv_hdr hdr;
	u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
#define I40E_CEE_FEAT_TLV_ENABLE_MASK	0x80
#define I40E_CEE_FEAT_TLV_WILLING_MASK	0x40
#define I40E_CEE_FEAT_TLV_ERR_MASK	0x20
	u8 subtype;
	u8 tlvinfo[1];
};

struct i40e_cee_app_prio {
	__be16 protocol;
	u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
#define I40E_CEE_APP_SELECTOR_MASK	0x03
	__be16 lower_oui;
	u8 prio_map;
};
#pragma pack()

/*
 * TODO: The below structures related LLDP/DCBX variables
 * and statistics are defined but need to find how to get
 * the required information from the Firmware to use them
 */

/* IEEE 802.1AB LLDP Agent Statistics */
struct i40e_lldp_stats {
	u64 remtablelastchangetime;
	u64 remtableinserts;
	u64 remtabledeletes;
	u64 remtabledrops;
	u64 remtableageouts;
	u64 txframestotal;
	u64 rxframesdiscarded;
	u64 rxportframeerrors;
	u64 rxportframestotal;
	u64 rxporttlvsdiscardedtotal;
	u64 rxporttlvsunrecognizedtotal;
	u64 remtoomanyneighbors;
};

/* IEEE 802.1Qaz DCBX variables */
struct i40e_dcbx_variables {
	u32 defmaxtrafficclasses;
	u32 defprioritytcmapping;
	u32 deftcbandwidth;
	u32 deftsaassignment;
};

enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw,
					   u16 *status);
enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,
					      struct i40e_dcbx_config *dcbcfg);
enum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
					     u8 bridgetype,
					     struct i40e_dcbx_config *dcbcfg);
enum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw);
enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw);
enum i40e_status_code i40e_set_dcb_config(struct i40e_hw *hw);
enum i40e_status_code i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
					      struct i40e_dcbx_config *dcbcfg);

#endif /* _I40E_DCB_H_ */
Commit	Line	Data
9f95a23c TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	* Copyright(c) 2001-2018
	3	*/
7c673cae FG	4
	5	#ifndef _I40E_DCB_H_
	6	#define _I40E_DCB_H_
	7
	8	#include "i40e_type.h"
	9
	10	#define I40E_DCBX_OFFLOAD_DISABLED 0
	11	#define I40E_DCBX_OFFLOAD_ENABLED 1
	12
	13	#define I40E_DCBX_STATUS_NOT_STARTED 0
	14	#define I40E_DCBX_STATUS_IN_PROGRESS 1
	15	#define I40E_DCBX_STATUS_DONE 2
	16	#define I40E_DCBX_STATUS_MULTIPLE_PEERS 3
	17	#define I40E_DCBX_STATUS_DISABLED 7
	18
	19	#define I40E_TLV_TYPE_END 0
	20	#define I40E_TLV_TYPE_ORG 127
	21
	22	#define I40E_IEEE_8021QAZ_OUI 0x0080C2
	23	#define I40E_IEEE_SUBTYPE_ETS_CFG 9
	24	#define I40E_IEEE_SUBTYPE_ETS_REC 10
	25	#define I40E_IEEE_SUBTYPE_PFC_CFG 11
	26	#define I40E_IEEE_SUBTYPE_APP_PRI 12
	27
	28	#define I40E_CEE_DCBX_OUI 0x001b21
	29	#define I40E_CEE_DCBX_TYPE 2
	30
	31	#define I40E_CEE_SUBTYPE_CTRL 1
	32	#define I40E_CEE_SUBTYPE_PG_CFG 2
	33	#define I40E_CEE_SUBTYPE_PFC_CFG 3
	34	#define I40E_CEE_SUBTYPE_APP_PRI 4
	35
	36	#define I40E_CEE_MAX_FEAT_TYPE 3
	37	#define I40E_LLDP_ADMINSTATUS_DISABLED 0
	38	#define I40E_LLDP_ADMINSTATUS_ENABLED_RX 1
	39	#define I40E_LLDP_ADMINSTATUS_ENABLED_TX 2
	40	#define I40E_LLDP_ADMINSTATUS_ENABLED_RXTX 3
	41
	42	/* Defines for LLDP TLV header */
	43	#define I40E_LLDP_MIB_HLEN 14
	44	#define I40E_LLDP_TLV_LEN_SHIFT 0
	45	#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
	46	#define I40E_LLDP_TLV_TYPE_SHIFT 9
	47	#define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
	48	#define I40E_LLDP_TLV_SUBTYPE_SHIFT 0
	49	#define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
	50	#define I40E_LLDP_TLV_OUI_SHIFT 8
	51	#define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)
	52
	53	/* Defines for IEEE ETS TLV */
	54	#define I40E_IEEE_ETS_MAXTC_SHIFT 0
	55	#define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
	56	#define I40E_IEEE_ETS_CBS_SHIFT 6
	57	#define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)
	58	#define I40E_IEEE_ETS_WILLING_SHIFT 7
	59	#define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)
	60	#define I40E_IEEE_ETS_PRIO_0_SHIFT 0
	61	#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
	62	#define I40E_IEEE_ETS_PRIO_1_SHIFT 4
	63	#define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
	64	#define I40E_CEE_PGID_PRIO_0_SHIFT 0
	65	#define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
	66	#define I40E_CEE_PGID_PRIO_1_SHIFT 4
	67	#define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
68	#define I40E_CEE_PGID_STRICT 15
69
70	/* Defines for IEEE TSA types */
71	#define I40E_IEEE_TSA_STRICT 0
72	#define I40E_IEEE_TSA_CBS 1
73	#define I40E_IEEE_TSA_ETS 2
74	#define I40E_IEEE_TSA_VENDOR 255
75
76	/* Defines for IEEE PFC TLV */
77	#define I40E_IEEE_PFC_CAP_SHIFT 0
78	#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)
79	#define I40E_IEEE_PFC_MBC_SHIFT 6
80	#define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)
81	#define I40E_IEEE_PFC_WILLING_SHIFT 7
82	#define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)
83
84	/* Defines for IEEE APP TLV */
85	#define I40E_IEEE_APP_SEL_SHIFT 0
86	#define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT)
87	#define I40E_IEEE_APP_PRIO_SHIFT 5
88	#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
89
90	/* TLV definitions for preparing MIB */
91	#define I40E_TLV_ID_CHASSIS_ID 0
92	#define I40E_TLV_ID_PORT_ID 1
93	#define I40E_TLV_ID_TIME_TO_LIVE 2
94	#define I40E_IEEE_TLV_ID_ETS_CFG 3
95	#define I40E_IEEE_TLV_ID_ETS_REC 4
96	#define I40E_IEEE_TLV_ID_PFC_CFG 5
97	#define I40E_IEEE_TLV_ID_APP_PRI 6
98	#define I40E_TLV_ID_END_OF_LLDPPDU 7
99	#define I40E_TLV_ID_START I40E_IEEE_TLV_ID_ETS_CFG
100
101	#define I40E_IEEE_ETS_TLV_LENGTH 25
102	#define I40E_IEEE_PFC_TLV_LENGTH 6
103	#define I40E_IEEE_APP_TLV_LENGTH 11
104
105	#pragma pack(1)
106
107	/* IEEE 802.1AB LLDP TLV structure */
108	struct i40e_lldp_generic_tlv {
109	__be16 typelength;
110	u8 tlvinfo[1];
111	};
112
113	/* IEEE 802.1AB LLDP Organization specific TLV */
114	struct i40e_lldp_org_tlv {
115	__be16 typelength;
116	__be32 ouisubtype;
117	u8 tlvinfo[1];
118	};
119
120	struct i40e_cee_tlv_hdr {
121	__be16 typelen;
122	u8 operver;
123	u8 maxver;
124	};
125
126	struct i40e_cee_ctrl_tlv {
127	struct i40e_cee_tlv_hdr hdr;
128	__be32 seqno;
129	__be32 ackno;
130	};
131
132	struct i40e_cee_feat_tlv {
133	struct i40e_cee_tlv_hdr hdr;
134	u8 en_will_err; /* Bits: \|En\|Will\|Err\|Reserved(5)\| */
135	#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80
136	#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40
137	#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20
138	u8 subtype;
139	u8 tlvinfo[1];
140	};
141
142	struct i40e_cee_app_prio {
143	__be16 protocol;
144	u8 upper_oui_sel; /* Bits: \|Upper OUI(6)\|Selector(2)\| */
145	#define I40E_CEE_APP_SELECTOR_MASK 0x03
146	__be16 lower_oui;
147	u8 prio_map;
148	};
149	#pragma pack()
150
151	/*
152	* TODO: The below structures related LLDP/DCBX variables
153	* and statistics are defined but need to find how to get
154	* the required information from the Firmware to use them
155	*/
156
157	/* IEEE 802.1AB LLDP Agent Statistics */
158	struct i40e_lldp_stats {
159	u64 remtablelastchangetime;
160	u64 remtableinserts;
161	u64 remtabledeletes;
162	u64 remtabledrops;
163	u64 remtableageouts;
164	u64 txframestotal;
165	u64 rxframesdiscarded;
166	u64 rxportframeerrors;
167	u64 rxportframestotal;
168	u64 rxporttlvsdiscardedtotal;
169	u64 rxporttlvsunrecognizedtotal;
170	u64 remtoomanyneighbors;
171	};
172
173	/* IEEE 802.1Qaz DCBX variables */
174	struct i40e_dcbx_variables {
175	u32 defmaxtrafficclasses;
176	u32 defprioritytcmapping;
177	u32 deftcbandwidth;
178	u32 deftsaassignment;
179	};
180
181	enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw,
182	u16 *status);
183	enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,
184	struct i40e_dcbx_config *dcbcfg);
185	enum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
186	u8 bridgetype,
187	struct i40e_dcbx_config *dcbcfg);
188	enum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw);
189	enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw);
190	enum i40e_status_code i40e_set_dcb_config(struct i40e_hw *hw);
191	enum i40e_status_code i40e_dcb_config_to_lldp(u8 lldpmib, u16 miblen,
192	struct i40e_dcbx_config *dcbcfg);
193
194	#endif /* _I40E_DCB_H_ */