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1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(c) 2017 Intel Corporation | |
3 | */ | |
4 | ||
9f95a23c TL |
5 | #ifndef _IAVF_OSDEP_H_ |
6 | #define _IAVF_OSDEP_H_ | |
11fdf7f2 TL |
7 | |
8 | #include <string.h> | |
9 | #include <stdint.h> | |
10 | #include <stdbool.h> | |
11 | #include <stdio.h> | |
12 | #include <stdarg.h> | |
13 | ||
14 | #include <rte_common.h> | |
15 | #include <rte_memcpy.h> | |
16 | #include <rte_memzone.h> | |
17 | #include <rte_malloc.h> | |
18 | #include <rte_byteorder.h> | |
19 | #include <rte_cycles.h> | |
20 | #include <rte_spinlock.h> | |
21 | #include <rte_log.h> | |
22 | #include <rte_io.h> | |
23 | ||
9f95a23c | 24 | #include "../iavf_log.h" |
11fdf7f2 TL |
25 | |
26 | #define INLINE inline | |
27 | #define STATIC static | |
28 | ||
29 | typedef uint8_t u8; | |
30 | typedef int8_t s8; | |
31 | typedef uint16_t u16; | |
32 | typedef uint32_t u32; | |
33 | typedef int32_t s32; | |
34 | typedef uint64_t u64; | |
35 | ||
36 | #define __iomem | |
37 | #define hw_dbg(hw, S, A...) do {} while (0) | |
38 | #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) | |
39 | #define lower_32_bits(n) ((u32)(n)) | |
40 | ||
41 | #ifndef ETH_ADDR_LEN | |
42 | #define ETH_ADDR_LEN 6 | |
43 | #endif | |
44 | ||
45 | #ifndef __le16 | |
46 | #define __le16 uint16_t | |
47 | #endif | |
48 | #ifndef __le32 | |
49 | #define __le32 uint32_t | |
50 | #endif | |
51 | #ifndef __le64 | |
52 | #define __le64 uint64_t | |
53 | #endif | |
54 | #ifndef __be16 | |
55 | #define __be16 uint16_t | |
56 | #endif | |
57 | #ifndef __be32 | |
58 | #define __be32 uint32_t | |
59 | #endif | |
60 | #ifndef __be64 | |
61 | #define __be64 uint64_t | |
62 | #endif | |
63 | ||
64 | #define FALSE 0 | |
65 | #define TRUE 1 | |
66 | #define false 0 | |
67 | #define true 1 | |
68 | ||
69 | #define min(a,b) RTE_MIN(a,b) | |
70 | #define max(a,b) RTE_MAX(a,b) | |
71 | ||
72 | #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) | |
9f95a23c | 73 | #define ASSERT(x) if(!(x)) rte_panic("IAVF: x") |
11fdf7f2 TL |
74 | |
75 | #define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S) | |
76 | #define DEBUGOUT2(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A) | |
77 | #define DEBUGFUNC(F) DEBUGOUT(F "\n") | |
78 | ||
79 | #define CPU_TO_LE16(o) rte_cpu_to_le_16(o) | |
80 | #define CPU_TO_LE32(s) rte_cpu_to_le_32(s) | |
81 | #define CPU_TO_LE64(h) rte_cpu_to_le_64(h) | |
82 | #define LE16_TO_CPU(a) rte_le_to_cpu_16(a) | |
83 | #define LE32_TO_CPU(c) rte_le_to_cpu_32(c) | |
84 | #define LE64_TO_CPU(k) rte_le_to_cpu_64(k) | |
85 | ||
86 | #define cpu_to_le16(o) rte_cpu_to_le_16(o) | |
87 | #define cpu_to_le32(s) rte_cpu_to_le_32(s) | |
88 | #define cpu_to_le64(h) rte_cpu_to_le_64(h) | |
89 | #define le16_to_cpu(a) rte_le_to_cpu_16(a) | |
90 | #define le32_to_cpu(c) rte_le_to_cpu_32(c) | |
91 | #define le64_to_cpu(k) rte_le_to_cpu_64(k) | |
92 | ||
9f95a23c TL |
93 | #define iavf_memset(a, b, c, d) memset((a), (b), (c)) |
94 | #define iavf_memcpy(a, b, c, d) rte_memcpy((a), (b), (c)) | |
11fdf7f2 | 95 | |
9f95a23c TL |
96 | #define iavf_usec_delay(x) rte_delay_us_sleep(x) |
97 | #define iavf_msec_delay(x) iavf_usec_delay(1000 * (x)) | |
11fdf7f2 | 98 | |
9f95a23c TL |
99 | #define IAVF_PCI_REG(reg) rte_read32(reg) |
100 | #define IAVF_PCI_REG_ADDR(a, reg) \ | |
11fdf7f2 TL |
101 | ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) |
102 | ||
9f95a23c | 103 | #define IAVF_PCI_REG_WRITE(reg, value) \ |
11fdf7f2 | 104 | rte_write32((rte_cpu_to_le_32(value)), reg) |
9f95a23c | 105 | #define IAVF_PCI_REG_WRITE_RELAXED(reg, value) \ |
11fdf7f2 TL |
106 | rte_write32_relaxed((rte_cpu_to_le_32(value)), reg) |
107 | static inline | |
9f95a23c | 108 | uint32_t iavf_read_addr(volatile void *addr) |
11fdf7f2 | 109 | { |
9f95a23c | 110 | return rte_le_to_cpu_32(IAVF_PCI_REG(addr)); |
11fdf7f2 TL |
111 | } |
112 | ||
9f95a23c TL |
113 | #define IAVF_READ_REG(hw, reg) \ |
114 | iavf_read_addr(IAVF_PCI_REG_ADDR((hw), (reg))) | |
115 | #define IAVF_WRITE_REG(hw, reg, value) \ | |
116 | IAVF_PCI_REG_WRITE(IAVF_PCI_REG_ADDR((hw), (reg)), (value)) | |
117 | #define IAVF_WRITE_FLUSH(a) \ | |
118 | IAVF_READ_REG(a, IAVFGEN_RSTAT) | |
11fdf7f2 | 119 | |
9f95a23c | 120 | #define rd32(a, reg) iavf_read_addr(IAVF_PCI_REG_ADDR((a), (reg))) |
11fdf7f2 | 121 | #define wr32(a, reg, value) \ |
9f95a23c | 122 | IAVF_PCI_REG_WRITE(IAVF_PCI_REG_ADDR((a), (reg)), (value)) |
11fdf7f2 TL |
123 | |
124 | #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) | |
125 | ||
9f95a23c | 126 | #define iavf_debug(h, m, s, ...) \ |
11fdf7f2 TL |
127 | do { \ |
128 | if (((m) & (h)->debug_mask)) \ | |
9f95a23c | 129 | PMD_DRV_LOG_RAW(DEBUG, "iavf %02x.%x " s, \ |
11fdf7f2 TL |
130 | (h)->bus.device, (h)->bus.func, \ |
131 | ##__VA_ARGS__); \ | |
132 | } while (0) | |
133 | ||
134 | /* memory allocation tracking */ | |
9f95a23c | 135 | struct iavf_dma_mem { |
11fdf7f2 TL |
136 | void *va; |
137 | u64 pa; | |
138 | u32 size; | |
139 | const void *zone; | |
140 | } __attribute__((packed)); | |
141 | ||
9f95a23c | 142 | struct iavf_virt_mem { |
11fdf7f2 TL |
143 | void *va; |
144 | u32 size; | |
145 | } __attribute__((packed)); | |
146 | ||
147 | /* SW spinlock */ | |
9f95a23c | 148 | struct iavf_spinlock { |
11fdf7f2 TL |
149 | rte_spinlock_t spinlock; |
150 | }; | |
151 | ||
9f95a23c TL |
152 | #define iavf_allocate_dma_mem(h, m, unused, s, a) \ |
153 | iavf_allocate_dma_mem_d(h, m, s, a) | |
154 | #define iavf_free_dma_mem(h, m) iavf_free_dma_mem_d(h, m) | |
11fdf7f2 | 155 | |
9f95a23c TL |
156 | #define iavf_allocate_virt_mem(h, m, s) iavf_allocate_virt_mem_d(h, m, s) |
157 | #define iavf_free_virt_mem(h, m) iavf_free_virt_mem_d(h, m) | |
11fdf7f2 TL |
158 | |
159 | static inline void | |
9f95a23c | 160 | iavf_init_spinlock_d(struct iavf_spinlock *sp) |
11fdf7f2 TL |
161 | { |
162 | rte_spinlock_init(&sp->spinlock); | |
163 | } | |
164 | ||
165 | static inline void | |
9f95a23c | 166 | iavf_acquire_spinlock_d(struct iavf_spinlock *sp) |
11fdf7f2 TL |
167 | { |
168 | rte_spinlock_lock(&sp->spinlock); | |
169 | } | |
170 | ||
171 | static inline void | |
9f95a23c | 172 | iavf_release_spinlock_d(struct iavf_spinlock *sp) |
11fdf7f2 TL |
173 | { |
174 | rte_spinlock_unlock(&sp->spinlock); | |
175 | } | |
176 | ||
177 | static inline void | |
9f95a23c | 178 | iavf_destroy_spinlock_d(__rte_unused struct iavf_spinlock *sp) |
11fdf7f2 TL |
179 | { |
180 | } | |
181 | ||
9f95a23c TL |
182 | #define iavf_init_spinlock(_sp) iavf_init_spinlock_d(_sp) |
183 | #define iavf_acquire_spinlock(_sp) iavf_acquire_spinlock_d(_sp) | |
184 | #define iavf_release_spinlock(_sp) iavf_release_spinlock_d(_sp) | |
185 | #define iavf_destroy_spinlock(_sp) iavf_destroy_spinlock_d(_sp) | |
11fdf7f2 | 186 | |
9f95a23c | 187 | #endif /* _IAVF_OSDEP_H_ */ |