[ceph.git] / ceph / src / spdk / dpdk / drivers / net / ice / base / ice_controlq.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2001-2020 Intel Corporation
 */

#ifndef _ICE_CONTROLQ_H_
#define _ICE_CONTROLQ_H_

#include "ice_adminq_cmd.h"

/* Maximum buffer lengths for all control queue types */
#define ICE_AQ_MAX_BUF_LEN 4096
#define ICE_MBXQ_MAX_BUF_LEN 4096

#define ICE_CTL_Q_DESC(R, i) \
	(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))

#define ICE_CTL_Q_DESC_UNUSED(R) \
	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	      (R)->next_to_clean - (R)->next_to_use - 1)

/* Defines that help manage the driver vs FW API checks.
 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
 */
#define EXP_FW_API_VER_BRANCH		0x00
#define EXP_FW_API_VER_MAJOR		0x01
#define EXP_FW_API_VER_MINOR		0x05

/* Different control queue types: These are mainly for SW consumption. */
enum ice_ctl_q {
	ICE_CTL_Q_UNKNOWN = 0,
	ICE_CTL_Q_ADMIN,
	ICE_CTL_Q_MAILBOX,
};

/* Control Queue timeout settings - max delay 250ms */
#define ICE_CTL_Q_SQ_CMD_TIMEOUT	2500  /* Count 2500 times */
#define ICE_CTL_Q_SQ_CMD_USEC		100   /* Check every 100usec */
#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT	10    /* Count 10 times */
#define ICE_CTL_Q_ADMIN_INIT_MSEC	100   /* Check every 100msec */

struct ice_ctl_q_ring {
	void *dma_head;			/* Virtual address to DMA head */
	struct ice_dma_mem desc_buf;	/* descriptor ring memory */
	void *cmd_buf;			/* command buffer memory */

	union {
		struct ice_dma_mem *sq_bi;
		struct ice_dma_mem *rq_bi;
	} r;

	u16 count;		/* Number of descriptors */

	/* used for interrupt processing */
	u16 next_to_use;
	u16 next_to_clean;

	/* used for queue tracking */
	u32 head;
	u32 tail;
	u32 len;
	u32 bah;
	u32 bal;
	u32 len_mask;
	u32 len_ena_mask;
	u32 len_crit_mask;
	u32 head_mask;
};

/* sq transaction details */
struct ice_sq_cd {
	struct ice_aq_desc *wb_desc;
};

#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))

/* rq event information */
struct ice_rq_event_info {
	struct ice_aq_desc desc;
	u16 msg_len;
	u16 buf_len;
	u8 *msg_buf;
};

/* Control Queue information */
struct ice_ctl_q_info {
	enum ice_ctl_q qtype;
	enum ice_aq_err rq_last_status;	/* last status on receive queue */
	struct ice_ctl_q_ring rq;	/* receive queue */
	struct ice_ctl_q_ring sq;	/* send queue */
	u32 sq_cmd_timeout;		/* send queue cmd write back timeout */
	u16 num_rq_entries;		/* receive queue depth */
	u16 num_sq_entries;		/* send queue depth */
	u16 rq_buf_size;		/* receive queue buffer size */
	u16 sq_buf_size;		/* send queue buffer size */
	enum ice_aq_err sq_last_status;	/* last status on send queue */
	struct ice_lock sq_lock;		/* Send queue lock */
	struct ice_lock rq_lock;		/* Receive queue lock */
};

#endif /* _ICE_CONTROLQ_H_ */
Commit	Line	Data
9f95a23c	1	/* SPDX-License-Identifier: BSD-3-Clause
f67539c2	2	* Copyright(c) 2001-2020 Intel Corporation
9f95a23c TL	3	*/
	4
	5	#ifndef _ICE_CONTROLQ_H_
	6	#define _ICE_CONTROLQ_H_
	7
	8	#include "ice_adminq_cmd.h"
	9
9f95a23c TL	10	/* Maximum buffer lengths for all control queue types */
	11	#define ICE_AQ_MAX_BUF_LEN 4096
	12	#define ICE_MBXQ_MAX_BUF_LEN 4096
	13
	14	#define ICE_CTL_Q_DESC(R, i) \
	15	(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
	16
	17	#define ICE_CTL_Q_DESC_UNUSED(R) \
	18	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	19	(R)->next_to_clean - (R)->next_to_use - 1)
	20
	21	/* Defines that help manage the driver vs FW API checks.
	22	* Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
	23	*/
	24	#define EXP_FW_API_VER_BRANCH 0x00
	25	#define EXP_FW_API_VER_MAJOR 0x01
f67539c2	26	#define EXP_FW_API_VER_MINOR 0x05
9f95a23c TL	27
	28	/* Different control queue types: These are mainly for SW consumption. */
	29	enum ice_ctl_q {
	30	ICE_CTL_Q_UNKNOWN = 0,
	31	ICE_CTL_Q_ADMIN,
	32	ICE_CTL_Q_MAILBOX,
	33	};
	34
f67539c2 TL	35	/* Control Queue timeout settings - max delay 250ms */
	36	#define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */
	37	#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
	38	#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
	39	#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
9f95a23c TL	40
9f95a23c TL	41	struct ice_ctl_q_ring {
f67539c2	42	void dma_head; / Virtual address to DMA head */
9f95a23c TL	43	struct ice_dma_mem desc_buf; /* descriptor ring memory */
	44	void cmd_buf; / command buffer memory */
	45
	46	union {
	47	struct ice_dma_mem *sq_bi;
	48	struct ice_dma_mem *rq_bi;
	49	} r;
	50
	51	u16 count; /* Number of descriptors */
	52
	53	/* used for interrupt processing */
	54	u16 next_to_use;
	55	u16 next_to_clean;
	56
	57	/* used for queue tracking */
	58	u32 head;
	59	u32 tail;
	60	u32 len;
	61	u32 bah;
	62	u32 bal;
	63	u32 len_mask;
	64	u32 len_ena_mask;
f67539c2	65	u32 len_crit_mask;
9f95a23c TL	66	u32 head_mask;
	67	};
	68
	69	/* sq transaction details */
	70	struct ice_sq_cd {
	71	struct ice_aq_desc *wb_desc;
	72	};
	73
	74	#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
	75
	76	/* rq event information */
	77	struct ice_rq_event_info {
	78	struct ice_aq_desc desc;
	79	u16 msg_len;
	80	u16 buf_len;
	81	u8 *msg_buf;
	82	};
	83
	84	/* Control Queue information */
	85	struct ice_ctl_q_info {
	86	enum ice_ctl_q qtype;
f67539c2	87	enum ice_aq_err rq_last_status; /* last status on receive queue */
9f95a23c TL	88	struct ice_ctl_q_ring rq; /* receive queue */
	89	struct ice_ctl_q_ring sq; /* send queue */
	90	u32 sq_cmd_timeout; /* send queue cmd write back timeout */
	91	u16 num_rq_entries; /* receive queue depth */
	92	u16 num_sq_entries; /* send queue depth */
	93	u16 rq_buf_size; /* receive queue buffer size */
	94	u16 sq_buf_size; /* send queue buffer size */
f67539c2	95	enum ice_aq_err sq_last_status; /* last status on send queue */
9f95a23c TL	96	struct ice_lock sq_lock; /* Send queue lock */
9f95a23c TL	97	struct ice_lock rq_lock; /* Receive queue lock */
9f95a23c TL	98	};
	99
	100	#endif /* _ICE_CONTROLQ_H_ */