]>
Commit | Line | Data |
---|---|---|
9f95a23c | 1 | /* SPDX-License-Identifier: BSD-3-Clause |
f67539c2 | 2 | * Copyright(c) 2001-2020 Intel Corporation |
9f95a23c | 3 | */ |
7c673cae FG |
4 | |
5 | #ifndef _IXGBE_OS_H_ | |
6 | #define _IXGBE_OS_H_ | |
7 | ||
8 | #include <string.h> | |
9 | #include <stdint.h> | |
10 | #include <stdio.h> | |
11 | #include <stdarg.h> | |
f67539c2 | 12 | #include <stdbool.h> |
7c673cae FG |
13 | #include <rte_common.h> |
14 | #include <rte_debug.h> | |
15 | #include <rte_cycles.h> | |
16 | #include <rte_log.h> | |
17 | #include <rte_byteorder.h> | |
11fdf7f2 | 18 | #include <rte_io.h> |
7c673cae FG |
19 | |
20 | #include "../ixgbe_logs.h" | |
21 | #include "../ixgbe_bypass_defines.h" | |
22 | ||
23 | #define ASSERT(x) if(!(x)) rte_panic("IXGBE: x") | |
24 | ||
9f95a23c | 25 | #define DELAY(x) rte_delay_us_sleep(x) |
7c673cae FG |
26 | #define usec_delay(x) DELAY(x) |
27 | #define msec_delay(x) DELAY(1000*(x)) | |
28 | ||
29 | #define DEBUGFUNC(F) DEBUGOUT(F "\n"); | |
30 | #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args) | |
31 | #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args) | |
32 | #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args) | |
33 | #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args) | |
34 | #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args) | |
35 | #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args) | |
36 | ||
37 | #define ERROR_REPORT1(e, S, args...) DEBUGOUT(S, ##args) | |
38 | #define ERROR_REPORT2(e, S, args...) DEBUGOUT(S, ##args) | |
39 | #define ERROR_REPORT3(e, S, args...) DEBUGOUT(S, ##args) | |
40 | ||
41 | #define FALSE 0 | |
42 | #define TRUE 1 | |
43 | ||
44 | #define false 0 | |
45 | #define true 1 | |
46 | #define min(a,b) RTE_MIN(a,b) | |
47 | ||
48 | #define EWARN(hw, S, args...) DEBUGOUT1(S, ##args) | |
49 | ||
50 | /* Bunch of defines for shared code bogosity */ | |
51 | #define UNREFERENCED_PARAMETER(_p) | |
52 | #define UNREFERENCED_1PARAMETER(_p) | |
53 | #define UNREFERENCED_2PARAMETER(_p, _q) | |
54 | #define UNREFERENCED_3PARAMETER(_p, _q, _r) | |
55 | #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) | |
11fdf7f2 | 56 | #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) |
7c673cae FG |
57 | |
58 | /* Shared code error reporting */ | |
59 | enum { | |
60 | IXGBE_ERROR_SOFTWARE, | |
61 | IXGBE_ERROR_POLLING, | |
62 | IXGBE_ERROR_INVALID_STATE, | |
63 | IXGBE_ERROR_UNSUPPORTED, | |
64 | IXGBE_ERROR_ARGUMENT, | |
65 | IXGBE_ERROR_CAUTION, | |
66 | }; | |
67 | ||
68 | #define STATIC static | |
69 | #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i) | |
70 | #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i) | |
11fdf7f2 | 71 | #define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i) |
7c673cae | 72 | #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i) |
11fdf7f2 | 73 | #define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i) |
7c673cae FG |
74 | #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i) |
75 | #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i) | |
76 | #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i) | |
77 | #define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i) | |
78 | ||
79 | typedef uint8_t u8; | |
80 | typedef int8_t s8; | |
81 | typedef uint16_t u16; | |
82 | typedef int16_t s16; | |
83 | typedef uint32_t u32; | |
84 | typedef int32_t s32; | |
85 | typedef uint64_t u64; | |
7c673cae FG |
86 | |
87 | #define mb() rte_mb() | |
88 | #define wmb() rte_wmb() | |
89 | #define rmb() rte_rmb() | |
90 | ||
91 | #define IOMEM | |
92 | ||
93 | #define prefetch(x) rte_prefetch0(x) | |
94 | ||
11fdf7f2 | 95 | #define IXGBE_PCI_REG(reg) rte_read32(reg) |
7c673cae FG |
96 | |
97 | static inline uint32_t ixgbe_read_addr(volatile void* addr) | |
98 | { | |
99 | return rte_le_to_cpu_32(IXGBE_PCI_REG(addr)); | |
100 | } | |
101 | ||
11fdf7f2 TL |
102 | #define IXGBE_PCI_REG_WRITE(reg, value) \ |
103 | rte_write32((rte_cpu_to_le_32(value)), reg) | |
104 | ||
105 | #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \ | |
106 | rte_write32_relaxed((rte_cpu_to_le_32(value)), reg) | |
7c673cae FG |
107 | |
108 | #define IXGBE_PCI_REG_ADDR(hw, reg) \ | |
109 | ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg))) | |
110 | ||
111 | #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \ | |
112 | IXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2)) | |
113 | ||
114 | /* Not implemented !! */ | |
115 | #define IXGBE_READ_PCIE_WORD(hw, reg) 0 | |
116 | #define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0) | |
117 | ||
118 | #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) | |
119 | ||
120 | #define IXGBE_READ_REG(hw, reg) \ | |
121 | ixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg))) | |
122 | ||
123 | #define IXGBE_WRITE_REG(hw, reg, value) \ | |
124 | IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value)) | |
125 | ||
126 | #define IXGBE_READ_REG_ARRAY(hw, reg, index) \ | |
127 | IXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index))) | |
128 | ||
129 | #define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \ | |
130 | IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value)) | |
131 | ||
11fdf7f2 TL |
132 | #define IXGBE_WRITE_REG_THEN_POLL_MASK(hw, reg, val, mask, poll_ms) \ |
133 | do { \ | |
134 | uint32_t cnt = poll_ms; \ | |
135 | IXGBE_WRITE_REG(hw, (reg), (val)); \ | |
136 | while (((IXGBE_READ_REG(hw, (reg))) & (mask)) && (cnt--)) \ | |
137 | rte_delay_ms(1); \ | |
138 | } while (0) | |
139 | ||
7c673cae | 140 | #endif /* _IXGBE_OS_H_ */ |