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1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(c) 2017 Cavium, Inc | |
3 | */ | |
4 | ||
5 | #ifndef __OCTEONTX_IO_H__ | |
6 | #define __OCTEONTX_IO_H__ | |
7 | ||
8 | #include <stddef.h> | |
9 | #include <stdint.h> | |
10 | ||
11 | #include <rte_io.h> | |
12 | ||
9f95a23c | 13 | /* In Cavium OCTEON TX SoC, all accesses to the device registers are |
11fdf7f2 TL |
14 | * implicitly strongly ordered. So, The relaxed version of IO operation is |
15 | * safe to use with out any IO memory barriers. | |
16 | */ | |
17 | #define octeontx_read64 rte_read64_relaxed | |
18 | #define octeontx_write64 rte_write64_relaxed | |
19 | ||
20 | /* ARM64 specific functions */ | |
21 | #if defined(RTE_ARCH_ARM64) | |
22 | #define octeontx_prefetch_store_keep(_ptr) ({\ | |
23 | asm volatile("prfm pstl1keep, %a0\n" : : "p" (_ptr)); }) | |
24 | ||
25 | #define octeontx_load_pair(val0, val1, addr) ({ \ | |
26 | asm volatile( \ | |
27 | "ldp %x[x0], %x[x1], [%x[p1]]" \ | |
28 | :[x0]"=r"(val0), [x1]"=r"(val1) \ | |
29 | :[p1]"r"(addr) \ | |
30 | ); }) | |
31 | ||
32 | #define octeontx_store_pair(val0, val1, addr) ({ \ | |
33 | asm volatile( \ | |
34 | "stp %x[x0], %x[x1], [%x[p1]]" \ | |
35 | ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \ | |
36 | ); }) | |
37 | #else /* Un optimized functions for building on non arm64 arch */ | |
38 | ||
39 | #define octeontx_prefetch_store_keep(_ptr) do {} while (0) | |
40 | ||
41 | #define octeontx_load_pair(val0, val1, addr) \ | |
42 | do { \ | |
43 | val0 = rte_read64(addr); \ | |
44 | val1 = rte_read64(((uint8_t *)addr) + 8); \ | |
45 | } while (0) | |
46 | ||
47 | #define octeontx_store_pair(val0, val1, addr) \ | |
48 | do { \ | |
49 | rte_write64(val0, addr); \ | |
50 | rte_write64(val1, (((uint8_t *)addr) + 8)); \ | |
51 | } while (0) | |
52 | #endif | |
53 | ||
54 | #if defined(RTE_ARCH_ARM64) | |
55 | /** | |
56 | * Perform an atomic fetch-and-add operation. | |
57 | */ | |
58 | static inline uint64_t | |
59 | octeontx_reg_ldadd_u64(void *addr, int64_t off) | |
60 | { | |
61 | uint64_t old_val; | |
62 | ||
63 | __asm__ volatile( | |
64 | " .cpu generic+lse\n" | |
65 | " ldadd %1, %0, [%2]\n" | |
66 | : "=r" (old_val) : "r" (off), "r" (addr) : "memory"); | |
67 | ||
68 | return old_val; | |
69 | } | |
70 | ||
71 | /** | |
72 | * Perform a LMTST operation - an atomic write of up to 128 byte to | |
73 | * an I/O block that supports this operation type. | |
74 | * | |
75 | * @param lmtline_va is the address where LMTLINE is mapped | |
76 | * @param ioreg_va is the virtual address of the device register | |
77 | * @param cmdbuf is the array of peripheral commands to execute | |
78 | * @param cmdsize is the number of 64-bit words in 'cmdbuf' | |
79 | * | |
80 | * @return N/A | |
81 | */ | |
82 | static inline void | |
83 | octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[], | |
84 | uint64_t cmdsize) | |
85 | { | |
86 | uint64_t result; | |
87 | uint64_t word_count; | |
88 | uint64_t *lmtline = lmtline_va; | |
89 | ||
90 | word_count = cmdsize; | |
91 | ||
92 | do { | |
93 | /* Copy commands to LMTLINE */ | |
94 | for (result = 0; result < word_count; result += 2) { | |
95 | lmtline[result + 0] = cmdbuf[result + 0]; | |
96 | lmtline[result + 1] = cmdbuf[result + 1]; | |
97 | } | |
98 | ||
99 | /* LDEOR initiates atomic transfer to I/O device */ | |
100 | __asm__ volatile( | |
101 | " .cpu generic+lse\n" | |
102 | " ldeor xzr, %0, [%1]\n" | |
103 | : "=r" (result) : "r" (ioreg_va) : "memory"); | |
104 | } while (!result); | |
105 | } | |
106 | ||
107 | #else | |
108 | ||
109 | static inline uint64_t | |
110 | octeontx_reg_ldadd_u64(void *addr, int64_t off) | |
111 | { | |
112 | RTE_SET_USED(addr); | |
113 | RTE_SET_USED(off); | |
114 | return 0; | |
115 | } | |
116 | ||
117 | static inline void | |
118 | octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[], | |
119 | uint64_t cmdsize) | |
120 | { | |
121 | RTE_SET_USED(lmtline_va); | |
122 | RTE_SET_USED(ioreg_va); | |
123 | RTE_SET_USED(cmdbuf); | |
124 | RTE_SET_USED(cmdsize); | |
125 | } | |
126 | ||
127 | #endif | |
128 | #endif /* __OCTEONTX_IO_H__ */ |