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11fdf7f2 TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright (c) 2016 - 2018 Cavium Inc. | |
7c673cae | 3 | * All rights reserved. |
11fdf7f2 | 4 | * www.cavium.com |
7c673cae FG |
5 | */ |
6 | ||
7 | #ifndef __ECORE_H | |
8 | #define __ECORE_H | |
9 | ||
10 | /* @DPDK */ | |
11 | #include <sys/stat.h> | |
12 | #include <fcntl.h> | |
13 | #include <unistd.h> | |
14 | ||
15 | #define CONFIG_ECORE_BINARY_FW | |
16 | #undef CONFIG_ECORE_ZIPPED_FW | |
17 | ||
18 | #ifdef CONFIG_ECORE_ZIPPED_FW | |
19 | #include <zlib.h> | |
20 | #endif | |
21 | ||
9f95a23c | 22 | #include "ecore_status.h" |
7c673cae FG |
23 | #include "ecore_hsi_common.h" |
24 | #include "ecore_hsi_debug_tools.h" | |
25 | #include "ecore_hsi_init_func.h" | |
26 | #include "ecore_hsi_init_tool.h" | |
27 | #include "ecore_proto_if.h" | |
28 | #include "mcp_public.h" | |
29 | ||
11fdf7f2 | 30 | #define ECORE_MAJOR_VERSION 8 |
f67539c2 TL |
31 | #define ECORE_MINOR_VERSION 40 |
32 | #define ECORE_REVISION_VERSION 26 | |
11fdf7f2 TL |
33 | #define ECORE_ENGINEERING_VERSION 0 |
34 | ||
35 | #define ECORE_VERSION \ | |
36 | ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ | |
37 | (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION) | |
38 | ||
39 | #define STORM_FW_VERSION \ | |
40 | ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ | |
41 | (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) | |
42 | ||
43 | #define IS_ECORE_PACING(p_hwfn) \ | |
44 | (!!(p_hwfn->b_en_pacing)) | |
45 | ||
46 | #define MAX_HWFNS_PER_DEVICE 2 | |
7c673cae | 47 | #define NAME_SIZE 128 /* @DPDK */ |
7c673cae FG |
48 | #define ECORE_WFQ_UNIT 100 |
49 | #include "../qede_logs.h" /* @DPDK */ | |
50 | ||
51 | #define ISCSI_BDQ_ID(_port_id) (_port_id) | |
52 | #define FCOE_BDQ_ID(_port_id) (_port_id + 2) | |
53 | /* Constants */ | |
54 | #define ECORE_WID_SIZE (1024) | |
11fdf7f2 | 55 | #define ECORE_MIN_WIDS (4) |
7c673cae FG |
56 | |
57 | /* Configurable */ | |
58 | #define ECORE_PF_DEMS_SIZE (4) | |
59 | ||
60 | /* cau states */ | |
61 | enum ecore_coalescing_mode { | |
62 | ECORE_COAL_MODE_DISABLE, | |
63 | ECORE_COAL_MODE_ENABLE | |
64 | }; | |
65 | ||
66 | enum ecore_nvm_cmd { | |
67 | ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, | |
68 | ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, | |
69 | ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM, | |
70 | ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, | |
71 | ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE, | |
11fdf7f2 | 72 | ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE, |
7c673cae FG |
73 | ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE, |
74 | ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ, | |
75 | ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE, | |
76 | ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ, | |
77 | ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE, | |
78 | ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00 | |
79 | }; | |
80 | ||
81 | #ifndef LINUX_REMOVE | |
82 | #if !defined(CONFIG_ECORE_L2) | |
83 | #define CONFIG_ECORE_L2 | |
84 | #define CONFIG_ECORE_SRIOV | |
85 | #endif | |
86 | #endif | |
87 | ||
88 | /* helpers */ | |
89 | #ifndef __EXTRACT__LINUX__ | |
90 | #define MASK_FIELD(_name, _value) \ | |
91 | ((_value) &= (_name##_MASK)) | |
92 | ||
93 | #define FIELD_VALUE(_name, _value) \ | |
94 | ((_value & _name##_MASK) << _name##_SHIFT) | |
95 | ||
96 | #define SET_FIELD(value, name, flag) \ | |
97 | do { \ | |
98 | (value) &= ~(name##_MASK << name##_SHIFT); \ | |
11fdf7f2 | 99 | (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\ |
7c673cae FG |
100 | } while (0) |
101 | ||
102 | #define GET_FIELD(value, name) \ | |
103 | (((value) >> (name##_SHIFT)) & name##_MASK) | |
11fdf7f2 TL |
104 | |
105 | #define GET_MFW_FIELD(name, field) \ | |
106 | (((name) & (field ## _MASK)) >> (field ## _OFFSET)) | |
107 | ||
108 | #define SET_MFW_FIELD(name, field, value) \ | |
109 | do { \ | |
110 | (name) &= ~((field ## _MASK)); \ | |
111 | (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \ | |
112 | } while (0) | |
7c673cae FG |
113 | #endif |
114 | ||
115 | static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) | |
116 | { | |
117 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
118 | (cid * ECORE_PF_DEMS_SIZE); | |
119 | ||
120 | return db_addr; | |
121 | } | |
122 | ||
123 | static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS) | |
124 | { | |
125 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
126 | FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); | |
127 | ||
128 | return db_addr; | |
129 | } | |
130 | ||
131 | #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ | |
132 | ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \ | |
133 | ~((1 << (p_hwfn->p_dev->cache_shift)) - 1)) | |
134 | ||
135 | #ifndef LINUX_REMOVE | |
136 | #ifndef U64_HI | |
137 | #define U64_HI(val) ((u32)(((u64)(val)) >> 32)) | |
138 | #endif | |
139 | ||
140 | #ifndef U64_LO | |
141 | #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) | |
142 | #endif | |
143 | #endif | |
144 | ||
145 | #ifndef __EXTRACT__LINUX__ | |
146 | enum DP_LEVEL { | |
147 | ECORE_LEVEL_VERBOSE = 0x0, | |
148 | ECORE_LEVEL_INFO = 0x1, | |
149 | ECORE_LEVEL_NOTICE = 0x2, | |
150 | ECORE_LEVEL_ERR = 0x3, | |
151 | }; | |
152 | ||
153 | #define ECORE_LOG_LEVEL_SHIFT (30) | |
154 | #define ECORE_LOG_VERBOSE_MASK (0x3fffffff) | |
155 | #define ECORE_LOG_INFO_MASK (0x40000000) | |
156 | #define ECORE_LOG_NOTICE_MASK (0x80000000) | |
157 | ||
158 | enum DP_MODULE { | |
159 | #ifndef LINUX_REMOVE | |
160 | ECORE_MSG_DRV = 0x0001, | |
161 | ECORE_MSG_PROBE = 0x0002, | |
162 | ECORE_MSG_LINK = 0x0004, | |
163 | ECORE_MSG_TIMER = 0x0008, | |
164 | ECORE_MSG_IFDOWN = 0x0010, | |
165 | ECORE_MSG_IFUP = 0x0020, | |
166 | ECORE_MSG_RX_ERR = 0x0040, | |
167 | ECORE_MSG_TX_ERR = 0x0080, | |
168 | ECORE_MSG_TX_QUEUED = 0x0100, | |
169 | ECORE_MSG_INTR = 0x0200, | |
170 | ECORE_MSG_TX_DONE = 0x0400, | |
171 | ECORE_MSG_RX_STATUS = 0x0800, | |
172 | ECORE_MSG_PKTDATA = 0x1000, | |
173 | ECORE_MSG_HW = 0x2000, | |
174 | ECORE_MSG_WOL = 0x4000, | |
175 | #endif | |
176 | ECORE_MSG_SPQ = 0x10000, | |
177 | ECORE_MSG_STATS = 0x20000, | |
178 | ECORE_MSG_DCB = 0x40000, | |
179 | ECORE_MSG_IOV = 0x80000, | |
180 | ECORE_MSG_SP = 0x100000, | |
181 | ECORE_MSG_STORAGE = 0x200000, | |
182 | ECORE_MSG_OOO = 0x200000, | |
183 | ECORE_MSG_CXT = 0x800000, | |
184 | ECORE_MSG_LL2 = 0x1000000, | |
185 | ECORE_MSG_ILT = 0x2000000, | |
11fdf7f2 TL |
186 | ECORE_MSG_RDMA = 0x4000000, |
187 | ECORE_MSG_DEBUG = 0x8000000, | |
7c673cae FG |
188 | /* to be added...up to 0x8000000 */ |
189 | }; | |
190 | #endif | |
191 | ||
192 | #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++) | |
193 | ||
194 | #define D_TRINE(val, cond1, cond2, true1, true2, def) \ | |
195 | (val == (cond1) ? true1 : \ | |
196 | (val == (cond2) ? true2 : def)) | |
197 | ||
198 | /* forward */ | |
199 | struct ecore_ptt_pool; | |
200 | struct ecore_spq; | |
201 | struct ecore_sb_info; | |
202 | struct ecore_sb_attn_info; | |
203 | struct ecore_cxt_mngr; | |
204 | struct ecore_dma_mem; | |
205 | struct ecore_sb_sp_info; | |
206 | struct ecore_ll2_info; | |
11fdf7f2 | 207 | struct ecore_l2_info; |
7c673cae FG |
208 | struct ecore_igu_info; |
209 | struct ecore_mcp_info; | |
210 | struct ecore_dcbx_info; | |
9f95a23c | 211 | struct ecore_llh_info; |
7c673cae FG |
212 | |
213 | struct ecore_rt_data { | |
214 | u32 *init_val; | |
215 | bool *b_valid; | |
216 | }; | |
217 | ||
218 | enum ecore_tunn_mode { | |
219 | ECORE_MODE_L2GENEVE_TUNN, | |
220 | ECORE_MODE_IPGENEVE_TUNN, | |
221 | ECORE_MODE_L2GRE_TUNN, | |
222 | ECORE_MODE_IPGRE_TUNN, | |
223 | ECORE_MODE_VXLAN_TUNN, | |
224 | }; | |
225 | ||
226 | enum ecore_tunn_clss { | |
227 | ECORE_TUNN_CLSS_MAC_VLAN, | |
228 | ECORE_TUNN_CLSS_MAC_VNI, | |
229 | ECORE_TUNN_CLSS_INNER_MAC_VLAN, | |
230 | ECORE_TUNN_CLSS_INNER_MAC_VNI, | |
231 | ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, | |
232 | MAX_ECORE_TUNN_CLSS, | |
233 | }; | |
234 | ||
11fdf7f2 TL |
235 | struct ecore_tunn_update_type { |
236 | bool b_update_mode; | |
237 | bool b_mode_enabled; | |
238 | enum ecore_tunn_clss tun_cls; | |
239 | }; | |
240 | ||
241 | struct ecore_tunn_update_udp_port { | |
242 | bool b_update_port; | |
243 | u16 port; | |
244 | }; | |
245 | ||
246 | struct ecore_tunnel_info { | |
247 | struct ecore_tunn_update_type vxlan; | |
248 | struct ecore_tunn_update_type l2_geneve; | |
249 | struct ecore_tunn_update_type ip_geneve; | |
250 | struct ecore_tunn_update_type l2_gre; | |
251 | struct ecore_tunn_update_type ip_gre; | |
252 | ||
253 | struct ecore_tunn_update_udp_port vxlan_port; | |
254 | struct ecore_tunn_update_udp_port geneve_port; | |
255 | ||
256 | bool b_update_rx_cls; | |
257 | bool b_update_tx_cls; | |
7c673cae FG |
258 | }; |
259 | ||
260 | /* The PCI personality is not quite synonymous to protocol ID: | |
261 | * 1. All personalities need CORE connections | |
262 | * 2. The Ethernet personality may support also the RoCE/iWARP protocol | |
263 | */ | |
264 | enum ecore_pci_personality { | |
265 | ECORE_PCI_ETH, | |
266 | ECORE_PCI_FCOE, | |
267 | ECORE_PCI_ISCSI, | |
268 | ECORE_PCI_ETH_ROCE, | |
11fdf7f2 TL |
269 | ECORE_PCI_ETH_IWARP, |
270 | ECORE_PCI_ETH_RDMA, | |
7c673cae FG |
271 | ECORE_PCI_DEFAULT /* default in shmem */ |
272 | }; | |
273 | ||
274 | /* All VFs are symmetric, all counters are PF + all VFs */ | |
275 | struct ecore_qm_iids { | |
276 | u32 cids; | |
277 | u32 vf_cids; | |
278 | u32 tids; | |
279 | }; | |
280 | ||
281 | #define MAX_PF_PER_PORT 8 | |
282 | ||
283 | /* HW / FW resources, output of features supported below, most information | |
284 | * is received from MFW. | |
285 | */ | |
286 | enum ecore_resources { | |
7c673cae FG |
287 | ECORE_L2_QUEUE, |
288 | ECORE_VPORT, | |
289 | ECORE_RSS_ENG, | |
290 | ECORE_PQ, | |
291 | ECORE_RL, | |
292 | ECORE_MAC, | |
293 | ECORE_VLAN, | |
294 | ECORE_RDMA_CNQ_RAM, | |
295 | ECORE_ILT, | |
296 | ECORE_LL2_QUEUE, | |
297 | ECORE_CMDQS_CQS, | |
298 | ECORE_RDMA_STATS_QUEUE, | |
11fdf7f2 TL |
299 | ECORE_BDQ, |
300 | ||
301 | /* This is needed only internally for matching against the IGU. | |
302 | * In case of legacy MFW, would be set to `0'. | |
303 | */ | |
304 | ECORE_SB, | |
305 | ||
306 | ECORE_MAX_RESC, | |
7c673cae FG |
307 | }; |
308 | ||
309 | /* Features that require resources, given as input to the resource management | |
310 | * algorithm, the output are the resources above | |
311 | */ | |
312 | enum ecore_feature { | |
313 | ECORE_PF_L2_QUE, | |
314 | ECORE_PF_TC, | |
315 | ECORE_VF, | |
316 | ECORE_EXTRA_VF_QUE, | |
317 | ECORE_VMQ, | |
318 | ECORE_RDMA_CNQ, | |
319 | ECORE_ISCSI_CQ, | |
320 | ECORE_FCOE_CQ, | |
11fdf7f2 | 321 | ECORE_VF_L2_QUE, |
7c673cae FG |
322 | ECORE_MAX_FEATURES, |
323 | }; | |
324 | ||
325 | enum ecore_port_mode { | |
326 | ECORE_PORT_MODE_DE_2X40G, | |
327 | ECORE_PORT_MODE_DE_2X50G, | |
328 | ECORE_PORT_MODE_DE_1X100G, | |
329 | ECORE_PORT_MODE_DE_4X10G_F, | |
330 | ECORE_PORT_MODE_DE_4X10G_E, | |
331 | ECORE_PORT_MODE_DE_4X20G, | |
332 | ECORE_PORT_MODE_DE_1X40G, | |
333 | ECORE_PORT_MODE_DE_2X25G, | |
334 | ECORE_PORT_MODE_DE_1X25G, | |
335 | ECORE_PORT_MODE_DE_4X25G, | |
11fdf7f2 | 336 | ECORE_PORT_MODE_DE_2X10G, |
7c673cae FG |
337 | }; |
338 | ||
339 | enum ecore_dev_cap { | |
340 | ECORE_DEV_CAP_ETH, | |
341 | ECORE_DEV_CAP_FCOE, | |
342 | ECORE_DEV_CAP_ISCSI, | |
343 | ECORE_DEV_CAP_ROCE, | |
344 | ECORE_DEV_CAP_IWARP | |
345 | }; | |
346 | ||
347 | #ifndef __EXTRACT__LINUX__ | |
348 | enum ecore_hw_err_type { | |
349 | ECORE_HW_ERR_FAN_FAIL, | |
350 | ECORE_HW_ERR_MFW_RESP_FAIL, | |
351 | ECORE_HW_ERR_HW_ATTN, | |
352 | ECORE_HW_ERR_DMAE_FAIL, | |
353 | ECORE_HW_ERR_RAMROD_FAIL, | |
354 | ECORE_HW_ERR_FW_ASSERT, | |
355 | }; | |
356 | #endif | |
357 | ||
11fdf7f2 TL |
358 | enum ecore_db_rec_exec { |
359 | DB_REC_DRY_RUN, | |
360 | DB_REC_REAL_DEAL, | |
361 | DB_REC_ONCE, | |
362 | }; | |
363 | ||
7c673cae FG |
364 | struct ecore_hw_info { |
365 | /* PCI personality */ | |
366 | enum ecore_pci_personality personality; | |
11fdf7f2 TL |
367 | #define ECORE_IS_RDMA_PERSONALITY(dev) \ |
368 | ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ | |
369 | (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ | |
370 | (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) | |
371 | #define ECORE_IS_ROCE_PERSONALITY(dev) \ | |
372 | ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ | |
373 | (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) | |
374 | #define ECORE_IS_IWARP_PERSONALITY(dev) \ | |
375 | ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ | |
376 | (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) | |
377 | #define ECORE_IS_L2_PERSONALITY(dev) \ | |
378 | ((dev)->hw_info.personality == ECORE_PCI_ETH || \ | |
379 | ECORE_IS_RDMA_PERSONALITY(dev)) | |
380 | #define ECORE_IS_FCOE_PERSONALITY(dev) \ | |
381 | ((dev)->hw_info.personality == ECORE_PCI_FCOE) | |
382 | #define ECORE_IS_ISCSI_PERSONALITY(dev) \ | |
383 | ((dev)->hw_info.personality == ECORE_PCI_ISCSI) | |
7c673cae FG |
384 | |
385 | /* Resource Allocation scheme results */ | |
386 | u32 resc_start[ECORE_MAX_RESC]; | |
387 | u32 resc_num[ECORE_MAX_RESC]; | |
388 | u32 feat_num[ECORE_MAX_FEATURES]; | |
389 | ||
390 | #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) | |
391 | #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) | |
392 | #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ | |
393 | RESC_NUM(_p_hwfn, resc)) | |
394 | #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) | |
395 | ||
396 | /* Amount of traffic classes HW supports */ | |
397 | u8 num_hw_tc; | |
398 | ||
399 | /* Amount of TCs which should be active according to DCBx or upper layer driver | |
400 | * configuration | |
401 | */ | |
402 | ||
403 | u8 num_active_tc; | |
404 | ||
7c673cae FG |
405 | /* The traffic class used by PF for it's offloaded protocol */ |
406 | u8 offload_tc; | |
407 | ||
408 | u32 concrete_fid; | |
409 | u16 opaque_fid; | |
410 | u16 ovlan; | |
411 | u32 part_num[4]; | |
412 | ||
413 | unsigned char hw_mac_addr[ETH_ALEN]; | |
414 | u64 node_wwn; /* For FCoE only */ | |
415 | u64 port_wwn; /* For FCoE only */ | |
416 | ||
417 | u16 num_iscsi_conns; | |
418 | u16 num_fcoe_conns; | |
419 | ||
420 | struct ecore_igu_info *p_igu_info; | |
421 | /* Sriov */ | |
422 | u8 max_chains_per_vf; | |
423 | ||
424 | u32 port_mode; | |
425 | u32 hw_mode; | |
426 | unsigned long device_capabilities; | |
7c673cae | 427 | |
11fdf7f2 TL |
428 | /* Default DCBX mode */ |
429 | u8 dcbx_mode; | |
7c673cae | 430 | |
11fdf7f2 | 431 | u16 mtu; |
7c673cae FG |
432 | }; |
433 | ||
434 | /* maximun size of read/write commands (HW limit) */ | |
435 | #define DMAE_MAX_RW_SIZE 0x2000 | |
436 | ||
437 | struct ecore_dmae_info { | |
11fdf7f2 TL |
438 | /* Spinlock for synchronizing access to functions */ |
439 | osal_spinlock_t lock; | |
440 | ||
441 | bool b_mem_ready; | |
7c673cae FG |
442 | |
443 | u8 channel; | |
444 | ||
445 | dma_addr_t completion_word_phys_addr; | |
446 | ||
447 | /* The memory location where the DMAE writes the completion | |
448 | * value when an operation is finished on this context. | |
449 | */ | |
450 | u32 *p_completion_word; | |
451 | ||
452 | dma_addr_t intermediate_buffer_phys_addr; | |
453 | ||
454 | /* An intermediate buffer for DMAE operations that use virtual | |
455 | * addresses - data is DMA'd to/from this buffer and then | |
456 | * memcpy'd to/from the virtual address | |
457 | */ | |
458 | u32 *p_intermediate_buffer; | |
459 | ||
460 | dma_addr_t dmae_cmd_phys_addr; | |
461 | struct dmae_cmd *p_dmae_cmd; | |
462 | }; | |
463 | ||
464 | struct ecore_wfq_data { | |
465 | u32 default_min_speed; /* When wfq feature is not configured */ | |
466 | u32 min_speed; /* when feature is configured for any 1 vport */ | |
467 | bool configured; | |
468 | }; | |
469 | ||
f67539c2 TL |
470 | #define OFLD_GRP_SIZE 4 |
471 | ||
7c673cae FG |
472 | struct ecore_qm_info { |
473 | struct init_qm_pq_params *qm_pq_params; | |
474 | struct init_qm_vport_params *qm_vport_params; | |
475 | struct init_qm_port_params *qm_port_params; | |
476 | u16 start_pq; | |
477 | u8 start_vport; | |
11fdf7f2 TL |
478 | u16 pure_lb_pq; |
479 | u16 offload_pq; | |
480 | u16 pure_ack_pq; | |
481 | u16 ooo_pq; | |
482 | u16 first_vf_pq; | |
483 | u16 first_mcos_pq; | |
484 | u16 first_rl_pq; | |
7c673cae FG |
485 | u16 num_pqs; |
486 | u16 num_vf_pqs; | |
487 | u8 num_vports; | |
488 | u8 max_phys_tcs_per_port; | |
11fdf7f2 | 489 | u8 ooo_tc; |
7c673cae FG |
490 | bool pf_rl_en; |
491 | bool pf_wfq_en; | |
492 | bool vport_rl_en; | |
493 | bool vport_wfq_en; | |
494 | u8 pf_wfq; | |
495 | u32 pf_rl; | |
496 | struct ecore_wfq_data *wfq_data; | |
497 | u8 num_pf_rls; | |
498 | }; | |
499 | ||
11fdf7f2 TL |
500 | struct ecore_db_recovery_info { |
501 | osal_list_t list; | |
502 | osal_spinlock_t lock; | |
503 | u32 db_recovery_counter; | |
504 | }; | |
505 | ||
7c673cae FG |
506 | struct storm_stats { |
507 | u32 address; | |
508 | u32 len; | |
509 | }; | |
510 | ||
511 | struct ecore_fw_data { | |
512 | #ifdef CONFIG_ECORE_BINARY_FW | |
513 | struct fw_ver_info *fw_ver_info; | |
514 | #endif | |
515 | const u8 *modes_tree_buf; | |
516 | union init_op *init_ops; | |
517 | const u32 *arr_data; | |
f67539c2 TL |
518 | const u32 *fw_overlays; |
519 | u32 fw_overlays_len; | |
7c673cae FG |
520 | u32 init_ops_size; |
521 | }; | |
522 | ||
11fdf7f2 TL |
523 | enum ecore_mf_mode_bit { |
524 | /* Supports PF-classification based on tag */ | |
525 | ECORE_MF_OVLAN_CLSS, | |
526 | ||
527 | /* Supports PF-classification based on MAC */ | |
528 | ECORE_MF_LLH_MAC_CLSS, | |
529 | ||
530 | /* Supports PF-classification based on protocol type */ | |
531 | ECORE_MF_LLH_PROTO_CLSS, | |
532 | ||
533 | /* Requires a default PF to be set */ | |
534 | ECORE_MF_NEED_DEF_PF, | |
535 | ||
536 | /* Allow LL2 to multicast/broadcast */ | |
537 | ECORE_MF_LL2_NON_UNICAST, | |
538 | ||
539 | /* Allow Cross-PF [& child VFs] Tx-switching */ | |
540 | ECORE_MF_INTER_PF_SWITCH, | |
541 | ||
542 | /* TODO - if we ever re-utilize any of this logic, we can rename */ | |
543 | ECORE_MF_UFP_SPECIFIC, | |
544 | ||
545 | ECORE_MF_DISABLE_ARFS, | |
546 | ||
547 | /* Use vlan for steering */ | |
548 | ECORE_MF_8021Q_TAGGING, | |
549 | ||
550 | /* Use stag for steering */ | |
551 | ECORE_MF_8021AD_TAGGING, | |
9f95a23c TL |
552 | |
553 | /* Allow FIP discovery fallback */ | |
554 | ECORE_MF_FIP_SPECIAL, | |
11fdf7f2 TL |
555 | }; |
556 | ||
557 | enum ecore_ufp_mode { | |
558 | ECORE_UFP_MODE_ETS, | |
559 | ECORE_UFP_MODE_VNIC_BW, | |
560 | }; | |
561 | ||
562 | enum ecore_ufp_pri_type { | |
563 | ECORE_UFP_PRI_OS, | |
564 | ECORE_UFP_PRI_VNIC | |
565 | }; | |
566 | ||
567 | struct ecore_ufp_info { | |
568 | enum ecore_ufp_pri_type pri_type; | |
569 | enum ecore_ufp_mode mode; | |
570 | u8 tc; | |
571 | }; | |
572 | ||
573 | enum BAR_ID { | |
574 | BAR_ID_0, /* used for GRC */ | |
575 | BAR_ID_1 /* Used for doorbells */ | |
576 | }; | |
577 | ||
7c673cae FG |
578 | struct ecore_hwfn { |
579 | struct ecore_dev *p_dev; | |
580 | u8 my_id; /* ID inside the PF */ | |
581 | #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) | |
582 | u8 rel_pf_id; /* Relative to engine*/ | |
583 | u8 abs_pf_id; | |
11fdf7f2 TL |
584 | #define ECORE_PATH_ID(_p_hwfn) \ |
585 | (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0) | |
7c673cae FG |
586 | u8 port_id; |
587 | bool b_active; | |
588 | ||
589 | u32 dp_module; | |
590 | u8 dp_level; | |
591 | char name[NAME_SIZE]; | |
11fdf7f2 | 592 | void *dp_ctx; |
7c673cae FG |
593 | |
594 | bool first_on_engine; | |
595 | bool hw_init_done; | |
596 | ||
597 | u8 num_funcs_on_engine; | |
598 | u8 enabled_func_idx; | |
f67539c2 | 599 | u8 num_funcs_on_port; |
7c673cae FG |
600 | |
601 | /* BAR access */ | |
602 | void OSAL_IOMEM *regview; | |
603 | void OSAL_IOMEM *doorbells; | |
604 | u64 db_phys_addr; | |
605 | unsigned long db_size; | |
606 | ||
607 | /* PTT pool */ | |
608 | struct ecore_ptt_pool *p_ptt_pool; | |
609 | ||
610 | /* HW info */ | |
611 | struct ecore_hw_info hw_info; | |
612 | ||
613 | /* rt_array (for init-tool) */ | |
614 | struct ecore_rt_data rt_data; | |
615 | ||
616 | /* SPQ */ | |
617 | struct ecore_spq *p_spq; | |
618 | ||
619 | /* EQ */ | |
620 | struct ecore_eq *p_eq; | |
621 | ||
622 | /* Consolidate Q*/ | |
623 | struct ecore_consq *p_consq; | |
624 | ||
625 | /* Slow-Path definitions */ | |
626 | osal_dpc_t sp_dpc; | |
627 | bool b_sp_dpc_enabled; | |
628 | ||
629 | struct ecore_ptt *p_main_ptt; | |
630 | struct ecore_ptt *p_dpc_ptt; | |
631 | ||
632 | struct ecore_sb_sp_info *p_sp_sb; | |
633 | struct ecore_sb_attn_info *p_sb_attn; | |
634 | ||
635 | /* Protocol related */ | |
636 | bool using_ll2; | |
637 | struct ecore_ll2_info *p_ll2_info; | |
638 | struct ecore_ooo_info *p_ooo_info; | |
639 | struct ecore_iscsi_info *p_iscsi_info; | |
640 | struct ecore_fcoe_info *p_fcoe_info; | |
641 | struct ecore_rdma_info *p_rdma_info; | |
642 | struct ecore_pf_params pf_params; | |
643 | ||
644 | bool b_rdma_enabled_in_prs; | |
645 | u32 rdma_prs_search_reg; | |
646 | ||
7c673cae FG |
647 | struct ecore_cxt_mngr *p_cxt_mngr; |
648 | ||
649 | /* Flag indicating whether interrupts are enabled or not*/ | |
650 | bool b_int_enabled; | |
651 | bool b_int_requested; | |
652 | ||
653 | /* True if the driver requests for the link */ | |
654 | bool b_drv_link_init; | |
655 | ||
656 | struct ecore_vf_iov *vf_iov_info; | |
657 | struct ecore_pf_iov *pf_iov_info; | |
658 | struct ecore_mcp_info *mcp_info; | |
659 | struct ecore_dcbx_info *p_dcbx_info; | |
11fdf7f2 | 660 | struct ecore_ufp_info ufp_info; |
7c673cae FG |
661 | |
662 | struct ecore_dmae_info dmae_info; | |
663 | ||
664 | /* QM init */ | |
665 | struct ecore_qm_info qm_info; | |
666 | ||
667 | #ifdef CONFIG_ECORE_ZIPPED_FW | |
668 | /* Buffer for unzipping firmware data */ | |
669 | void *unzip_buf; | |
670 | #endif | |
671 | ||
672 | struct dbg_tools_data dbg_info; | |
9f95a23c | 673 | void *dbg_user_info; |
7c673cae FG |
674 | |
675 | struct z_stream_s *stream; | |
676 | ||
677 | /* PWM region specific data */ | |
678 | u32 dpi_size; | |
679 | u32 dpi_count; | |
680 | u32 dpi_start_offset; /* this is used to | |
681 | * calculate th | |
682 | * doorbell address | |
683 | */ | |
684 | ||
685 | /* If one of the following is set then EDPM shouldn't be used */ | |
686 | u8 dcbx_no_edpm; | |
687 | u8 db_bar_no_edpm; | |
11fdf7f2 TL |
688 | |
689 | /* L2-related */ | |
690 | struct ecore_l2_info *p_l2_info; | |
691 | ||
692 | /* Mechanism for recovering from doorbell drop */ | |
693 | struct ecore_db_recovery_info db_recovery_info; | |
694 | ||
695 | /* Enable/disable pacing, if request to enable then | |
696 | * IOV and mcos configuration will be skipped. | |
697 | * this actually reflects the value requested in | |
698 | * struct ecore_hw_prepare_params by ecore client. | |
699 | */ | |
700 | bool b_en_pacing; | |
701 | ||
f67539c2 TL |
702 | struct phys_mem_desc *fw_overlay_mem; |
703 | ||
11fdf7f2 TL |
704 | /* @DPDK */ |
705 | struct ecore_ptt *p_arfs_ptt; | |
7c673cae FG |
706 | }; |
707 | ||
7c673cae FG |
708 | enum ecore_mf_mode { |
709 | ECORE_MF_DEFAULT, | |
710 | ECORE_MF_OVLAN, | |
711 | ECORE_MF_NPAR, | |
11fdf7f2 | 712 | ECORE_MF_UFP, |
7c673cae | 713 | }; |
7c673cae FG |
714 | |
715 | /* @DPDK */ | |
716 | struct ecore_dbg_feature { | |
717 | u8 *dump_buf; | |
718 | u32 buf_size; | |
719 | u32 dumped_dwords; | |
720 | }; | |
721 | ||
722 | enum qed_dbg_features { | |
723 | DBG_FEATURE_BUS, | |
724 | DBG_FEATURE_GRC, | |
725 | DBG_FEATURE_IDLE_CHK, | |
726 | DBG_FEATURE_MCP_TRACE, | |
727 | DBG_FEATURE_REG_FIFO, | |
728 | DBG_FEATURE_PROTECTION_OVERRIDE, | |
729 | DBG_FEATURE_NUM | |
730 | }; | |
731 | ||
11fdf7f2 TL |
732 | enum ecore_dev_type { |
733 | ECORE_DEV_TYPE_BB, | |
734 | ECORE_DEV_TYPE_AH, | |
735 | }; | |
736 | ||
7c673cae FG |
737 | struct ecore_dev { |
738 | u32 dp_module; | |
739 | u8 dp_level; | |
740 | char name[NAME_SIZE]; | |
11fdf7f2 | 741 | void *dp_ctx; |
7c673cae | 742 | |
11fdf7f2 | 743 | enum ecore_dev_type type; |
7c673cae FG |
744 | /* Translate type/revision combo into the proper conditions */ |
745 | #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB) | |
746 | #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev)) | |
747 | #ifndef ASIC_ONLY | |
748 | #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \ | |
749 | (CHIP_REV_IS_TEDIBEAR(dev))) | |
750 | #else | |
751 | #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) | |
752 | #endif | |
753 | #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH) | |
754 | #define ECORE_IS_K2(dev) ECORE_IS_AH(dev) | |
755 | ||
756 | u16 vendor_id; | |
757 | u16 device_id; | |
11fdf7f2 TL |
758 | #define ECORE_DEV_ID_MASK 0xff00 |
759 | #define ECORE_DEV_ID_MASK_BB 0x1600 | |
760 | #define ECORE_DEV_ID_MASK_AH 0x8000 | |
7c673cae FG |
761 | |
762 | u16 chip_num; | |
11fdf7f2 TL |
763 | #define CHIP_NUM_MASK 0xffff |
764 | #define CHIP_NUM_SHIFT 0 | |
7c673cae | 765 | |
11fdf7f2 TL |
766 | u8 chip_rev; |
767 | #define CHIP_REV_MASK 0xf | |
768 | #define CHIP_REV_SHIFT 0 | |
7c673cae | 769 | #ifndef ASIC_ONLY |
11fdf7f2 TL |
770 | #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) |
771 | #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) | |
772 | #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) | |
773 | #define CHIP_REV_IS_EMUL(_p_dev) \ | |
774 | (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev)) | |
775 | #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) | |
776 | #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) | |
777 | #define CHIP_REV_IS_FPGA(_p_dev) \ | |
778 | (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev)) | |
779 | #define CHIP_REV_IS_SLOW(_p_dev) \ | |
780 | (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) | |
781 | #define CHIP_REV_IS_A0(_p_dev) \ | |
782 | (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \ | |
783 | (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)) | |
784 | #define CHIP_REV_IS_B0(_p_dev) \ | |
785 | (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \ | |
786 | ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)) | |
787 | #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) | |
7c673cae | 788 | #else |
11fdf7f2 TL |
789 | #define CHIP_REV_IS_A0(_p_dev) \ |
790 | (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal) | |
791 | #define CHIP_REV_IS_B0(_p_dev) \ | |
792 | ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal) | |
7c673cae FG |
793 | #endif |
794 | ||
11fdf7f2 TL |
795 | u8 chip_metal; |
796 | #define CHIP_METAL_MASK 0xff | |
797 | #define CHIP_METAL_SHIFT 0 | |
7c673cae | 798 | |
11fdf7f2 TL |
799 | u8 chip_bond_id; |
800 | #define CHIP_BOND_ID_MASK 0xff | |
801 | #define CHIP_BOND_ID_SHIFT 0 | |
7c673cae FG |
802 | |
803 | u8 num_engines; | |
11fdf7f2 TL |
804 | u8 num_ports; |
805 | u8 num_ports_in_engine; | |
7c673cae FG |
806 | u8 num_funcs_in_port; |
807 | ||
808 | u8 path_id; | |
11fdf7f2 TL |
809 | |
810 | unsigned long mf_bits; | |
7c673cae | 811 | enum ecore_mf_mode mf_mode; |
11fdf7f2 TL |
812 | #define IS_MF_DEFAULT(_p_hwfn) \ |
813 | (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) | |
814 | #define IS_MF_SI(_p_hwfn) \ | |
815 | (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) | |
816 | #define IS_MF_SD(_p_hwfn) \ | |
817 | (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) | |
7c673cae FG |
818 | |
819 | int pcie_width; | |
820 | int pcie_speed; | |
11fdf7f2 | 821 | |
7c673cae FG |
822 | /* Add MF related configuration */ |
823 | u8 mcp_rev; | |
824 | u8 boot_mode; | |
825 | ||
826 | u8 wol; | |
827 | ||
828 | u32 int_mode; | |
829 | enum ecore_coalescing_mode int_coalescing_mode; | |
830 | u16 rx_coalesce_usecs; | |
831 | u16 tx_coalesce_usecs; | |
832 | ||
833 | /* Start Bar offset of first hwfn */ | |
834 | void OSAL_IOMEM *regview; | |
835 | void OSAL_IOMEM *doorbells; | |
836 | u64 db_phys_addr; | |
837 | unsigned long db_size; | |
838 | ||
839 | /* PCI */ | |
840 | u8 cache_shift; | |
841 | ||
842 | /* Init */ | |
f67539c2 TL |
843 | const u32 *iro_arr; |
844 | #define IRO ((const struct iro *)p_hwfn->p_dev->iro_arr) | |
7c673cae FG |
845 | |
846 | /* HW functions */ | |
847 | u8 num_hwfns; | |
848 | struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; | |
9f95a23c | 849 | #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) |
11fdf7f2 | 850 | #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1) |
7c673cae | 851 | |
9f95a23c TL |
852 | /* Engine affinity */ |
853 | u8 l2_affin_hint; | |
854 | u8 fir_affin; | |
855 | u8 iwarp_affin; | |
856 | /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */ | |
857 | #define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin]) | |
858 | /* Macro for getting the engine-affinitized hwfn for iWARP */ | |
859 | #define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin]) | |
860 | /* Generic macro for getting the engine-affinitized hwfn */ | |
861 | #define ECORE_AFFIN_HWFN(dev) \ | |
862 | (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \ | |
863 | ECORE_IWARP_AFFIN_HWFN(dev) : \ | |
864 | ECORE_FIR_AFFIN_HWFN(dev)) | |
865 | /* Macro for getting the index (0/1) of the engine-affinitized hwfn */ | |
866 | #define ECORE_AFFIN_HWFN_IDX(dev) \ | |
867 | (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1) | |
868 | ||
7c673cae FG |
869 | /* SRIOV */ |
870 | struct ecore_hw_sriov_info *p_iov_info; | |
871 | #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info) | |
11fdf7f2 | 872 | struct ecore_tunnel_info tunnel; |
7c673cae | 873 | bool b_is_vf; |
11fdf7f2 | 874 | bool b_dont_override_vf_msix; |
7c673cae FG |
875 | |
876 | u32 drv_type; | |
877 | ||
878 | u32 rdma_max_sge; | |
879 | u32 rdma_max_inline; | |
880 | u32 rdma_max_srq_sge; | |
881 | ||
882 | struct ecore_eth_stats *reset_stats; | |
883 | struct ecore_fw_data *fw_data; | |
884 | ||
885 | u32 mcp_nvm_resp; | |
886 | ||
887 | /* Recovery */ | |
888 | bool recov_in_prog; | |
889 | ||
890 | /* Indicates whether should prevent attentions from being reasserted */ | |
891 | ||
892 | bool attn_clr_en; | |
893 | ||
894 | /* Indicates whether allowing the MFW to collect a crash dump */ | |
11fdf7f2 | 895 | bool allow_mdump; |
7c673cae FG |
896 | |
897 | /* Indicates if the reg_fifo is checked after any register access */ | |
898 | bool chk_reg_fifo; | |
899 | ||
900 | #ifndef ASIC_ONLY | |
901 | bool b_is_emul_full; | |
f67539c2 | 902 | bool b_is_emul_mac; |
7c673cae | 903 | #endif |
9f95a23c TL |
904 | /* LLH info */ |
905 | u8 ppfid_bitmap; | |
906 | struct ecore_llh_info *p_llh_info; | |
907 | ||
908 | /* Indicates whether this PF serves a storage target */ | |
909 | bool b_is_target; | |
7c673cae FG |
910 | |
911 | #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */ | |
912 | void *firmware; | |
913 | u64 fw_len; | |
914 | #endif | |
915 | ||
916 | /* @DPDK */ | |
917 | struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM]; | |
918 | u8 engine_for_debug; | |
919 | }; | |
920 | ||
f67539c2 TL |
921 | enum ecore_hsi_def_type { |
922 | ECORE_HSI_DEF_MAX_NUM_VFS, | |
923 | ECORE_HSI_DEF_MAX_NUM_L2_QUEUES, | |
924 | ECORE_HSI_DEF_MAX_NUM_PORTS, | |
925 | ECORE_HSI_DEF_MAX_SB_PER_PATH, | |
926 | ECORE_HSI_DEF_MAX_NUM_PFS, | |
927 | ECORE_HSI_DEF_MAX_NUM_VPORTS, | |
928 | ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE, | |
929 | ECORE_HSI_DEF_MAX_QM_TX_QUEUES, | |
930 | ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS, | |
931 | ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS, | |
932 | ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS, | |
933 | ECORE_HSI_DEF_MAX_PBF_CMD_LINES, | |
934 | ECORE_HSI_DEF_MAX_BTB_BLOCKS, | |
935 | ECORE_NUM_HSI_DEFS | |
936 | }; | |
937 | ||
938 | u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev, | |
939 | enum ecore_hsi_def_type type); | |
940 | ||
941 | #define NUM_OF_VFS(dev) \ | |
942 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VFS) | |
943 | #define NUM_OF_L2_QUEUES(dev) \ | |
944 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_L2_QUEUES) | |
945 | #define NUM_OF_PORTS(dev) \ | |
946 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PORTS) | |
947 | #define NUM_OF_SBS(dev) \ | |
948 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_SB_PER_PATH) | |
949 | #define NUM_OF_ENG_PFS(dev) \ | |
950 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PFS) | |
951 | #define NUM_OF_VPORTS(dev) \ | |
952 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VPORTS) | |
953 | #define NUM_OF_RSS_ENGINES(dev) \ | |
954 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE) | |
955 | #define NUM_OF_QM_TX_QUEUES(dev) \ | |
956 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_TX_QUEUES) | |
957 | #define NUM_OF_PXP_ILT_RECORDS(dev) \ | |
958 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS) | |
959 | #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \ | |
960 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS) | |
961 | #define NUM_OF_QM_GLOBAL_RLS(dev) \ | |
962 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS) | |
963 | #define NUM_OF_PBF_CMD_LINES(dev) \ | |
964 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_PBF_CMD_LINES) | |
965 | #define NUM_OF_BTB_BLOCKS(dev) \ | |
966 | ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_BTB_BLOCKS) | |
7c673cae | 967 | |
11fdf7f2 | 968 | #define CRC8_TABLE_SIZE 256 |
7c673cae FG |
969 | |
970 | /** | |
971 | * @brief ecore_concrete_to_sw_fid - get the sw function id from | |
972 | * the concrete value. | |
973 | * | |
974 | * @param concrete_fid | |
975 | * | |
976 | * @return OSAL_INLINE u8 | |
977 | */ | |
11fdf7f2 | 978 | static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid) |
7c673cae FG |
979 | { |
980 | u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); | |
981 | u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); | |
982 | u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID); | |
983 | u8 sw_fid; | |
984 | ||
985 | if (vf_valid) | |
986 | sw_fid = vfid + MAX_NUM_PFS; | |
987 | else | |
988 | sw_fid = pfid; | |
989 | ||
990 | return sw_fid; | |
991 | } | |
992 | ||
11fdf7f2 | 993 | #define PKT_LB_TC 9 |
7c673cae FG |
994 | |
995 | int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); | |
996 | void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, | |
11fdf7f2 | 997 | struct ecore_ptt *p_ptt, |
7c673cae FG |
998 | u32 min_pf_rate); |
999 | ||
1000 | int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw); | |
1001 | int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw); | |
1002 | void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); | |
1003 | int ecore_device_num_engines(struct ecore_dev *p_dev); | |
1004 | int ecore_device_num_ports(struct ecore_dev *p_dev); | |
11fdf7f2 TL |
1005 | void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, |
1006 | u8 *mac); | |
1007 | ||
1008 | /* Flags for indication of required queues */ | |
1009 | #define PQ_FLAGS_RLS (1 << 0) | |
1010 | #define PQ_FLAGS_MCOS (1 << 1) | |
1011 | #define PQ_FLAGS_LB (1 << 2) | |
1012 | #define PQ_FLAGS_OOO (1 << 3) | |
1013 | #define PQ_FLAGS_ACK (1 << 4) | |
1014 | #define PQ_FLAGS_OFLD (1 << 5) | |
1015 | #define PQ_FLAGS_VFS (1 << 6) | |
1016 | #define PQ_FLAGS_LLT (1 << 7) | |
1017 | ||
1018 | /* physical queue index for cm context intialization */ | |
1019 | u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags); | |
1020 | u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc); | |
1021 | u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); | |
1022 | u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl); | |
1023 | ||
1024 | /* qm vport for rate limit configuration */ | |
1025 | u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl); | |
1026 | ||
1027 | const char *ecore_hw_get_resc_name(enum ecore_resources res_id); | |
1028 | ||
1029 | /* doorbell recovery mechanism */ | |
1030 | void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn); | |
1031 | void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, | |
1032 | enum ecore_db_rec_exec); | |
1033 | ||
9f95a23c TL |
1034 | bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn); |
1035 | ||
11fdf7f2 TL |
1036 | /* amount of resources used in qm init */ |
1037 | u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); | |
1038 | u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn); | |
1039 | u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn); | |
1040 | u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn); | |
1041 | u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); | |
7c673cae | 1042 | |
9f95a23c TL |
1043 | #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ |
1044 | ecore_device_num_ports((_p_hwfn)->p_dev)) | |
1045 | ||
1046 | /* The PFID<->PPFID calculation is based on the relative index of a PF on its | |
1047 | * port. In BB there is a bug in the LLH in which the PPFID is actually engine | |
1048 | * based, and thus it equals the PFID. | |
1049 | */ | |
1050 | #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \ | |
1051 | (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ | |
1052 | (abs_ppfid) : \ | |
1053 | (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \ | |
1054 | MFW_PORT(_p_hwfn)) | |
1055 | #define ECORE_PPFID_BY_PFID(_p_hwfn) \ | |
1056 | (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ | |
1057 | (_p_hwfn)->rel_pf_id : \ | |
1058 | (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine) | |
1059 | ||
1060 | enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn, | |
1061 | struct ecore_ptt *p_ptt, u32 addr, | |
1062 | u32 val); | |
1063 | ||
1064 | /* Utility functions for dumping the content of the NIG LLH filters */ | |
1065 | enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid); | |
1066 | enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev); | |
7c673cae | 1067 | |
f67539c2 TL |
1068 | #define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A |
1069 | ||
1070 | #define MSTORM_QZONE_START(dev) \ | |
1071 | (TSTORM_QZONE_START + (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev))) | |
1072 | ||
7c673cae | 1073 | #endif /* __ECORE_H */ |