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update source to Ceph Pacific 16.2.2
[ceph.git] / ceph / src / spdk / dpdk / drivers / net / qede / base / ecore_cxt.c
CommitLineData
11fdf7f2
TL		 1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7c673cae 3 * All rights reserved.
11fdf7f2 4 * www.cavium.com
7c673cae
FG		 5 */
6
7#include "bcm_osal.h"
8#include "reg_addr.h"
11fdf7f2 9#include "common_hsi.h"
7c673cae
FG		 10#include "ecore_hsi_common.h"
11#include "ecore_hsi_eth.h"
12#include "ecore_rt_defs.h"
13#include "ecore_status.h"
14#include "ecore.h"
15#include "ecore_init_ops.h"
16#include "ecore_init_fw_funcs.h"
17#include "ecore_cxt.h"
18#include "ecore_hw.h"
19#include "ecore_dev_api.h"
20#include "ecore_sriov.h"
11fdf7f2 21#include "ecore_mcp.h"
7c673cae
FG		 22
23/* Max number of connection types in HW (DQ/CDU etc.) */
24#define MAX_CONN_TYPES PROTOCOLID_COMMON
25#define NUM_TASK_TYPES 2
26#define NUM_TASK_PF_SEGMENTS 4
27#define NUM_TASK_VF_SEGMENTS 1
28
29/* Doorbell-Queue constants */
30#define DQ_RANGE_SHIFT 4
31#define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT)
32
33/* Searcher constants */
34#define SRC_MIN_NUM_ELEMS 256
35
f67539c2
TL		 36/* GFS constants */
37#define RGFS_MIN_NUM_ELEMS 256
38#define TGFS_MIN_NUM_ELEMS 256
39
7c673cae
FG		 40/* Timers constants */
41#define TM_SHIFT 7
42#define TM_ALIGN (1 << TM_SHIFT)
43#define TM_ELEM_SIZE 4
44
45/* ILT constants */
11fdf7f2 46#define ILT_DEFAULT_HW_P_SIZE 4
7c673cae
FG		 47
48#define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
49#define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
50
51/* ILT entry structure */
52#define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
53#define ILT_ENTRY_PHY_ADDR_SHIFT 0
54#define ILT_ENTRY_VALID_MASK 0x1ULL
55#define ILT_ENTRY_VALID_SHIFT 52
56#define ILT_ENTRY_IN_REGS 2
57#define ILT_REG_SIZE_IN_BYTES 4
58
59/* connection context union */
60union conn_context {
f67539c2
TL		 61 struct core_conn_context core_ctx;
62 struct eth_conn_context eth_ctx;
7c673cae
FG		 63};
64
65/* TYPE-0 task context - iSCSI, FCOE */
66union type0_task_context {
67};
68
69/* TYPE-1 task context - ROCE */
70union type1_task_context {
11fdf7f2 71 struct regpair reserved; /* @DPDK */
7c673cae
FG		 72};
73
74struct src_ent {
75 u8 opaque[56];
76 u64 next;
77};
78
79#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
80#define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
81
82#define CONN_CXT_SIZE(p_hwfn) \
83 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
84
85#define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
86
87#define TYPE0_TASK_CXT_SIZE(p_hwfn) \
88 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
89
90/* Alignment is inherent to the type1_task_context structure */
91#define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
92
93/* PF per protocl configuration object */
94#define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
95#define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
96
97struct ecore_tid_seg {
98 u32 count;
99 u8 type;
100 bool has_fl_mem;
101};
102
103struct ecore_conn_type_cfg {
104 u32 cid_count;
7c673cae
FG		 105 u32 cids_per_vf;
106 struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
107};
108
109/* ILT Client configuration,
110 * Per connection type (protocol) resources (cids, tis, vf cids etc.)
111 * 1 - for connection context (CDUC) and for each task context we need two
112 * values, for regular task context and for force load memory
113 */
114#define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
115#define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
116#define CDUC_BLK (0)
117#define SRQ_BLK (0)
118#define CDUT_SEG_BLK(n) (1 + (u8)(n))
119#define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
120
7c673cae
FG		 121struct ilt_cfg_pair {
122 u32 reg;
123 u32 val;
124};
125
126struct ecore_ilt_cli_blk {
127 u32 total_size; /* 0 means not active */
128 u32 real_size_in_page;
129 u32 start_line;
f67539c2 130 u32 dynamic_line_offset;
7c673cae
FG		 131 u32 dynamic_line_cnt;
132};
133
134struct ecore_ilt_client_cfg {
135 bool active;
136
137 /* ILT boundaries */
138 struct ilt_cfg_pair first;
139 struct ilt_cfg_pair last;
140 struct ilt_cfg_pair p_size;
141
142 /* ILT client blocks for PF */
143 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
144 u32 pf_total_lines;
145
146 /* ILT client blocks for VFs */
147 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
148 u32 vf_total_lines;
149};
150
7c673cae
FG		 151#define MAP_WORD_SIZE sizeof(unsigned long)
152#define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8)
153
154struct ecore_cid_acquired_map {
155 u32 start_cid;
156 u32 max_count;
157 unsigned long *cid_map;
158};
159
f67539c2
TL		 160struct ecore_src_t2 {
161 struct phys_mem_desc *dma_mem;
162 u32 num_pages;
163 u64 first_free;
164 u64 last_free;
165};
166
7c673cae
FG		 167struct ecore_cxt_mngr {
168 /* Per protocl configuration */
169 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
170
171 /* computed ILT structure */
172 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
173
174 /* Task type sizes */
175 u32 task_type_size[NUM_TASK_TYPES];
176
177 /* total number of VFs for this hwfn -
178 * ALL VFs are symmetric in terms of HW resources
179 */
180 u32 vf_count;
181
7c673cae
FG		 182 /* Acquired CIDs */
183 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
f67539c2 184 struct ecore_cid_acquired_map *acquired_vf[MAX_CONN_TYPES];
7c673cae
FG		 185
186 /* ILT shadow table */
f67539c2 187 struct phys_mem_desc *ilt_shadow;
7c673cae
FG		 188 u32 pf_start_line;
189
190 /* Mutex for a dynamic ILT allocation */
191 osal_mutex_t mutex;
192
193 /* SRC T2 */
f67539c2 194 struct ecore_src_t2 src_t2;
7c673cae 195
11fdf7f2
TL		 196 /* The infrastructure originally was very generic and context/task
197 * oriented - per connection-type we would set how many of those
198 * are needed, and later when determining how much memory we're
199 * needing for a given block we'd iterate over all the relevant
200 * connection-types.
201 * But since then we've had some additional resources, some of which
202 * require memory which is indepent of the general context/task
203 * scheme. We add those here explicitly per-feature.
204 */
205
206 /* total number of SRQ's for this hwfn */
207 u32 srq_count;
208
209 /* Maximal number of L2 steering filters */
210 u32 arfs_count;
211
212 /* TODO - VF arfs filters ? */
213};
7c673cae
FG		 214
215static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
216{
217 return type == PROTOCOLID_TOE;
218}
219
220static bool tm_tid_proto(enum protocol_type type)
221{
222 return type == PROTOCOLID_FCOE;
223}
224
225/* counts the iids for the CDU/CDUC ILT client configuration */
226struct ecore_cdu_iids {
227 u32 pf_cids;
228 u32 per_vf_cids;
229};
230
231static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
232 struct ecore_cdu_iids *iids)
233{
234 u32 type;
235
236 for (type = 0; type < MAX_CONN_TYPES; type++) {
237 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
238 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
239 }
240}
241
242/* counts the iids for the Searcher block configuration */
243struct ecore_src_iids {
244 u32 pf_cids;
245 u32 per_vf_cids;
246};
247
11fdf7f2
TL		 248static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
249 struct ecore_src_iids *iids)
7c673cae
FG		 250{
251 u32 i;
252
253 for (i = 0; i < MAX_CONN_TYPES; i++) {
7c673cae
FG		 254 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
255 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
256 }
11fdf7f2
TL		 257
258 /* Add L2 filtering filters in addition */
259 iids->pf_cids += p_mngr->arfs_count;
7c673cae
FG		 260}
261
262/* counts the iids for the Timers block configuration */
263struct ecore_tm_iids {
264 u32 pf_cids;
265 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
266 u32 pf_tids_total;
267 u32 per_vf_cids;
268 u32 per_vf_tids;
269};
270
f67539c2
TL		 271static void ecore_cxt_tm_iids(struct ecore_hwfn *p_hwfn,
272 struct ecore_cxt_mngr *p_mngr,
11fdf7f2 273 struct ecore_tm_iids *iids)
7c673cae 274{
f67539c2 275 struct ecore_conn_type_cfg *p_cfg;
11fdf7f2
TL		 276 bool tm_vf_required = false;
277 bool tm_required = false;
7c673cae
FG		 278 u32 i, j;
279
280 for (i = 0; i < MAX_CONN_TYPES; i++) {
f67539c2 281 p_cfg = &p_mngr->conn_cfg[i];
7c673cae 282
11fdf7f2
TL		 283 if (tm_cid_proto(i) || tm_required) {
284 if (p_cfg->cid_count)
285 tm_required = true;
286
7c673cae 287 iids->pf_cids += p_cfg->cid_count;
11fdf7f2
TL		 288 }
289
290 if (tm_cid_proto(i) || tm_vf_required) {
291 if (p_cfg->cids_per_vf)
292 tm_vf_required = true;
293
7c673cae
FG		 294 }
295
296 if (tm_tid_proto(i)) {
297 struct ecore_tid_seg *segs = p_cfg->tid_seg;
298
299 /* for each segment there is at most one
300 * protocol for which count is not 0.
301 */
302 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
303 iids->pf_tids[j] += segs[j].count;
304
305 /* The last array elelment is for the VFs. As for PF
306 * segments there can be only one protocol for
307 * which this value is not 0.
308 */
309 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
310 }
311 }
312
313 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
314 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
315 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
316
317 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
318 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
319 iids->pf_tids_total += iids->pf_tids[j];
320 }
321}
322
11fdf7f2
TL		 323static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
324 struct ecore_qm_iids *iids)
7c673cae
FG		 325{
326 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
327 struct ecore_tid_seg *segs;
328 u32 vf_cids = 0, type, j;
329 u32 vf_tids = 0;
330
331 for (type = 0; type < MAX_CONN_TYPES; type++) {
332 iids->cids += p_mngr->conn_cfg[type].cid_count;
333 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
334
335 segs = p_mngr->conn_cfg[type].tid_seg;
336 /* for each segment there is at most one
337 * protocol for which count is not 0.
338 */
339 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
340 iids->tids += segs[j].count;
341
342 /* The last array elelment is for the VFs. As for PF
343 * segments there can be only one protocol for
344 * which this value is not 0.
345 */
346 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
347 }
348
349 iids->vf_cids += vf_cids * p_mngr->vf_count;
350 iids->tids += vf_tids * p_mngr->vf_count;
351
352 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
353 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
354 iids->cids, iids->vf_cids, iids->tids, vf_tids);
355}
356
357static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
358 u32 seg)
359{
360 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
361 u32 i;
362
363 /* Find the protocol with tid count > 0 for this segment.
364 * Note: there can only be one and this is already validated.
365 */
366 for (i = 0; i < MAX_CONN_TYPES; i++) {
367 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
368 return &p_cfg->conn_cfg[i].tid_seg[seg];
369 }
370 return OSAL_NULL;
371}
372
11fdf7f2
TL		 373static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
374{
375 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
376
377 p_mgr->srq_count = num_srqs;
378}
379
380u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
381{
382 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
383
384 return p_mgr->srq_count;
385}
386
7c673cae
FG		 387/* set the iids (cid/tid) count per protocol */
388static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
389 enum protocol_type type,
390 u32 cid_count, u32 vf_cid_cnt)
391{
392 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
393 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
394
395 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
396 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
397}
398
399u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
400 enum protocol_type type, u32 *vf_cid)
401{
402 if (vf_cid)
403 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
404
405 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
406}
407
408u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
409 enum protocol_type type)
410{
411 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
412}
413
414u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
415 enum protocol_type type)
416{
417 u32 cnt = 0;
418 int i;
419
420 for (i = 0; i < TASK_SEGMENTS; i++)
421 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
422
423 return cnt;
424}
425
426static OSAL_INLINE void
427ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
428 enum protocol_type proto,
429 u8 seg, u8 seg_type, u32 count, bool has_fl)
430{
431 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
432 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
433
434 p_seg->count = count;
435 p_seg->has_fl_mem = has_fl;
436 p_seg->type = seg_type;
437}
438
439/* the *p_line parameter must be either 0 for the first invocation or the
440 * value returned in the previous invocation.
441 */
442static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
443 struct ecore_ilt_cli_blk *p_blk,
444 u32 start_line,
445 u32 total_size, u32 elem_size)
446{
447 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
448
449 /* verify that it's called once for each block */
450 if (p_blk->total_size)
451 return;
452
453 p_blk->total_size = total_size;
454 p_blk->real_size_in_page = 0;
455 if (elem_size)
456 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
457 p_blk->start_line = start_line;
458}
459
460static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
461 struct ecore_ilt_client_cfg *p_cli,
462 struct ecore_ilt_cli_blk *p_blk,
463 u32 *p_line, enum ilt_clients client_id)
464{
465 if (!p_blk->total_size)
466 return;
467
468 if (!p_cli->active)
469 p_cli->first.val = *p_line;
470
471 p_cli->active = true;
472 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
473 p_cli->last.val = *p_line - 1;
474
475 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
476 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
477 " [Real %08x] Start line %d\n",
478 client_id, p_cli->first.val, p_cli->last.val,
479 p_blk->total_size, p_blk->real_size_in_page,
480 p_blk->start_line);
481}
482
f67539c2
TL		 483static void ecore_ilt_get_dynamic_line_range(struct ecore_hwfn *p_hwfn,
484 enum ilt_clients ilt_client,
485 u32 *dynamic_line_offset,
486 u32 *dynamic_line_cnt)
7c673cae 487{
7c673cae 488 struct ecore_ilt_client_cfg *p_cli;
f67539c2 489 struct ecore_conn_type_cfg *p_cfg;
7c673cae
FG		 490 u32 cxts_per_p;
491
492 /* TBD MK: ILT code should be simplified once PROTO enum is changed */
493
f67539c2
TL		 494 *dynamic_line_offset = 0;
495 *dynamic_line_cnt = 0;
496
7c673cae
FG		 497 if (ilt_client == ILT_CLI_CDUC) {
498 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
f67539c2 499 p_cfg = &p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE];
7c673cae
FG		 500
501 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
502 (u32)CONN_CXT_SIZE(p_hwfn);
503
f67539c2
TL		 504 *dynamic_line_cnt = p_cfg->cid_count / cxts_per_p;
505 }
506}
507
508static struct ecore_ilt_client_cfg *
509ecore_cxt_set_cli(struct ecore_ilt_client_cfg *p_cli)
510{
511 p_cli->active = false;
512 p_cli->first.val = 0;
513 p_cli->last.val = 0;
514 return p_cli;
515}
516
517static struct ecore_ilt_cli_blk *
518ecore_cxt_set_blk(struct ecore_ilt_cli_blk *p_blk)
519{
520 p_blk->total_size = 0;
521 return p_blk;
7c673cae
FG		 522 }
523
f67539c2
TL		 524static u32
525ecore_cxt_src_elements(struct ecore_cxt_mngr *p_mngr)
526{
527 struct ecore_src_iids src_iids;
528 u32 elem_num = 0;
529
530 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
531 ecore_cxt_src_iids(p_mngr, &src_iids);
532
533 /* Both the PF and VFs searcher connections are stored in the per PF
534 * database. Thus sum the PF searcher cids and all the VFs searcher
535 * cids.
536 */
537 elem_num = src_iids.pf_cids +
538 src_iids.per_vf_cids * p_mngr->vf_count;
539 if (elem_num == 0)
540 return elem_num;
541
542 elem_num = OSAL_MAX_T(u32, elem_num, SRC_MIN_NUM_ELEMS);
543 elem_num = OSAL_ROUNDUP_POW_OF_TWO(elem_num);
544
545 return elem_num;
7c673cae
FG		 546}
547
548enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
549{
f67539c2 550 u32 curr_line, total, i, task_size, line, total_size, elem_size;
7c673cae 551 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
7c673cae
FG		 552 struct ecore_ilt_client_cfg *p_cli;
553 struct ecore_ilt_cli_blk *p_blk;
554 struct ecore_cdu_iids cdu_iids;
7c673cae
FG		 555 struct ecore_qm_iids qm_iids;
556 struct ecore_tm_iids tm_iids;
557 struct ecore_tid_seg *p_seg;
558
559 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
560 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
7c673cae
FG		 561 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
562
563 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
564
565 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
566 "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
567 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
568
569 /* CDUC */
f67539c2 570 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]);
7c673cae
FG		 571
572 curr_line = p_mngr->pf_start_line;
573
574 /* CDUC PF */
575 p_cli->pf_total_lines = 0;
576
577 /* get the counters for the CDUC,CDUC and QM clients */
578 ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
579
f67539c2 580 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]);
7c673cae
FG		 581
582 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
583
584 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
585 total, CONN_CXT_SIZE(p_hwfn));
586
587 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
588 p_cli->pf_total_lines = curr_line - p_blk->start_line;
589
f67539c2
TL		 590 ecore_ilt_get_dynamic_line_range(p_hwfn, ILT_CLI_CDUC,
591 &p_blk->dynamic_line_offset,
592 &p_blk->dynamic_line_cnt);
7c673cae
FG		 593
594 /* CDUC VF */
f67539c2 595 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]);
7c673cae
FG		 596 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
597
598 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
599 total, CONN_CXT_SIZE(p_hwfn));
600
601 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
602 p_cli->vf_total_lines = curr_line - p_blk->start_line;
603
604 for (i = 1; i < p_mngr->vf_count; i++)
605 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
606 ILT_CLI_CDUC);
607
608 /* CDUT PF */
f67539c2 609 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]);
7c673cae
FG		 610 p_cli->first.val = curr_line;
611
612 /* first the 'working' task memory */
613 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
614 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
615 if (!p_seg || p_seg->count == 0)
616 continue;
617
f67539c2 618 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]);
7c673cae
FG		 619 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
620 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
621 p_mngr->task_type_size[p_seg->type]);
622
623 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
624 ILT_CLI_CDUT);
625 }
626
627 /* next the 'init' task memory (forced load memory) */
628 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
629 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
630 if (!p_seg || p_seg->count == 0)
631 continue;
632
f67539c2
TL		 633 p_blk =
634 ecore_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]);
7c673cae
FG		 635
636 if (!p_seg->has_fl_mem) {
637 /* The segment is active (total size pf 'working'
638 * memory is > 0) but has no FL (forced-load, Init)
639 * memory. Thus:
640 *
641 * 1. The total-size in the corrsponding FL block of
642 * the ILT client is set to 0 - No ILT line are
643 * provisioned and no ILT memory allocated.
644 *
645 * 2. The start-line of said block is set to the
646 * start line of the matching working memory
647 * block in the ILT client. This is later used to
648 * configure the CDU segment offset registers and
649 * results in an FL command for TIDs of this
650 * segment behaves as regular load commands
651 * (loading TIDs from the working memory).
652 */
653 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
654
655 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
656 continue;
657 }
658 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
659
660 ecore_ilt_cli_blk_fill(p_cli, p_blk,
661 curr_line, total,
662 p_mngr->task_type_size[p_seg->type]);
663
664 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
665 ILT_CLI_CDUT);
666 }
f67539c2 667 p_cli->pf_total_lines = curr_line - p_cli->first.val;
7c673cae
FG		 668
669 /* CDUT VF */
670 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
671 if (p_seg && p_seg->count) {
672 /* Stricly speaking we need to iterate over all VF
673 * task segment types, but a VF has only 1 segment
674 */
675
676 /* 'working' memory */
677 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
678
f67539c2 679 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]);
7c673cae
FG		 680 ecore_ilt_cli_blk_fill(p_cli, p_blk,
681 curr_line, total,
682 p_mngr->task_type_size[p_seg->type]);
683
684 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
685 ILT_CLI_CDUT);
686
687 /* 'init' memory */
f67539c2
TL		 688 p_blk =
689 ecore_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]);
7c673cae
FG		 690 if (!p_seg->has_fl_mem) {
691 /* see comment above */
692 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
693 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
694 } else {
695 task_size = p_mngr->task_type_size[p_seg->type];
696 ecore_ilt_cli_blk_fill(p_cli, p_blk,
697 curr_line, total, task_size);
698 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
699 ILT_CLI_CDUT);
700 }
f67539c2
TL		 701 p_cli->vf_total_lines = curr_line - (p_cli->first.val +
702 p_cli->pf_total_lines);
7c673cae
FG		 703
704 /* Now for the rest of the VFs */
705 for (i = 1; i < p_mngr->vf_count; i++) {
f67539c2 706 /* don't set p_blk i.e. don't clear total_size */
7c673cae
FG		 707 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
708 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
709 ILT_CLI_CDUT);
710
f67539c2 711 /* don't set p_blk i.e. don't clear total_size */
7c673cae
FG		 712 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
713 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
714 ILT_CLI_CDUT);
715 }
716 }
717
718 /* QM */
f67539c2
TL		 719 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]);
720 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
721
722 /* At this stage, after the first QM configuration, the PF PQs amount
723 * is the highest possible. Save this value at qm_info->ilt_pf_pqs to
724 * detect overflows in the future.
725 * Even though VF PQs amount can be larger than VF count, use vf_count
726 * because each VF requires only the full amount of CIDs.
727 */
7c673cae 728 ecore_cxt_qm_iids(p_hwfn, &qm_iids);
f67539c2 729 total = ecore_qm_pf_mem_size(p_hwfn, qm_iids.cids,
7c673cae 730 qm_iids.vf_cids, qm_iids.tids,
f67539c2 731 p_hwfn->qm_info.num_pqs + OFLD_GRP_SIZE,
7c673cae
FG		 732 p_hwfn->qm_info.num_vf_pqs);
733
734 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
735 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
736 " num_vf_pqs=%d, memory_size=%d)\n",
737 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
738 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
739
740 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
741 QM_PQ_ELEMENT_SIZE);
742
743 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
744 p_cli->pf_total_lines = curr_line - p_blk->start_line;
745
7c673cae 746 /* TM PF */
f67539c2
TL		 747 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]);
748 ecore_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
7c673cae
FG		 749 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
750 if (total) {
f67539c2 751 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
7c673cae 752 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
f67539c2
TL		 753 total * TM_ELEM_SIZE,
754 TM_ELEM_SIZE);
7c673cae
FG		 755
756 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
757 ILT_CLI_TM);
758 p_cli->pf_total_lines = curr_line - p_blk->start_line;
759 }
760
761 /* TM VF */
762 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
763 if (total) {
f67539c2 764 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[0]);
7c673cae
FG		 765 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
766 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
767
768 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
769 ILT_CLI_TM);
770
11fdf7f2 771 p_cli->vf_total_lines = curr_line - p_blk->start_line;
7c673cae
FG		 772 for (i = 1; i < p_mngr->vf_count; i++) {
773 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
774 ILT_CLI_TM);
775 }
7c673cae
FG		 776 }
777
f67539c2
TL		 778 /* SRC */
779 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]);
780 total = ecore_cxt_src_elements(p_mngr);
781
782 if (total) {
783 total_size = total * sizeof(struct src_ent);
784 elem_size = sizeof(struct src_ent);
785
786 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
787 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
788 total_size, elem_size);
789 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
790 ILT_CLI_SRC);
791 p_cli->pf_total_lines = curr_line - p_blk->start_line;
792 }
793
7c673cae
FG		 794 /* TSDM (SRQ CONTEXT) */
795 total = ecore_cxt_get_srq_count(p_hwfn);
796
797 if (total) {
f67539c2
TL		 798 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]);
799 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]);
7c673cae
FG		 800 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
801 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
802
803 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
804 ILT_CLI_TSDM);
805 p_cli->pf_total_lines = curr_line - p_blk->start_line;
806 }
807
808 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
809 RESC_NUM(p_hwfn, ECORE_ILT)) {
810 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
811 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
812 return ECORE_INVAL;
813 }
814
815 return ECORE_SUCCESS;
816}
817
818static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
819{
f67539c2 820 struct ecore_src_t2 *p_t2 = &p_hwfn->p_cxt_mngr->src_t2;
7c673cae
FG		 821 u32 i;
822
f67539c2 823 if (!p_t2 || !p_t2->dma_mem)
7c673cae
FG		 824 return;
825
f67539c2
TL		 826 for (i = 0; i < p_t2->num_pages; i++)
827 if (p_t2->dma_mem[i].virt_addr)
7c673cae 828 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
f67539c2
TL		 829 p_t2->dma_mem[i].virt_addr,
830 p_t2->dma_mem[i].phys_addr,
831 p_t2->dma_mem[i].size);
832
833 OSAL_FREE(p_hwfn->p_dev, p_t2->dma_mem);
834 p_t2->dma_mem = OSAL_NULL;
835}
836
837static enum _ecore_status_t
838ecore_cxt_t2_alloc_pages(struct ecore_hwfn *p_hwfn,
839 struct ecore_src_t2 *p_t2,
840 u32 total_size, u32 page_size)
841{
842 void **p_virt;
843 u32 size, i;
844
845 if (!p_t2 || !p_t2->dma_mem)
846 return ECORE_INVAL;
847
848 for (i = 0; i < p_t2->num_pages; i++) {
849 size = OSAL_MIN_T(u32, total_size, page_size);
850 p_virt = &p_t2->dma_mem[i].virt_addr;
851
852 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
853 &p_t2->dma_mem[i].phys_addr,
854 size);
855 if (!p_t2->dma_mem[i].virt_addr)
856 return ECORE_NOMEM;
857
858 OSAL_MEM_ZERO(*p_virt, size);
859 p_t2->dma_mem[i].size = size;
860 total_size -= size;
861 }
7c673cae 862
f67539c2 863 return ECORE_SUCCESS;
7c673cae
FG		 864}
865
866static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
867{
868 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
869 u32 conn_num, total_size, ent_per_page, psz, i;
f67539c2 870 struct phys_mem_desc *p_t2_last_page;
7c673cae
FG		 871 struct ecore_ilt_client_cfg *p_src;
872 struct ecore_src_iids src_iids;
f67539c2 873 struct ecore_src_t2 *p_t2;
7c673cae
FG		 874 enum _ecore_status_t rc;
875
876 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
877
878 /* if the SRC ILT client is inactive - there are no connection
879 * requiring the searcer, leave.
880 */
881 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
882 if (!p_src->active)
883 return ECORE_SUCCESS;
884
885 ecore_cxt_src_iids(p_mngr, &src_iids);
886 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
887 total_size = conn_num * sizeof(struct src_ent);
888
889 /* use the same page size as the SRC ILT client */
890 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
f67539c2
TL		 891 p_t2 = &p_mngr->src_t2;
892 p_t2->num_pages = DIV_ROUND_UP(total_size, psz);
7c673cae
FG		 893
894 /* allocate t2 */
f67539c2
TL		 895 p_t2->dma_mem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
896 p_t2->num_pages *
897 sizeof(struct phys_mem_desc));
898 if (!p_t2->dma_mem) {
11fdf7f2 899 DP_NOTICE(p_hwfn, false, "Failed to allocate t2 table\n");
7c673cae
FG		 900 rc = ECORE_NOMEM;
901 goto t2_fail;
902 }
903
f67539c2
TL		 904 rc = ecore_cxt_t2_alloc_pages(p_hwfn, p_t2, total_size, psz);
905 if (rc)
906 goto t2_fail;
7c673cae
FG		 907
908 /* Set the t2 pointers */
909
910 /* entries per page - must be a power of two */
911 ent_per_page = psz / sizeof(struct src_ent);
912
f67539c2 913 p_t2->first_free = (u64)p_t2->dma_mem[0].phys_addr;
7c673cae 914
f67539c2
TL		 915 p_t2_last_page = &p_t2->dma_mem[(conn_num - 1) / ent_per_page];
916 p_t2->last_free = (u64)p_t2_last_page->phys_addr +
917 ((conn_num - 1) & (ent_per_page - 1)) *
918 sizeof(struct src_ent);
7c673cae 919
f67539c2 920 for (i = 0; i < p_t2->num_pages; i++) {
7c673cae 921 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
f67539c2
TL		 922 struct src_ent *entries = p_t2->dma_mem[i].virt_addr;
923 u64 p_ent_phys = (u64)p_t2->dma_mem[i].phys_addr, val;
7c673cae
FG		 924 u32 j;
925
926 for (j = 0; j < ent_num - 1; j++) {
927 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
928 entries[j].next = OSAL_CPU_TO_BE64(val);
929 }
930
f67539c2
TL		 931 if (i < p_t2->num_pages - 1)
932 val = (u64)p_t2->dma_mem[i + 1].phys_addr;
7c673cae
FG		 933 else
934 val = 0;
935 entries[j].next = OSAL_CPU_TO_BE64(val);
936
937 conn_num -= ent_num;
938 }
939
940 return ECORE_SUCCESS;
941
942t2_fail:
943 ecore_cxt_src_t2_free(p_hwfn);
944 return rc;
945}
946
947#define for_each_ilt_valid_client(pos, clients) \
948 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
949 if (!clients[pos].active) { \
950 continue; \
951 } else \
952
953
954/* Total number of ILT lines used by this PF */
955static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
956{
957 u32 size = 0;
958 u32 i;
959
960 for_each_ilt_valid_client(i, ilt_clients)
961 size += (ilt_clients[i].last.val -
962 ilt_clients[i].first.val + 1);
963
964 return size;
965}
966
967static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
968{
969 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
970 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
971 u32 ilt_size, i;
972
11fdf7f2
TL		 973 if (p_mngr->ilt_shadow == OSAL_NULL)
974 return;
975
7c673cae
FG		 976 ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
977
978 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
f67539c2 979 struct phys_mem_desc *p_dma = &p_mngr->ilt_shadow[i];
7c673cae 980
f67539c2 981 if (p_dma->virt_addr)
7c673cae
FG		 982 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
983 p_dma->p_virt,
f67539c2
TL		 984 p_dma->phys_addr, p_dma->size);
985 p_dma->virt_addr = OSAL_NULL;
7c673cae
FG		 986 }
987 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
11fdf7f2 988 p_mngr->ilt_shadow = OSAL_NULL;
7c673cae
FG		 989}
990
991static enum _ecore_status_t
992ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
993 struct ecore_ilt_cli_blk *p_blk,
994 enum ilt_clients ilt_client, u32 start_line_offset)
995{
f67539c2
TL		 996 struct phys_mem_desc *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
997 u32 lines, line, sz_left, lines_to_skip, first_skipped_line;
7c673cae
FG		 998
999 /* Special handling for RoCE that supports dynamic allocation */
1000 if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
1001 return ECORE_SUCCESS;
1002
7c673cae
FG		 1003 if (!p_blk->total_size)
1004 return ECORE_SUCCESS;
1005
1006 sz_left = p_blk->total_size;
f67539c2 1007 lines_to_skip = p_blk->dynamic_line_cnt;
7c673cae
FG		 1008 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
1009 line = p_blk->start_line + start_line_offset -
f67539c2
TL		 1010 p_hwfn->p_cxt_mngr->pf_start_line;
1011 first_skipped_line = line + p_blk->dynamic_line_offset;
7c673cae 1012
f67539c2 1013 while (lines) {
7c673cae
FG		 1014 dma_addr_t p_phys;
1015 void *p_virt;
1016 u32 size;
1017
f67539c2
TL		 1018 if (lines_to_skip && (line == first_skipped_line)) {
1019 line += lines_to_skip;
1020 continue;
1021 }
1022
7c673cae
FG		 1023 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
1024
1025/* @DPDK */
1026#define ILT_BLOCK_ALIGN_SIZE 0x1000
1027 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
1028 &p_phys, size,
1029 ILT_BLOCK_ALIGN_SIZE);
1030 if (!p_virt)
1031 return ECORE_NOMEM;
1032 OSAL_MEM_ZERO(p_virt, size);
1033
f67539c2
TL		 1034 ilt_shadow[line].phys_addr = p_phys;
1035 ilt_shadow[line].virt_addr = p_virt;
7c673cae
FG		 1036 ilt_shadow[line].size = size;
1037
1038 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1039 "ILT shadow: Line [%d] Physical 0x%lx"
1040 " Virtual %p Size %d\n",
1041 line, (unsigned long)p_phys, p_virt, size);
1042
1043 sz_left -= size;
1044 line++;
f67539c2 1045 lines--;
7c673cae
FG		 1046 }
1047
1048 return ECORE_SUCCESS;
1049}
1050
1051static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
1052{
1053 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1054 struct ecore_ilt_client_cfg *clients = p_mngr->clients;
1055 struct ecore_ilt_cli_blk *p_blk;
1056 u32 size, i, j, k;
1057 enum _ecore_status_t rc;
1058
1059 size = ecore_cxt_ilt_shadow_size(clients);
1060 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
f67539c2 1061 size * sizeof(struct phys_mem_desc));
7c673cae
FG		 1062
1063 if (!p_mngr->ilt_shadow) {
11fdf7f2 1064 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt shadow table\n");
7c673cae
FG		 1065 rc = ECORE_NOMEM;
1066 goto ilt_shadow_fail;
1067 }
1068
1069 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1070 "Allocated 0x%x bytes for ilt shadow\n",
f67539c2 1071 (u32)(size * sizeof(struct phys_mem_desc)));
7c673cae
FG		 1072
1073 for_each_ilt_valid_client(i, clients) {
1074 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1075 p_blk = &clients[i].pf_blks[j];
1076 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1077 if (rc != ECORE_SUCCESS)
1078 goto ilt_shadow_fail;
1079 }
1080 for (k = 0; k < p_mngr->vf_count; k++) {
1081 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1082 u32 lines = clients[i].vf_total_lines * k;
1083
1084 p_blk = &clients[i].vf_blks[j];
1085 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1086 i, lines);
1087 if (rc != ECORE_SUCCESS)
1088 goto ilt_shadow_fail;
1089 }
1090 }
1091 }
1092
1093 return ECORE_SUCCESS;
1094
1095ilt_shadow_fail:
1096 ecore_ilt_shadow_free(p_hwfn);
1097 return rc;
1098}
1099
1100static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1101{
f67539c2 1102 u32 type, vf, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
7c673cae 1103 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
7c673cae
FG		 1104
1105 for (type = 0; type < MAX_CONN_TYPES; type++) {
1106 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
11fdf7f2 1107 p_mngr->acquired[type].cid_map = OSAL_NULL;
7c673cae
FG		 1108 p_mngr->acquired[type].max_count = 0;
1109 p_mngr->acquired[type].start_cid = 0;
11fdf7f2 1110
f67539c2 1111 for (vf = 0; vf < max_num_vfs; vf++) {
11fdf7f2
TL		 1112 OSAL_FREE(p_hwfn->p_dev,
1113 p_mngr->acquired_vf[type][vf].cid_map);
1114 p_mngr->acquired_vf[type][vf].cid_map = OSAL_NULL;
1115 p_mngr->acquired_vf[type][vf].max_count = 0;
1116 p_mngr->acquired_vf[type][vf].start_cid = 0;
1117 }
7c673cae
FG		 1118 }
1119}
1120
11fdf7f2 1121static enum _ecore_status_t
f67539c2 1122__ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
11fdf7f2
TL		 1123 u32 cid_start, u32 cid_count,
1124 struct ecore_cid_acquired_map *p_map)
1125{
1126 u32 size;
1127
1128 if (!cid_count)
1129 return ECORE_SUCCESS;
1130
1131 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1132 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1133 if (p_map->cid_map == OSAL_NULL)
1134 return ECORE_NOMEM;
1135
1136 p_map->max_count = cid_count;
1137 p_map->start_cid = cid_start;
1138
1139 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1140 "Type %08x start: %08x count %08x\n",
1141 type, p_map->start_cid, p_map->max_count);
1142
1143 return ECORE_SUCCESS;
1144}
1145
f67539c2
TL		 1146static enum _ecore_status_t
1147ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type, u32 start_cid,
1148 u32 vf_start_cid)
7c673cae
FG		 1149{
1150 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
f67539c2
TL		 1151 u32 vf, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
1152 struct ecore_cid_acquired_map *p_map;
1153 struct ecore_conn_type_cfg *p_cfg;
1154 enum _ecore_status_t rc;
7c673cae 1155
f67539c2 1156 p_cfg = &p_mngr->conn_cfg[type];
7c673cae 1157
11fdf7f2
TL		 1158 /* Handle PF maps */
1159 p_map = &p_mngr->acquired[type];
f67539c2
TL		 1160 rc = __ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1161 p_cfg->cid_count, p_map);
1162 if (rc != ECORE_SUCCESS)
1163 return rc;
1164
1165 /* Handle VF maps */
1166 for (vf = 0; vf < max_num_vfs; vf++) {
1167 p_map = &p_mngr->acquired_vf[type][vf];
1168 rc = __ecore_cid_map_alloc_single(p_hwfn, type, vf_start_cid,
1169 p_cfg->cids_per_vf, p_map);
1170 if (rc != ECORE_SUCCESS)
1171 return rc;
1172 }
7c673cae 1173
f67539c2
TL		 1174 return ECORE_SUCCESS;
1175}
7c673cae 1176
f67539c2
TL		 1177static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1178{
1179 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1180 u32 start_cid = 0, vf_start_cid = 0;
1181 u32 type;
1182 enum _ecore_status_t rc;
1183
1184 for (type = 0; type < MAX_CONN_TYPES; type++) {
1185 rc = ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1186 vf_start_cid);
1187 if (rc != ECORE_SUCCESS)
1188 goto cid_map_fail;
1189
1190 start_cid += p_mngr->conn_cfg[type].cid_count;
1191 vf_start_cid += p_mngr->conn_cfg[type].cids_per_vf;
7c673cae
FG		 1192 }
1193
1194 return ECORE_SUCCESS;
1195
1196cid_map_fail:
1197 ecore_cid_map_free(p_hwfn);
f67539c2 1198 return rc;
7c673cae
FG		 1199}
1200
1201enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1202{
f67539c2 1203 struct ecore_cid_acquired_map *acquired_vf;
7c673cae
FG		 1204 struct ecore_ilt_client_cfg *clients;
1205 struct ecore_cxt_mngr *p_mngr;
f67539c2 1206 u32 i, max_num_vfs;
7c673cae
FG		 1207
1208 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1209 if (!p_mngr) {
11fdf7f2 1210 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_cxt_mngr'\n");
7c673cae
FG		 1211 return ECORE_NOMEM;
1212 }
1213
1214 /* Initialize ILT client registers */
1215 clients = p_mngr->clients;
1216 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1217 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1218 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1219
1220 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1221 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1222 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1223
1224 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1225 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1226 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1227
1228 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1229 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1230 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1231
1232 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1233 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1234 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1235
1236 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1237 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1238 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1239
11fdf7f2 1240 /* default ILT page size for all clients is 64K */
7c673cae
FG		 1241 for (i = 0; i < ILT_CLI_MAX; i++)
1242 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1243
1244 /* due to removal of ISCSI/FCoE files union type0_task_context
1245 * task_type_size will be 0. So hardcoded for now.
1246 */
1247 p_mngr->task_type_size[0] = 512; /* @DPDK */
1248 p_mngr->task_type_size[1] = 128; /* @DPDK */
1249
1250 if (p_hwfn->p_dev->p_iov_info)
1251 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1252
1253 /* Initialize the dynamic ILT allocation mutex */
11fdf7f2 1254#ifdef CONFIG_ECORE_LOCK_ALLOC
9f95a23c
TL		 1255 if (OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex)) {
1256 DP_NOTICE(p_hwfn, false, "Failed to alloc p_mngr->mutex\n");
1257 return ECORE_NOMEM;
1258 }
11fdf7f2 1259#endif
7c673cae
FG		 1260 OSAL_MUTEX_INIT(&p_mngr->mutex);
1261
f67539c2
TL		 1262 /* Set the cxt mangr pointer prior to further allocations */
1263 p_hwfn->p_cxt_mngr = p_mngr;
1264
1265 max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
1266 for (i = 0; i < MAX_CONN_TYPES; i++) {
1267 acquired_vf = OSAL_CALLOC(p_hwfn->p_dev, GFP_KERNEL,
1268 max_num_vfs, sizeof(*acquired_vf));
1269 if (!acquired_vf) {
1270 DP_NOTICE(p_hwfn, false,
1271 "Failed to allocate an array of `struct ecore_cid_acquired_map'\n");
1272 return ECORE_NOMEM;
1273 }
1274
1275 p_mngr->acquired_vf[i] = acquired_vf;
1276 }
1277
7c673cae
FG		 1278 return ECORE_SUCCESS;
1279}
1280
1281enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1282{
1283 enum _ecore_status_t rc;
1284
1285 /* Allocate the ILT shadow table */
1286 rc = ecore_ilt_shadow_alloc(p_hwfn);
1287 if (rc) {
11fdf7f2 1288 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt memory\n");
7c673cae
FG		 1289 goto tables_alloc_fail;
1290 }
1291
1292 /* Allocate the T2 table */
1293 rc = ecore_cxt_src_t2_alloc(p_hwfn);
1294 if (rc) {
11fdf7f2 1295 DP_NOTICE(p_hwfn, false, "Failed to allocate T2 memory\n");
7c673cae
FG		 1296 goto tables_alloc_fail;
1297 }
1298
1299 /* Allocate and initialize the acquired cids bitmaps */
1300 rc = ecore_cid_map_alloc(p_hwfn);
1301 if (rc) {
11fdf7f2 1302 DP_NOTICE(p_hwfn, false, "Failed to allocate cid maps\n");
7c673cae
FG		 1303 goto tables_alloc_fail;
1304 }
1305
1306 return ECORE_SUCCESS;
1307
1308tables_alloc_fail:
1309 ecore_cxt_mngr_free(p_hwfn);
1310 return rc;
1311}
1312
1313void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1314{
f67539c2
TL		 1315 u32 i;
1316
7c673cae
FG		 1317 if (!p_hwfn->p_cxt_mngr)
1318 return;
1319
1320 ecore_cid_map_free(p_hwfn);
1321 ecore_cxt_src_t2_free(p_hwfn);
1322 ecore_ilt_shadow_free(p_hwfn);
11fdf7f2
TL		 1323#ifdef CONFIG_ECORE_LOCK_ALLOC
1324 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1325#endif
f67539c2
TL		 1326 for (i = 0; i < MAX_CONN_TYPES; i++)
1327 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr->acquired_vf[i]);
7c673cae 1328 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
f67539c2
TL		 1329
1330 p_hwfn->p_cxt_mngr = OSAL_NULL;
7c673cae
FG		 1331}
1332
1333void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1334{
1335 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
f67539c2 1336 u32 len, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
11fdf7f2
TL		 1337 struct ecore_cid_acquired_map *p_map;
1338 struct ecore_conn_type_cfg *p_cfg;
7c673cae
FG		 1339 int type;
1340
1341 /* Reset acquired cids */
1342 for (type = 0; type < MAX_CONN_TYPES; type++) {
11fdf7f2
TL		 1343 u32 vf;
1344
1345 p_cfg = &p_mngr->conn_cfg[type];
1346 if (p_cfg->cid_count) {
1347 p_map = &p_mngr->acquired[type];
1348 len = DIV_ROUND_UP(p_map->max_count,
1349 BITS_PER_MAP_WORD) *
1350 MAP_WORD_SIZE;
1351 OSAL_MEM_ZERO(p_map->cid_map, len);
1352 }
7c673cae 1353
11fdf7f2 1354 if (!p_cfg->cids_per_vf)
7c673cae
FG		 1355 continue;
1356
f67539c2 1357 for (vf = 0; vf < max_num_vfs; vf++) {
11fdf7f2
TL		 1358 p_map = &p_mngr->acquired_vf[type][vf];
1359 len = DIV_ROUND_UP(p_map->max_count,
1360 BITS_PER_MAP_WORD) *
1361 MAP_WORD_SIZE;
1362 OSAL_MEM_ZERO(p_map->cid_map, len);
1363 }
7c673cae
FG		 1364 }
1365}
1366
1367/* HW initialization helper (per Block, per phase) */
1368
1369/* CDU Common */
1370#define CDUC_CXT_SIZE_SHIFT \
1371 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1372
1373#define CDUC_CXT_SIZE_MASK \
1374 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1375
1376#define CDUC_BLOCK_WASTE_SHIFT \
1377 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1378
1379#define CDUC_BLOCK_WASTE_MASK \
1380 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1381
1382#define CDUC_NCIB_SHIFT \
1383 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1384
1385#define CDUC_NCIB_MASK \
1386 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1387
1388#define CDUT_TYPE0_CXT_SIZE_SHIFT \
1389 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1390
1391#define CDUT_TYPE0_CXT_SIZE_MASK \
1392 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1393 CDUT_TYPE0_CXT_SIZE_SHIFT)
1394
1395#define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1396 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1397
1398#define CDUT_TYPE0_BLOCK_WASTE_MASK \
1399 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1400 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1401
1402#define CDUT_TYPE0_NCIB_SHIFT \
1403 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1404
1405#define CDUT_TYPE0_NCIB_MASK \
1406 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1407 CDUT_TYPE0_NCIB_SHIFT)
1408
1409#define CDUT_TYPE1_CXT_SIZE_SHIFT \
1410 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1411
1412#define CDUT_TYPE1_CXT_SIZE_MASK \
1413 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1414 CDUT_TYPE1_CXT_SIZE_SHIFT)
1415
1416#define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1417 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1418
1419#define CDUT_TYPE1_BLOCK_WASTE_MASK \
1420 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1421 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1422
1423#define CDUT_TYPE1_NCIB_SHIFT \
1424 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1425
1426#define CDUT_TYPE1_NCIB_MASK \
1427 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1428 CDUT_TYPE1_NCIB_SHIFT)
1429
1430static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1431{
1432 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1433
1434 /* CDUC - connection configuration */
1435 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1436 cxt_size = CONN_CXT_SIZE(p_hwfn);
1437 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1438 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1439
1440 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1441 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1442 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1443 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1444
1445 /* CDUT - type-0 tasks configuration */
1446 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1447 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1448 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1449 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1450
1451 /* cxt size and block-waste are multipes of 8 */
1452 cdu_params = 0;
1453 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1454 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1455 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1456 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1457
1458 /* CDUT - type-1 tasks configuration */
1459 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1460 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1461 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1462
1463 /* cxt size and block-waste are multipes of 8 */
1464 cdu_params = 0;
1465 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1466 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1467 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1468 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1469}
1470
1471/* CDU PF */
1472#define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1473#define CDU_SEG_REG_TYPE_MASK 0x1
1474#define CDU_SEG_REG_OFFSET_SHIFT 0
1475#define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1476
1477static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1478{
1479 struct ecore_ilt_client_cfg *p_cli;
1480 struct ecore_tid_seg *p_seg;
1481 u32 cdu_seg_params, offset;
1482 int i;
1483
1484 static const u32 rt_type_offset_arr[] = {
1485 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1486 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1487 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1488 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1489 };
1490
1491 static const u32 rt_type_offset_fl_arr[] = {
1492 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1493 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1494 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1495 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1496 };
1497
1498 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1499
1500 /* There are initializations only for CDUT during pf Phase */
1501 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1502 /* Segment 0 */
1503 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1504 if (!p_seg)
1505 continue;
1506
1507 /* Note: start_line is already adjusted for the CDU
1508 * segment register granularity, so we just need to
1509 * divide. Adjustment is implicit as we assume ILT
1510 * Page size is larger than 32K!
1511 */
1512 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1513 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1514 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1515
1516 cdu_seg_params = 0;
1517 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1518 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1519 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1520
1521 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1522 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1523 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1524
1525 cdu_seg_params = 0;
1526 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1527 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1528 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1529 }
1530}
1531
11fdf7f2
TL		 1532void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1533 bool is_pf_loading)
7c673cae
FG		 1534{
1535 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1536 struct ecore_qm_iids iids;
1537
1538 OSAL_MEM_ZERO(&iids, sizeof(iids));
1539 ecore_cxt_qm_iids(p_hwfn, &iids);
11fdf7f2
TL		 1540 ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1541 qm_info->max_phys_tcs_per_port,
1542 is_pf_loading,
7c673cae
FG		 1543 iids.cids, iids.vf_cids, iids.tids,
1544 qm_info->start_pq,
1545 qm_info->num_pqs - qm_info->num_vf_pqs,
1546 qm_info->num_vf_pqs,
1547 qm_info->start_vport,
1548 qm_info->num_vports, qm_info->pf_wfq,
f67539c2 1549 qm_info->pf_rl,
11fdf7f2 1550 p_hwfn->qm_info.qm_pq_params,
7c673cae
FG		 1551 p_hwfn->qm_info.qm_vport_params);
1552}
1553
1554/* CM PF */
11fdf7f2 1555static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
7c673cae 1556{
11fdf7f2
TL		 1557 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1558 ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
7c673cae
FG		 1559}
1560
1561/* DQ PF */
1562static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1563{
1564 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1565 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1566
1567 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1568 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1569
1570 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1571 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1572
1573 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1574 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1575
1576 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1577 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1578
1579 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1580 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1581
1582 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1583 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1584
1585 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1586 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1587
1588 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1589 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1590
1591 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1592 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1593
1594 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1595 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1596
1597 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1598 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1599
1600 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1601 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1602
1603 /* Connection types 6 & 7 are not in use, yet they must be configured
1604 * as the highest possible connection. Not configuring them means the
1605 * defaults will be used, and with a large number of cids a bug may
1606 * occur, if the defaults will be smaller than dq_pf_max_cid /
1607 * dq_vf_max_cid.
1608 */
1609 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1610 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1611
1612 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1613 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1614}
1615
1616static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1617{
1618 struct ecore_ilt_client_cfg *ilt_clients;
1619 int i;
1620
1621 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1622 for_each_ilt_valid_client(i, ilt_clients) {
1623 STORE_RT_REG(p_hwfn,
1624 ilt_clients[i].first.reg,
1625 ilt_clients[i].first.val);
1626 STORE_RT_REG(p_hwfn,
1627 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1628 STORE_RT_REG(p_hwfn,
1629 ilt_clients[i].p_size.reg,
1630 ilt_clients[i].p_size.val);
1631 }
1632}
1633
1634static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1635{
1636 struct ecore_ilt_client_cfg *p_cli;
1637 u32 blk_factor;
1638
1639 /* For simplicty we set the 'block' to be an ILT page */
1640 if (p_hwfn->p_dev->p_iov_info) {
1641 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1642
1643 STORE_RT_REG(p_hwfn,
1644 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1645 p_iov->first_vf_in_pf);
1646 STORE_RT_REG(p_hwfn,
1647 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1648 p_iov->first_vf_in_pf + p_iov->total_vfs);
1649 }
1650
1651 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1652 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1653 if (p_cli->active) {
1654 STORE_RT_REG(p_hwfn,
1655 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1656 blk_factor);
1657 STORE_RT_REG(p_hwfn,
1658 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1659 p_cli->pf_total_lines);
1660 STORE_RT_REG(p_hwfn,
1661 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1662 p_cli->vf_total_lines);
1663 }
1664
1665 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1666 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1667 if (p_cli->active) {
1668 STORE_RT_REG(p_hwfn,
1669 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1670 blk_factor);
1671 STORE_RT_REG(p_hwfn,
1672 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1673 p_cli->pf_total_lines);
1674 STORE_RT_REG(p_hwfn,
1675 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1676 p_cli->vf_total_lines);
1677 }
1678
1679 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1680 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1681 if (p_cli->active) {
1682 STORE_RT_REG(p_hwfn,
1683 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1684 STORE_RT_REG(p_hwfn,
1685 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1686 p_cli->pf_total_lines);
1687 STORE_RT_REG(p_hwfn,
1688 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1689 p_cli->vf_total_lines);
1690 }
1691}
1692
1693/* ILT (PSWRQ2) PF */
1694static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1695{
1696 struct ecore_ilt_client_cfg *clients;
1697 struct ecore_cxt_mngr *p_mngr;
f67539c2 1698 struct phys_mem_desc *p_shdw;
7c673cae
FG		 1699 u32 line, rt_offst, i;
1700
1701 ecore_ilt_bounds_init(p_hwfn);
1702 ecore_ilt_vf_bounds_init(p_hwfn);
1703
1704 p_mngr = p_hwfn->p_cxt_mngr;
1705 p_shdw = p_mngr->ilt_shadow;
1706 clients = p_hwfn->p_cxt_mngr->clients;
1707
1708 for_each_ilt_valid_client(i, clients) {
1709 /* Client's 1st val and RT array are absolute, ILT shadows'
1710 * lines are relative.
1711 */
1712 line = clients[i].first.val - p_mngr->pf_start_line;
1713 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1714 clients[i].first.val * ILT_ENTRY_IN_REGS;
1715
1716 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1717 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1718 u64 ilt_hw_entry = 0;
1719
1720 /** p_virt could be OSAL_NULL incase of dynamic
1721 * allocation
1722 */
f67539c2 1723 if (p_shdw[line].virt_addr != OSAL_NULL) {
7c673cae
FG		 1724 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1725 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
f67539c2 1726 (p_shdw[line].phys_addr >> 12));
7c673cae
FG		 1727
1728 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1729 "Setting RT[0x%08x] from"
1730 " ILT[0x%08x] [Client is %d] to"
1731 " Physical addr: 0x%lx\n",
1732 rt_offst, line, i,
1733 (unsigned long)(p_shdw[line].
f67539c2 1734 phys_addr >> 12));
7c673cae
FG		 1735 }
1736
1737 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1738 }
1739 }
1740}
1741
1742/* SRC (Searcher) PF */
1743static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1744{
1745 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1746 u32 rounded_conn_num, conn_num, conn_max;
1747 struct ecore_src_iids src_iids;
1748
1749 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1750 ecore_cxt_src_iids(p_mngr, &src_iids);
1751 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1752 if (!conn_num)
1753 return;
1754
1755 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1756 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1757
1758 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1759 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1760 OSAL_LOG2(rounded_conn_num));
1761
1762 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
f67539c2 1763 p_hwfn->p_cxt_mngr->src_t2.first_free);
7c673cae 1764 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
f67539c2 1765 p_hwfn->p_cxt_mngr->src_t2.last_free);
11fdf7f2
TL		 1766 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1767 "Configured SEARCHER for 0x%08x connections\n",
1768 conn_num);
7c673cae
FG		 1769}
1770
1771/* Timers PF */
1772#define TM_CFG_NUM_IDS_SHIFT 0
1773#define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1774#define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1775#define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1776#define TM_CFG_PARENT_PF_SHIFT 25
1777#define TM_CFG_PARENT_PF_MASK 0x7ULL
1778
1779#define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1780#define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1781
1782#define TM_CFG_TID_OFFSET_SHIFT 30
1783#define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1784#define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1785#define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1786
1787static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1788{
1789 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1790 u32 active_seg_mask = 0, tm_offset, rt_reg;
1791 struct ecore_tm_iids tm_iids;
1792 u64 cfg_word;
1793 u8 i;
1794
1795 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
f67539c2 1796 ecore_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
7c673cae
FG		 1797
1798 /* @@@TBD No pre-scan for now */
1799
7c673cae
FG		 1800 cfg_word = 0;
1801 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
7c673cae 1802 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
f67539c2 1803 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
7c673cae
FG		 1804 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1805
f67539c2
TL		 1806 /* Note: We assume consecutive VFs for a PF */
1807 for (i = 0; i < p_mngr->vf_count; i++) {
7c673cae
FG		 1808 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1809 (sizeof(cfg_word) / sizeof(u32)) *
1810 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1811 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1812 }
1813
1814 cfg_word = 0;
1815 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1816 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1817 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1818 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1819
1820 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1821 (sizeof(cfg_word) / sizeof(u32)) *
1822 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1823 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1824
f67539c2 1825 /* enable scan */
7c673cae
FG		 1826 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1827 tm_iids.pf_cids ? 0x1 : 0x0);
1828
1829 /* @@@TBD how to enable the scan for the VFs */
1830
1831 tm_offset = tm_iids.per_vf_cids;
1832
1833 /* Note: We assume consecutive VFs for a PF */
1834 for (i = 0; i < p_mngr->vf_count; i++) {
1835 cfg_word = 0;
1836 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1837 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1838 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1839 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1840 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1841
1842 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1843 (sizeof(cfg_word) / sizeof(u32)) *
1844 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1845
1846 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1847 }
1848
1849 tm_offset = tm_iids.pf_cids;
1850 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1851 cfg_word = 0;
1852 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1853 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1854 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1855 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1856 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1857
1858 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1859 (sizeof(cfg_word) / sizeof(u32)) *
1860 (NUM_OF_VFS(p_hwfn->p_dev) +
1861 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1862
1863 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1864 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1865
1866 tm_offset += tm_iids.pf_tids[i];
1867 }
1868
1869 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1870
1871 /* @@@TBD how to enable the scan for the VFs */
1872}
1873
1874static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1875{
1876 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
11fdf7f2 1877 struct ecore_conn_type_cfg *p_fcoe;
7c673cae
FG		 1878 struct ecore_tid_seg *p_tid;
1879
11fdf7f2
TL		 1880 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1881
7c673cae
FG		 1882 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1883 if (!p_fcoe->cid_count)
1884 return;
1885
1886 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1887 STORE_RT_REG_AGG(p_hwfn,
1888 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1889 p_tid->count);
1890}
1891
1892void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1893{
1894 /* CDU configuration */
1895 ecore_cdu_init_common(p_hwfn);
1896}
1897
11fdf7f2 1898void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
7c673cae 1899{
11fdf7f2 1900 ecore_qm_init_pf(p_hwfn, p_ptt, true);
7c673cae
FG		 1901 ecore_cm_init_pf(p_hwfn);
1902 ecore_dq_init_pf(p_hwfn);
1903 ecore_cdu_init_pf(p_hwfn);
1904 ecore_ilt_init_pf(p_hwfn);
1905 ecore_src_init_pf(p_hwfn);
1906 ecore_tm_init_pf(p_hwfn);
1907 ecore_prs_init_pf(p_hwfn);
1908}
1909
11fdf7f2
TL		 1910enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1911 enum protocol_type type,
1912 u32 *p_cid, u8 vfid)
7c673cae 1913{
f67539c2 1914 u32 rel_cid, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
7c673cae 1915 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
11fdf7f2 1916 struct ecore_cid_acquired_map *p_map;
7c673cae 1917
11fdf7f2 1918 if (type >= MAX_CONN_TYPES) {
7c673cae
FG		 1919 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1920 return ECORE_INVAL;
1921 }
1922
f67539c2 1923 if (vfid >= max_num_vfs && vfid != ECORE_CXT_PF_CID) {
11fdf7f2
TL		 1924 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1925 return ECORE_INVAL;
1926 }
1927
1928 /* Determine the right map to take this CID from */
1929 if (vfid == ECORE_CXT_PF_CID)
1930 p_map = &p_mngr->acquired[type];
1931 else
1932 p_map = &p_mngr->acquired_vf[type][vfid];
1933
1934 if (p_map->cid_map == OSAL_NULL) {
1935 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1936 return ECORE_INVAL;
1937 }
1938
1939 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1940 p_map->max_count);
7c673cae 1941
11fdf7f2 1942 if (rel_cid >= p_map->max_count) {
7c673cae
FG		 1943 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1944 type);
1945 return ECORE_NORESOURCES;
1946 }
1947
11fdf7f2
TL		 1948 OSAL_SET_BIT(rel_cid, p_map->cid_map);
1949
1950 *p_cid = rel_cid + p_map->start_cid;
7c673cae 1951
11fdf7f2
TL		 1952 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1953 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1954 *p_cid, rel_cid, vfid, type);
7c673cae
FG		 1955
1956 return ECORE_SUCCESS;
1957}
1958
11fdf7f2
TL		 1959enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1960 enum protocol_type type,
1961 u32 *p_cid)
1962{
1963 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1964}
1965
7c673cae 1966static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
11fdf7f2
TL		 1967 u32 cid, u8 vfid,
1968 enum protocol_type *p_type,
1969 struct ecore_cid_acquired_map **pp_map)
7c673cae
FG		 1970{
1971 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
7c673cae
FG		 1972 u32 rel_cid;
1973
1974 /* Iterate over protocols and find matching cid range */
11fdf7f2
TL		 1975 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1976 if (vfid == ECORE_CXT_PF_CID)
1977 *pp_map = &p_mngr->acquired[*p_type];
1978 else
1979 *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
7c673cae 1980
11fdf7f2 1981 if (!((*pp_map)->cid_map))
7c673cae 1982 continue;
11fdf7f2
TL		 1983 if (cid >= (*pp_map)->start_cid &&
1984 cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
7c673cae
FG		 1985 break;
1986 }
1987 }
11fdf7f2
TL		 1988 if (*p_type == MAX_CONN_TYPES) {
1989 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1990 goto fail;
7c673cae 1991 }
11fdf7f2
TL		 1992
1993 rel_cid = cid - (*pp_map)->start_cid;
1994 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1995 DP_NOTICE(p_hwfn, true,
1996 "CID %d [vifd %02x] not acquired", cid, vfid);
1997 goto fail;
7c673cae 1998 }
11fdf7f2 1999
7c673cae 2000 return true;
11fdf7f2
TL		 2001fail:
2002 *p_type = MAX_CONN_TYPES;
2003 *pp_map = OSAL_NULL;
2004 return false;
7c673cae
FG		 2005}
2006
11fdf7f2 2007void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
7c673cae 2008{
f67539c2 2009 u32 rel_cid, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
11fdf7f2 2010 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
7c673cae
FG		 2011 enum protocol_type type;
2012 bool b_acquired;
7c673cae 2013
f67539c2 2014 if (vfid != ECORE_CXT_PF_CID && vfid > max_num_vfs) {
11fdf7f2
TL		 2015 DP_NOTICE(p_hwfn, true,
2016 "Trying to return incorrect CID belonging to VF %02x\n",
2017 vfid);
2018 return;
2019 }
2020
7c673cae 2021 /* Test acquired and find matching per-protocol map */
11fdf7f2
TL		 2022 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
2023 &type, &p_map);
7c673cae
FG		 2024
2025 if (!b_acquired)
2026 return;
2027
11fdf7f2
TL		 2028 rel_cid = cid - p_map->start_cid;
2029 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
2030
2031 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
2032 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
2033 cid, rel_cid, vfid, type);
2034}
2035
2036void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
2037{
2038 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
7c673cae
FG		 2039}
2040
2041enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
2042 struct ecore_cxt_info *p_info)
2043{
2044 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
11fdf7f2 2045 struct ecore_cid_acquired_map *p_map = OSAL_NULL;
7c673cae
FG		 2046 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
2047 enum protocol_type type;
2048 bool b_acquired;
2049
2050 /* Test acquired and find matching per-protocol map */
11fdf7f2
TL		 2051 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
2052 ECORE_CXT_PF_CID,
2053 &type, &p_map);
7c673cae
FG		 2054
2055 if (!b_acquired)
2056 return ECORE_INVAL;
2057
2058 /* set the protocl type */
2059 p_info->type = type;
2060
2061 /* compute context virtual pointer */
2062 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
2063
2064 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
2065 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
2066 line = p_info->iid / cxts_per_p;
2067
2068 /* Make sure context is allocated (dynamic allocation) */
f67539c2 2069 if (!p_mngr->ilt_shadow[line].virt_addr)
7c673cae
FG		 2070 return ECORE_INVAL;
2071
f67539c2 2072 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].virt_addr +
7c673cae
FG		 2073 p_info->iid % cxts_per_p * conn_cxt_size;
2074
2075 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
2076 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
2077 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
2078
2079 return ECORE_SUCCESS;
2080}
2081
7c673cae
FG		 2082enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
2083{
2084 /* Set the number of required CORE connections */
2085 u32 core_cids = 1; /* SPQ */
2086
2087 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
2088
2089 switch (p_hwfn->hw_info.personality) {
2090 case ECORE_PCI_ETH:
2091 {
11fdf7f2 2092 u32 count = 0;
7c673cae 2093
11fdf7f2
TL		 2094 struct ecore_eth_pf_params *p_params =
2095 &p_hwfn->pf_params.eth_pf_params;
7c673cae 2096
11fdf7f2
TL		 2097 if (!p_params->num_vf_cons)
2098 p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
2099 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2100 p_params->num_cons,
2101 p_params->num_vf_cons);
7c673cae 2102
11fdf7f2 2103 count = p_params->num_arfs_filters;
7c673cae 2104
11fdf7f2
TL		 2105 if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS,
2106 &p_hwfn->p_dev->mf_bits))
2107 p_hwfn->p_cxt_mngr->arfs_count = count;
7c673cae 2108
11fdf7f2
TL		 2109 break;
2110 }
7c673cae
FG		 2111 default:
2112 return ECORE_INVAL;
2113 }
2114
7c673cae
FG		 2115 return ECORE_SUCCESS;
2116}
2117
2118/* This function is very RoCE oriented, if another protocol in the future
2119 * will want this feature we'll need to modify the function to be more generic
2120 */
2121enum _ecore_status_t
2122ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2123 enum ecore_cxt_elem_type elem_type,
2124 u32 iid)
2125{
2126 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2127 struct ecore_ilt_client_cfg *p_cli;
2128 struct ecore_ilt_cli_blk *p_blk;
2129 struct ecore_ptt *p_ptt;
2130 dma_addr_t p_phys;
2131 u64 ilt_hw_entry;
2132 void *p_virt;
2133 enum _ecore_status_t rc = ECORE_SUCCESS;
2134
2135 switch (elem_type) {
2136 case ECORE_ELEM_CXT:
2137 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2138 elem_size = CONN_CXT_SIZE(p_hwfn);
2139 p_blk = &p_cli->pf_blks[CDUC_BLK];
2140 break;
2141 case ECORE_ELEM_SRQ:
2142 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2143 elem_size = SRQ_CXT_SIZE;
2144 p_blk = &p_cli->pf_blks[SRQ_BLK];
2145 break;
2146 case ECORE_ELEM_TASK:
2147 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2148 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2149 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2150 break;
2151 default:
2152 DP_NOTICE(p_hwfn, false,
2153 "ECORE_INVALID elem type = %d", elem_type);
2154 return ECORE_INVAL;
2155 }
2156
2157 /* Calculate line in ilt */
2158 hw_p_size = p_cli->p_size.val;
2159 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2160 line = p_blk->start_line + (iid / elems_per_p);
2161 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2162
2163 /* If line is already allocated, do nothing, otherwise allocate it and
2164 * write it to the PSWRQ2 registers.
2165 * This section can be run in parallel from different contexts and thus
2166 * a mutex protection is needed.
2167 */
2168
2169 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2170
f67539c2 2171 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr)
7c673cae
FG		 2172 goto out0;
2173
2174 p_ptt = ecore_ptt_acquire(p_hwfn);
2175 if (!p_ptt) {
2176 DP_NOTICE(p_hwfn, false,
2177 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2178 rc = ECORE_TIMEOUT;
2179 goto out0;
2180 }
2181
2182 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2183 &p_phys,
2184 p_blk->real_size_in_page);
2185 if (!p_virt) {
2186 rc = ECORE_NOMEM;
2187 goto out1;
2188 }
2189 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2190
f67539c2
TL		 2191 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt;
2192 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys;
7c673cae
FG		 2193 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2194 p_blk->real_size_in_page;
2195
2196 /* compute absolute offset */
2197 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2198 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2199
2200 ilt_hw_entry = 0;
2201 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2202 SET_FIELD(ilt_hw_entry,
2203 ILT_ENTRY_PHY_ADDR,
f67539c2 2204 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr >> 12));
7c673cae
FG		 2205
2206/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2207
2208 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2209 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
9f95a23c 2210 OSAL_NULL /* default parameters */);
7c673cae 2211
7c673cae
FG		 2212out1:
2213 ecore_ptt_release(p_hwfn, p_ptt);
2214out0:
2215 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2216
2217 return rc;
2218}
2219
2220/* This function is very RoCE oriented, if another protocol in the future
2221 * will want this feature we'll need to modify the function to be more generic
2222 */
2223static enum _ecore_status_t
2224ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2225 enum ecore_cxt_elem_type elem_type,
2226 u32 start_iid, u32 count)
2227{
2228 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2229 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2230 struct ecore_ilt_client_cfg *p_cli;
2231 struct ecore_ilt_cli_blk *p_blk;
2232 u32 end_iid = start_iid + count;
2233 struct ecore_ptt *p_ptt;
2234 u64 ilt_hw_entry = 0;
2235 u32 i;
2236
2237 switch (elem_type) {
2238 case ECORE_ELEM_CXT:
2239 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2240 elem_size = CONN_CXT_SIZE(p_hwfn);
2241 p_blk = &p_cli->pf_blks[CDUC_BLK];
2242 break;
2243 case ECORE_ELEM_SRQ:
2244 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2245 elem_size = SRQ_CXT_SIZE;
2246 p_blk = &p_cli->pf_blks[SRQ_BLK];
2247 break;
2248 case ECORE_ELEM_TASK:
2249 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2250 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2251 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2252 break;
2253 default:
2254 DP_NOTICE(p_hwfn, false,
2255 "ECORE_INVALID elem type = %d", elem_type);
2256 return ECORE_INVAL;
2257 }
2258
2259 /* Calculate line in ilt */
2260 hw_p_size = p_cli->p_size.val;
2261 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2262 start_line = p_blk->start_line + (start_iid / elems_per_p);
2263 end_line = p_blk->start_line + (end_iid / elems_per_p);
2264 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2265 end_line--;
2266
2267 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2268 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2269
2270 p_ptt = ecore_ptt_acquire(p_hwfn);
2271 if (!p_ptt) {
2272 DP_NOTICE(p_hwfn, false,
2273 "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2274 return ECORE_TIMEOUT;
2275 }
2276
2277 for (i = shadow_start_line; i < shadow_end_line; i++) {
f67539c2 2278 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr)
7c673cae
FG		 2279 continue;
2280
2281 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
f67539c2
TL		 2282 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr,
2283 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr,
2284 p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
7c673cae 2285
f67539c2
TL		 2286 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr = OSAL_NULL;
2287 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr = 0;
7c673cae
FG		 2288 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2289
2290 /* compute absolute offset */
2291 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2292 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2293 ILT_ENTRY_IN_REGS);
2294
2295 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2296 * wide-bus.
2297 */
2298 ecore_dmae_host2grc(p_hwfn, p_ptt,
2299 (u64)(osal_uintptr_t)&ilt_hw_entry,
2300 reg_offset,
2301 sizeof(ilt_hw_entry) / sizeof(u32),
9f95a23c 2302 OSAL_NULL /* default parameters */);
7c673cae
FG		 2303 }
2304
2305 ecore_ptt_release(p_hwfn, p_ptt);
2306
2307 return ECORE_SUCCESS;
2308}
Ceph