]>
Commit | Line | Data |
---|---|---|
11fdf7f2 TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright (c) 2016 - 2018 Cavium Inc. | |
7c673cae | 3 | * All rights reserved. |
11fdf7f2 | 4 | * www.cavium.com |
7c673cae FG |
5 | */ |
6 | ||
7 | #ifndef __ECORE_HSI_DEBUG_TOOLS__ | |
8 | #define __ECORE_HSI_DEBUG_TOOLS__ | |
9 | /****************************************/ | |
10 | /* Debug Tools HSI constants and macros */ | |
11 | /****************************************/ | |
12 | ||
13 | ||
14 | enum block_addr { | |
15 | GRCBASE_GRC = 0x50000, | |
16 | GRCBASE_MISCS = 0x9000, | |
17 | GRCBASE_MISC = 0x8000, | |
18 | GRCBASE_DBU = 0xa000, | |
19 | GRCBASE_PGLUE_B = 0x2a8000, | |
20 | GRCBASE_CNIG = 0x218000, | |
21 | GRCBASE_CPMU = 0x30000, | |
22 | GRCBASE_NCSI = 0x40000, | |
23 | GRCBASE_OPTE = 0x53000, | |
24 | GRCBASE_BMB = 0x540000, | |
25 | GRCBASE_PCIE = 0x54000, | |
26 | GRCBASE_MCP = 0xe00000, | |
27 | GRCBASE_MCP2 = 0x52000, | |
28 | GRCBASE_PSWHST = 0x2a0000, | |
29 | GRCBASE_PSWHST2 = 0x29e000, | |
30 | GRCBASE_PSWRD = 0x29c000, | |
31 | GRCBASE_PSWRD2 = 0x29d000, | |
32 | GRCBASE_PSWWR = 0x29a000, | |
33 | GRCBASE_PSWWR2 = 0x29b000, | |
34 | GRCBASE_PSWRQ = 0x280000, | |
35 | GRCBASE_PSWRQ2 = 0x240000, | |
36 | GRCBASE_PGLCS = 0x0, | |
37 | GRCBASE_DMAE = 0xc000, | |
38 | GRCBASE_PTU = 0x560000, | |
39 | GRCBASE_TCM = 0x1180000, | |
40 | GRCBASE_MCM = 0x1200000, | |
41 | GRCBASE_UCM = 0x1280000, | |
42 | GRCBASE_XCM = 0x1000000, | |
43 | GRCBASE_YCM = 0x1080000, | |
44 | GRCBASE_PCM = 0x1100000, | |
45 | GRCBASE_QM = 0x2f0000, | |
46 | GRCBASE_TM = 0x2c0000, | |
47 | GRCBASE_DORQ = 0x100000, | |
48 | GRCBASE_BRB = 0x340000, | |
49 | GRCBASE_SRC = 0x238000, | |
50 | GRCBASE_PRS = 0x1f0000, | |
51 | GRCBASE_TSDM = 0xfb0000, | |
52 | GRCBASE_MSDM = 0xfc0000, | |
53 | GRCBASE_USDM = 0xfd0000, | |
54 | GRCBASE_XSDM = 0xf80000, | |
55 | GRCBASE_YSDM = 0xf90000, | |
56 | GRCBASE_PSDM = 0xfa0000, | |
57 | GRCBASE_TSEM = 0x1700000, | |
58 | GRCBASE_MSEM = 0x1800000, | |
59 | GRCBASE_USEM = 0x1900000, | |
60 | GRCBASE_XSEM = 0x1400000, | |
61 | GRCBASE_YSEM = 0x1500000, | |
62 | GRCBASE_PSEM = 0x1600000, | |
63 | GRCBASE_RSS = 0x238800, | |
64 | GRCBASE_TMLD = 0x4d0000, | |
65 | GRCBASE_MULD = 0x4e0000, | |
66 | GRCBASE_YULD = 0x4c8000, | |
67 | GRCBASE_XYLD = 0x4c0000, | |
11fdf7f2 TL |
68 | GRCBASE_PTLD = 0x590000, |
69 | GRCBASE_YPLD = 0x5b0000, | |
7c673cae FG |
70 | GRCBASE_PRM = 0x230000, |
71 | GRCBASE_PBF_PB1 = 0xda0000, | |
72 | GRCBASE_PBF_PB2 = 0xda4000, | |
73 | GRCBASE_RPB = 0x23c000, | |
74 | GRCBASE_BTB = 0xdb0000, | |
75 | GRCBASE_PBF = 0xd80000, | |
76 | GRCBASE_RDIF = 0x300000, | |
77 | GRCBASE_TDIF = 0x310000, | |
78 | GRCBASE_CDU = 0x580000, | |
79 | GRCBASE_CCFC = 0x2e0000, | |
80 | GRCBASE_TCFC = 0x2d0000, | |
81 | GRCBASE_IGU = 0x180000, | |
82 | GRCBASE_CAU = 0x1c0000, | |
11fdf7f2 TL |
83 | GRCBASE_RGFS = 0xf00000, |
84 | GRCBASE_RGSRC = 0x320000, | |
85 | GRCBASE_TGFS = 0xd00000, | |
86 | GRCBASE_TGSRC = 0x322000, | |
7c673cae FG |
87 | GRCBASE_UMAC = 0x51000, |
88 | GRCBASE_XMAC = 0x210000, | |
89 | GRCBASE_DBG = 0x10000, | |
90 | GRCBASE_NIG = 0x500000, | |
91 | GRCBASE_WOL = 0x600000, | |
92 | GRCBASE_BMBN = 0x610000, | |
93 | GRCBASE_IPC = 0x20000, | |
94 | GRCBASE_NWM = 0x800000, | |
95 | GRCBASE_NWS = 0x700000, | |
96 | GRCBASE_MS = 0x6a0000, | |
97 | GRCBASE_PHY_PCIE = 0x620000, | |
98 | GRCBASE_LED = 0x6b8000, | |
11fdf7f2 | 99 | GRCBASE_AVS_WRAP = 0x6b0000, |
7c673cae FG |
100 | GRCBASE_MISC_AEU = 0x8000, |
101 | GRCBASE_BAR0_MAP = 0x1c00000, | |
102 | MAX_BLOCK_ADDR | |
103 | }; | |
104 | ||
105 | ||
106 | enum block_id { | |
107 | BLOCK_GRC, | |
108 | BLOCK_MISCS, | |
109 | BLOCK_MISC, | |
110 | BLOCK_DBU, | |
111 | BLOCK_PGLUE_B, | |
112 | BLOCK_CNIG, | |
113 | BLOCK_CPMU, | |
114 | BLOCK_NCSI, | |
115 | BLOCK_OPTE, | |
116 | BLOCK_BMB, | |
117 | BLOCK_PCIE, | |
118 | BLOCK_MCP, | |
119 | BLOCK_MCP2, | |
120 | BLOCK_PSWHST, | |
121 | BLOCK_PSWHST2, | |
122 | BLOCK_PSWRD, | |
123 | BLOCK_PSWRD2, | |
124 | BLOCK_PSWWR, | |
125 | BLOCK_PSWWR2, | |
126 | BLOCK_PSWRQ, | |
127 | BLOCK_PSWRQ2, | |
128 | BLOCK_PGLCS, | |
129 | BLOCK_DMAE, | |
130 | BLOCK_PTU, | |
131 | BLOCK_TCM, | |
132 | BLOCK_MCM, | |
133 | BLOCK_UCM, | |
134 | BLOCK_XCM, | |
135 | BLOCK_YCM, | |
136 | BLOCK_PCM, | |
137 | BLOCK_QM, | |
138 | BLOCK_TM, | |
139 | BLOCK_DORQ, | |
140 | BLOCK_BRB, | |
141 | BLOCK_SRC, | |
142 | BLOCK_PRS, | |
143 | BLOCK_TSDM, | |
144 | BLOCK_MSDM, | |
145 | BLOCK_USDM, | |
146 | BLOCK_XSDM, | |
147 | BLOCK_YSDM, | |
148 | BLOCK_PSDM, | |
149 | BLOCK_TSEM, | |
150 | BLOCK_MSEM, | |
151 | BLOCK_USEM, | |
152 | BLOCK_XSEM, | |
153 | BLOCK_YSEM, | |
154 | BLOCK_PSEM, | |
155 | BLOCK_RSS, | |
156 | BLOCK_TMLD, | |
157 | BLOCK_MULD, | |
158 | BLOCK_YULD, | |
159 | BLOCK_XYLD, | |
11fdf7f2 TL |
160 | BLOCK_PTLD, |
161 | BLOCK_YPLD, | |
7c673cae FG |
162 | BLOCK_PRM, |
163 | BLOCK_PBF_PB1, | |
164 | BLOCK_PBF_PB2, | |
165 | BLOCK_RPB, | |
166 | BLOCK_BTB, | |
167 | BLOCK_PBF, | |
168 | BLOCK_RDIF, | |
169 | BLOCK_TDIF, | |
170 | BLOCK_CDU, | |
171 | BLOCK_CCFC, | |
172 | BLOCK_TCFC, | |
173 | BLOCK_IGU, | |
174 | BLOCK_CAU, | |
11fdf7f2 TL |
175 | BLOCK_RGFS, |
176 | BLOCK_RGSRC, | |
177 | BLOCK_TGFS, | |
178 | BLOCK_TGSRC, | |
7c673cae FG |
179 | BLOCK_UMAC, |
180 | BLOCK_XMAC, | |
181 | BLOCK_DBG, | |
182 | BLOCK_NIG, | |
183 | BLOCK_WOL, | |
184 | BLOCK_BMBN, | |
185 | BLOCK_IPC, | |
186 | BLOCK_NWM, | |
187 | BLOCK_NWS, | |
188 | BLOCK_MS, | |
189 | BLOCK_PHY_PCIE, | |
190 | BLOCK_LED, | |
11fdf7f2 | 191 | BLOCK_AVS_WRAP, |
7c673cae FG |
192 | BLOCK_MISC_AEU, |
193 | BLOCK_BAR0_MAP, | |
194 | MAX_BLOCK_ID | |
195 | }; | |
196 | ||
197 | ||
198 | /* | |
199 | * binary debug buffer types | |
200 | */ | |
201 | enum bin_dbg_buffer_type { | |
202 | BIN_BUF_DBG_MODE_TREE /* init modes tree */, | |
203 | BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */, | |
204 | BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */, | |
205 | BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */, | |
206 | BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */, | |
207 | BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */, | |
208 | BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, | |
209 | BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */, | |
210 | BIN_BUF_DBG_ATTN_REGS /* Attention registers */, | |
211 | BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */, | |
212 | BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */, | |
11fdf7f2 TL |
213 | BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, |
214 | BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, | |
215 | BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, | |
216 | BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, | |
7c673cae FG |
217 | BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */, |
218 | MAX_BIN_DBG_BUFFER_TYPE | |
219 | }; | |
220 | ||
221 | ||
222 | /* | |
223 | * Attention bit mapping | |
224 | */ | |
225 | struct dbg_attn_bit_mapping { | |
11fdf7f2 | 226 | u16 data; |
7c673cae | 227 | /* The index of an attention in the blocks attentions list |
11fdf7f2 TL |
228 | * (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits |
229 | * (if is_unused_bit_cnt=1) | |
7c673cae FG |
230 | */ |
231 | #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF | |
232 | #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 | |
233 | /* if set, the val field indicates the number of consecutive unused attention | |
234 | * bits | |
235 | */ | |
236 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 | |
237 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 | |
238 | }; | |
239 | ||
240 | ||
241 | /* | |
242 | * Attention block per-type data | |
243 | */ | |
244 | struct dbg_attn_block_type_data { | |
245 | /* Offset of this block attention names in the debug attention name offsets | |
246 | * array | |
247 | */ | |
11fdf7f2 TL |
248 | u16 names_offset; |
249 | u16 reserved1; | |
7c673cae FG |
250 | u8 num_regs /* Number of attention registers in this block */; |
251 | u8 reserved2; | |
252 | /* Offset of this blocks attention registers in the attention registers array | |
253 | * (in dbg_attn_reg units) | |
254 | */ | |
11fdf7f2 | 255 | u16 regs_offset; |
7c673cae FG |
256 | }; |
257 | ||
258 | /* | |
259 | * Block attentions | |
260 | */ | |
261 | struct dbg_attn_block { | |
262 | /* attention block per-type data. Count must match the number of elements in | |
263 | * dbg_attn_type. | |
264 | */ | |
265 | struct dbg_attn_block_type_data per_type_data[2]; | |
266 | }; | |
267 | ||
268 | ||
269 | /* | |
270 | * Attention register result | |
271 | */ | |
272 | struct dbg_attn_reg_result { | |
11fdf7f2 | 273 | u32 data; |
7c673cae FG |
274 | /* STS attention register GRC address (in dwords) */ |
275 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF | |
276 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 | |
277 | /* Number of attention indexes in this register */ | |
11fdf7f2 TL |
278 | #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF |
279 | #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 | |
280 | /* The offset of this registers attentions within the blocks attentions list | |
281 | * (a value in the range 0..number of block attentions-1) | |
282 | */ | |
283 | u16 block_attn_offset; | |
284 | u16 reserved; | |
285 | u32 sts_val /* Value read from the STS attention register */; | |
286 | u32 mask_val /* Value read from the MASK attention register */; | |
7c673cae FG |
287 | }; |
288 | ||
289 | /* | |
290 | * Attention block result | |
291 | */ | |
292 | struct dbg_attn_block_result { | |
293 | u8 block_id /* Registers block ID */; | |
294 | u8 data; | |
295 | /* Value from dbg_attn_type enum */ | |
296 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 | |
297 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 | |
11fdf7f2 | 298 | /* Number of registers in block in which at least one attention bit is set */ |
7c673cae FG |
299 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F |
300 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 | |
301 | /* Offset of this registers block attention names in the attention name offsets | |
302 | * array | |
303 | */ | |
11fdf7f2 | 304 | u16 names_offset; |
7c673cae FG |
305 | /* result data for each register in the block in which at least one attention |
306 | * bit is set | |
307 | */ | |
308 | struct dbg_attn_reg_result reg_results[15]; | |
309 | }; | |
310 | ||
311 | ||
312 | ||
313 | /* | |
314 | * mode header | |
315 | */ | |
316 | struct dbg_mode_hdr { | |
11fdf7f2 | 317 | u16 data; |
7c673cae FG |
318 | /* indicates if a mode expression should be evaluated (0/1) */ |
319 | #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 | |
320 | #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 | |
321 | /* offset (in bytes) in modes expression buffer. valid only if eval_mode is | |
322 | * set. | |
323 | */ | |
324 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF | |
325 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 | |
326 | }; | |
327 | ||
328 | /* | |
329 | * Attention register | |
330 | */ | |
331 | struct dbg_attn_reg { | |
11fdf7f2 TL |
332 | /* The offset of this registers attentions within the blocks attentions list |
333 | * (a value in the range 0..number of block attentions-1) | |
7c673cae | 334 | */ |
11fdf7f2 TL |
335 | u16 block_attn_offset; |
336 | u32 data; | |
7c673cae FG |
337 | /* STS attention register GRC address (in dwords) */ |
338 | #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF | |
339 | #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 | |
11fdf7f2 TL |
340 | /* Number of attention in this register */ |
341 | #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF | |
342 | #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 | |
7c673cae | 343 | /* STS_CLR attention register GRC address (in dwords) */ |
11fdf7f2 TL |
344 | u32 sts_clr_address; |
345 | u32 mask_address /* MASK attention register GRC address (in dwords) */; | |
7c673cae FG |
346 | }; |
347 | ||
348 | ||
349 | ||
350 | /* | |
351 | * attention types | |
352 | */ | |
353 | enum dbg_attn_type { | |
354 | ATTN_TYPE_INTERRUPT, | |
355 | ATTN_TYPE_PARITY, | |
356 | MAX_DBG_ATTN_TYPE | |
357 | }; | |
358 | ||
359 | ||
11fdf7f2 TL |
360 | /* |
361 | * Debug Bus block data | |
362 | */ | |
363 | struct dbg_bus_block { | |
364 | /* Number of debug lines in this block (excluding signature & latency events) */ | |
365 | u8 num_of_lines; | |
366 | /* Indicates if this block has a latency events debug line (0/1). */ | |
367 | u8 has_latency_events; | |
368 | /* Offset of this blocks lines in the Debug Bus lines array. */ | |
369 | u16 lines_offset; | |
370 | }; | |
371 | ||
372 | ||
373 | /* | |
374 | * Debug Bus block user data | |
375 | */ | |
376 | struct dbg_bus_block_user_data { | |
377 | /* Number of debug lines in this block (excluding signature & latency events) */ | |
378 | u8 num_of_lines; | |
379 | /* Indicates if this block has a latency events debug line (0/1). */ | |
380 | u8 has_latency_events; | |
381 | /* Offset of this blocks lines in the debug bus line name offsets array. */ | |
382 | u16 names_offset; | |
383 | }; | |
384 | ||
385 | ||
386 | /* | |
387 | * Block Debug line data | |
388 | */ | |
389 | struct dbg_bus_line { | |
390 | u8 data; | |
391 | /* Number of groups in the line (0-3) */ | |
392 | #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF | |
393 | #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 | |
394 | /* Indicates if this is a 128b line (0) or a 256b line (1). */ | |
395 | #define DBG_BUS_LINE_IS_256B_MASK 0x1 | |
396 | #define DBG_BUS_LINE_IS_256B_SHIFT 4 | |
397 | #define DBG_BUS_LINE_RESERVED_MASK 0x7 | |
398 | #define DBG_BUS_LINE_RESERVED_SHIFT 5 | |
399 | /* Four 2-bit values, indicating the size of each group minus 1 (i.e. | |
400 | * value=0 means size=1, value=1 means size=2, etc), starting from lsb. | |
401 | * The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1). | |
402 | */ | |
403 | u8 group_sizes; | |
404 | }; | |
405 | ||
406 | ||
7c673cae FG |
407 | /* |
408 | * condition header for registers dump | |
409 | */ | |
410 | struct dbg_dump_cond_hdr { | |
411 | struct dbg_mode_hdr mode /* Mode header */; | |
412 | u8 block_id /* block ID */; | |
413 | u8 data_size /* size in dwords of the data following this header */; | |
414 | }; | |
415 | ||
416 | ||
417 | /* | |
418 | * memory data for registers dump | |
419 | */ | |
420 | struct dbg_dump_mem { | |
11fdf7f2 | 421 | u32 dword0; |
7c673cae FG |
422 | /* register address (in dwords) */ |
423 | #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF | |
424 | #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 | |
425 | #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ | |
426 | #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 | |
11fdf7f2 | 427 | u32 dword1; |
7c673cae FG |
428 | /* register size (in dwords) */ |
429 | #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF | |
430 | #define DBG_DUMP_MEM_LENGTH_SHIFT 0 | |
11fdf7f2 TL |
431 | /* indicates if the register is wide-bus */ |
432 | #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 | |
433 | #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 | |
434 | #define DBG_DUMP_MEM_RESERVED_MASK 0x7F | |
435 | #define DBG_DUMP_MEM_RESERVED_SHIFT 25 | |
7c673cae FG |
436 | }; |
437 | ||
438 | ||
439 | /* | |
440 | * register data for registers dump | |
441 | */ | |
442 | struct dbg_dump_reg { | |
11fdf7f2 | 443 | u32 data; |
7c673cae | 444 | /* register address (in dwords) */ |
11fdf7f2 TL |
445 | #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ |
446 | #define DBG_DUMP_REG_ADDRESS_SHIFT 0 | |
447 | /* indicates if the register is wide-bus */ | |
448 | #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 | |
449 | #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 | |
450 | #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ | |
451 | #define DBG_DUMP_REG_LENGTH_SHIFT 24 | |
7c673cae FG |
452 | }; |
453 | ||
454 | ||
455 | /* | |
456 | * split header for registers dump | |
457 | */ | |
458 | struct dbg_dump_split_hdr { | |
11fdf7f2 | 459 | u32 hdr; |
7c673cae FG |
460 | /* size in dwords of the data following this header */ |
461 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF | |
462 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 | |
463 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */ | |
464 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 | |
465 | }; | |
466 | ||
467 | ||
468 | /* | |
469 | * condition header for idle check | |
470 | */ | |
471 | struct dbg_idle_chk_cond_hdr { | |
472 | struct dbg_mode_hdr mode /* Mode header */; | |
11fdf7f2 | 473 | u16 data_size /* size in dwords of the data following this header */; |
7c673cae FG |
474 | }; |
475 | ||
476 | ||
477 | /* | |
478 | * Idle Check condition register | |
479 | */ | |
480 | struct dbg_idle_chk_cond_reg { | |
11fdf7f2 | 481 | u32 data; |
7c673cae | 482 | /* Register GRC address (in dwords) */ |
11fdf7f2 | 483 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF |
7c673cae | 484 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 |
11fdf7f2 TL |
485 | /* indicates if the register is wide-bus */ |
486 | #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 | |
487 | #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 | |
7c673cae FG |
488 | /* value from block_id enum */ |
489 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF | |
490 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 | |
11fdf7f2 | 491 | u16 num_entries /* number of registers entries to check */; |
7c673cae FG |
492 | u8 entry_size /* size of registers entry (in dwords) */; |
493 | u8 start_entry /* index of the first entry to check */; | |
494 | }; | |
495 | ||
496 | ||
497 | /* | |
498 | * Idle Check info register | |
499 | */ | |
500 | struct dbg_idle_chk_info_reg { | |
11fdf7f2 | 501 | u32 data; |
7c673cae | 502 | /* Register GRC address (in dwords) */ |
11fdf7f2 | 503 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF |
7c673cae | 504 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 |
11fdf7f2 TL |
505 | /* indicates if the register is wide-bus */ |
506 | #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 | |
507 | #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 | |
7c673cae FG |
508 | /* value from block_id enum */ |
509 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF | |
510 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 | |
11fdf7f2 | 511 | u16 size /* register size in dwords */; |
7c673cae FG |
512 | struct dbg_mode_hdr mode /* Mode header */; |
513 | }; | |
514 | ||
515 | ||
516 | /* | |
517 | * Idle Check register | |
518 | */ | |
519 | union dbg_idle_chk_reg { | |
520 | struct dbg_idle_chk_cond_reg cond_reg /* condition register */; | |
521 | struct dbg_idle_chk_info_reg info_reg /* info register */; | |
522 | }; | |
523 | ||
524 | ||
525 | /* | |
526 | * Idle Check result header | |
527 | */ | |
528 | struct dbg_idle_chk_result_hdr { | |
11fdf7f2 TL |
529 | u16 rule_id /* Failing rule index */; |
530 | u16 mem_entry_id /* Failing memory entry index */; | |
7c673cae FG |
531 | u8 num_dumped_cond_regs /* number of dumped condition registers */; |
532 | u8 num_dumped_info_regs /* number of dumped condition registers */; | |
533 | u8 severity /* from dbg_idle_chk_severity_types enum */; | |
534 | u8 reserved; | |
535 | }; | |
536 | ||
537 | ||
538 | /* | |
539 | * Idle Check result register header | |
540 | */ | |
541 | struct dbg_idle_chk_result_reg_hdr { | |
542 | u8 data; | |
543 | /* indicates if this register is a memory */ | |
544 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 | |
545 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 | |
546 | /* register index within the failing rule */ | |
547 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F | |
548 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 | |
549 | u8 start_entry /* index of the first checked entry */; | |
11fdf7f2 | 550 | u16 size /* register size in dwords */; |
7c673cae FG |
551 | }; |
552 | ||
553 | ||
554 | /* | |
555 | * Idle Check rule | |
556 | */ | |
557 | struct dbg_idle_chk_rule { | |
11fdf7f2 | 558 | u16 rule_id /* Idle Check rule ID */; |
7c673cae FG |
559 | u8 severity /* value from dbg_idle_chk_severity_types enum */; |
560 | u8 cond_id /* Condition ID */; | |
561 | u8 num_cond_regs /* number of condition registers */; | |
562 | u8 num_info_regs /* number of info registers */; | |
563 | u8 num_imms /* number of immediates in the condition */; | |
564 | u8 reserved1; | |
565 | /* offset of this rules registers in the idle check register array | |
566 | * (in dbg_idle_chk_reg units) | |
567 | */ | |
11fdf7f2 | 568 | u16 reg_offset; |
7c673cae FG |
569 | /* offset of this rules immediate values in the immediate values array |
570 | * (in dwords) | |
571 | */ | |
11fdf7f2 | 572 | u16 imm_offset; |
7c673cae FG |
573 | }; |
574 | ||
575 | ||
576 | /* | |
577 | * Idle Check rule parsing data | |
578 | */ | |
579 | struct dbg_idle_chk_rule_parsing_data { | |
11fdf7f2 | 580 | u32 data; |
7c673cae FG |
581 | /* indicates if this register has a FW message */ |
582 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 | |
583 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 | |
584 | /* Offset of this rules strings in the debug strings array (in bytes) */ | |
585 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF | |
586 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 | |
587 | }; | |
588 | ||
589 | ||
590 | /* | |
591 | * idle check severity types | |
592 | */ | |
593 | enum dbg_idle_chk_severity_types { | |
594 | /* idle check failure should cause an error */ | |
595 | IDLE_CHK_SEVERITY_ERROR, | |
596 | /* idle check failure should cause an error only if theres no traffic */ | |
597 | IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC, | |
598 | /* idle check failure should cause a warning */ | |
599 | IDLE_CHK_SEVERITY_WARNING, | |
600 | MAX_DBG_IDLE_CHK_SEVERITY_TYPES | |
601 | }; | |
602 | ||
603 | ||
604 | ||
605 | /* | |
606 | * Debug Bus block data | |
607 | */ | |
608 | struct dbg_bus_block_data { | |
11fdf7f2 TL |
609 | __le16 data; |
610 | /* 4-bit value: bit i set -> dword/qword i is enabled. */ | |
611 | #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF | |
612 | #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 | |
613 | /* Number of dwords/qwords to shift right the debug data (0-3) */ | |
614 | #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF | |
615 | #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 | |
616 | /* 4-bit value: bit i set -> dword/qword i is forced valid. */ | |
617 | #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF | |
618 | #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 | |
619 | /* 4-bit value: bit i set -> dword/qword i frame bit is forced. */ | |
620 | #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF | |
621 | #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 | |
7c673cae | 622 | u8 line_num /* Debug line number to select */; |
11fdf7f2 | 623 | u8 hw_id /* HW ID associated with the block */; |
7c673cae FG |
624 | }; |
625 | ||
626 | ||
627 | /* | |
628 | * Debug Bus Clients | |
629 | */ | |
630 | enum dbg_bus_clients { | |
631 | DBG_BUS_CLIENT_RBCN, | |
632 | DBG_BUS_CLIENT_RBCP, | |
633 | DBG_BUS_CLIENT_RBCR, | |
634 | DBG_BUS_CLIENT_RBCT, | |
635 | DBG_BUS_CLIENT_RBCU, | |
636 | DBG_BUS_CLIENT_RBCF, | |
637 | DBG_BUS_CLIENT_RBCX, | |
638 | DBG_BUS_CLIENT_RBCS, | |
639 | DBG_BUS_CLIENT_RBCH, | |
640 | DBG_BUS_CLIENT_RBCZ, | |
641 | DBG_BUS_CLIENT_OTHER_ENGINE, | |
642 | DBG_BUS_CLIENT_TIMESTAMP, | |
643 | DBG_BUS_CLIENT_CPU, | |
644 | DBG_BUS_CLIENT_RBCY, | |
645 | DBG_BUS_CLIENT_RBCQ, | |
646 | DBG_BUS_CLIENT_RBCM, | |
647 | DBG_BUS_CLIENT_RBCB, | |
648 | DBG_BUS_CLIENT_RBCW, | |
649 | DBG_BUS_CLIENT_RBCV, | |
650 | MAX_DBG_BUS_CLIENTS | |
651 | }; | |
652 | ||
653 | ||
654 | /* | |
655 | * Debug Bus constraint operation types | |
656 | */ | |
657 | enum dbg_bus_constraint_ops { | |
658 | DBG_BUS_CONSTRAINT_OP_EQ /* equal */, | |
659 | DBG_BUS_CONSTRAINT_OP_NE /* not equal */, | |
660 | DBG_BUS_CONSTRAINT_OP_LT /* less than */, | |
661 | DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */, | |
662 | DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */, | |
663 | DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */, | |
664 | DBG_BUS_CONSTRAINT_OP_GT /* greater than */, | |
665 | DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */, | |
666 | DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */, | |
667 | DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */, | |
668 | MAX_DBG_BUS_CONSTRAINT_OPS | |
669 | }; | |
670 | ||
671 | ||
11fdf7f2 TL |
672 | /* |
673 | * Debug Bus trigger state data | |
674 | */ | |
675 | struct dbg_bus_trigger_state_data { | |
676 | u8 data; | |
677 | /* 4-bit value: bit i set -> dword i of the trigger state block | |
678 | * (after right shift) is enabled. | |
679 | */ | |
680 | #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF | |
681 | #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 | |
682 | /* 4-bit value: bit i set -> dword i is compared by a constraint */ | |
683 | #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF | |
684 | #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 | |
685 | }; | |
686 | ||
7c673cae FG |
687 | /* |
688 | * Debug Bus memory address | |
689 | */ | |
690 | struct dbg_bus_mem_addr { | |
11fdf7f2 TL |
691 | u32 lo; |
692 | u32 hi; | |
7c673cae FG |
693 | }; |
694 | ||
695 | /* | |
696 | * Debug Bus PCI buffer data | |
697 | */ | |
698 | struct dbg_bus_pci_buf_data { | |
699 | struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; | |
700 | struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; | |
11fdf7f2 | 701 | u32 size /* PCI buffer size in bytes */; |
7c673cae FG |
702 | }; |
703 | ||
704 | /* | |
705 | * Debug Bus Storm EID range filter params | |
706 | */ | |
707 | struct dbg_bus_storm_eid_range_params { | |
708 | u8 min /* Minimal event ID to filter on */; | |
709 | u8 max /* Maximal event ID to filter on */; | |
710 | }; | |
711 | ||
712 | /* | |
713 | * Debug Bus Storm EID mask filter params | |
714 | */ | |
715 | struct dbg_bus_storm_eid_mask_params { | |
716 | u8 val /* Event ID value */; | |
717 | u8 mask /* Event ID mask. 1s in the mask = dont care bits. */; | |
718 | }; | |
719 | ||
720 | /* | |
721 | * Debug Bus Storm EID filter params | |
722 | */ | |
723 | union dbg_bus_storm_eid_params { | |
724 | /* EID range filter params */ | |
725 | struct dbg_bus_storm_eid_range_params range; | |
726 | /* EID mask filter params */ | |
727 | struct dbg_bus_storm_eid_mask_params mask; | |
728 | }; | |
729 | ||
730 | /* | |
731 | * Debug Bus Storm data | |
732 | */ | |
733 | struct dbg_bus_storm_data { | |
11fdf7f2 TL |
734 | u8 enabled /* indicates if the Storm is enabled for recording */; |
735 | u8 mode /* Storm debug mode, valid only if the Storm is enabled */; | |
7c673cae FG |
736 | u8 hw_id /* HW ID associated with the Storm */; |
737 | u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */; | |
738 | /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is | |
739 | * set, | |
740 | */ | |
741 | u8 eid_range_not_mask; | |
742 | u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; | |
743 | /* EID filter params to filter on. Valid only if eid_filter_en is set. */ | |
744 | union dbg_bus_storm_eid_params eid_filter_params; | |
11fdf7f2 | 745 | u32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; |
7c673cae FG |
746 | }; |
747 | ||
748 | /* | |
749 | * Debug Bus data | |
750 | */ | |
751 | struct dbg_bus_data { | |
11fdf7f2 | 752 | u32 app_version /* The tools version number of the application */; |
7c673cae FG |
753 | u8 state /* The current debug bus state */; |
754 | u8 hw_dwords /* HW dwords per cycle */; | |
11fdf7f2 TL |
755 | /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the |
756 | * HW ID of dword/qword i | |
757 | */ | |
758 | u16 hw_id_mask; | |
7c673cae FG |
759 | u8 num_enabled_blocks /* Number of blocks enabled for recording */; |
760 | u8 num_enabled_storms /* Number of Storms enabled for recording */; | |
761 | u8 target /* Output target */; | |
7c673cae FG |
762 | u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */; |
763 | u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */; | |
764 | /* Indicates if timestamp recording is enabled (0/1) */ | |
765 | u8 timestamp_input_en; | |
766 | u8 filter_en /* Indicates if the recording filter is enabled (0/1) */; | |
7c673cae FG |
767 | /* If true, the next added constraint belong to the filter. Otherwise, |
768 | * it belongs to the last added trigger state. Valid only if either filter or | |
769 | * triggers are enabled. | |
770 | */ | |
771 | u8 adding_filter; | |
772 | /* Indicates if the recording filter should be applied before the trigger. | |
773 | * Valid only if both filter and trigger are enabled (0/1) | |
774 | */ | |
775 | u8 filter_pre_trigger; | |
776 | /* Indicates if the recording filter should be applied after the trigger. | |
777 | * Valid only if both filter and trigger are enabled (0/1) | |
778 | */ | |
779 | u8 filter_post_trigger; | |
11fdf7f2 TL |
780 | u16 reserved; |
781 | /* Indicates if the recording trigger is enabled (0/1) */ | |
782 | u8 trigger_en; | |
783 | /* trigger states data */ | |
784 | struct dbg_bus_trigger_state_data trigger_states[3]; | |
785 | u8 next_trigger_state /* ID of next trigger state to be added */; | |
786 | /* ID of next filter/trigger constraint to be added */ | |
787 | u8 next_constraint_id; | |
7c673cae FG |
788 | /* If true, all inputs are associated with HW ID 0. Otherwise, each input is |
789 | * assigned a different HW ID (0/1) | |
790 | */ | |
791 | u8 unify_inputs; | |
792 | /* Indicates if the other engine sends it NW recording to this engine (0/1) */ | |
793 | u8 rcv_from_other_engine; | |
794 | /* Debug Bus PCI buffer data. Valid only when the target is | |
795 | * DBG_BUS_TARGET_ID_PCI. | |
796 | */ | |
797 | struct dbg_bus_pci_buf_data pci_buf; | |
7c673cae | 798 | /* Debug Bus data for each block */ |
11fdf7f2 | 799 | struct dbg_bus_block_data blocks[88]; |
7c673cae FG |
800 | /* Debug Bus data for each block */ |
801 | struct dbg_bus_storm_data storms[6]; | |
802 | }; | |
803 | ||
804 | ||
805 | /* | |
806 | * Debug bus filter types | |
807 | */ | |
808 | enum dbg_bus_filter_types { | |
809 | DBG_BUS_FILTER_TYPE_OFF /* filter always off */, | |
810 | DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */, | |
811 | DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */, | |
812 | DBG_BUS_FILTER_TYPE_ON /* filter always on */, | |
813 | MAX_DBG_BUS_FILTER_TYPES | |
814 | }; | |
815 | ||
816 | ||
817 | /* | |
818 | * Debug bus frame modes | |
819 | */ | |
820 | enum dbg_bus_frame_modes { | |
821 | DBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */, | |
822 | DBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */, | |
823 | DBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */, | |
824 | MAX_DBG_BUS_FRAME_MODES | |
825 | }; | |
826 | ||
827 | ||
7c673cae FG |
828 | /* |
829 | * Debug bus other engine mode | |
830 | */ | |
831 | enum dbg_bus_other_engine_modes { | |
832 | DBG_BUS_OTHER_ENGINE_MODE_NONE, | |
833 | DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, | |
834 | DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, | |
835 | DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, | |
836 | DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, | |
837 | MAX_DBG_BUS_OTHER_ENGINE_MODES | |
838 | }; | |
839 | ||
840 | ||
841 | ||
842 | /* | |
843 | * Debug bus post-trigger recording types | |
844 | */ | |
845 | enum dbg_bus_post_trigger_types { | |
846 | DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */, | |
847 | DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */, | |
848 | MAX_DBG_BUS_POST_TRIGGER_TYPES | |
849 | }; | |
850 | ||
851 | ||
852 | /* | |
853 | * Debug bus pre-trigger recording types | |
854 | */ | |
855 | enum dbg_bus_pre_trigger_types { | |
856 | DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */, | |
857 | /* start recording some chunks before trigger */ | |
858 | DBG_BUS_PRE_TRIGGER_NUM_CHUNKS, | |
859 | DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */, | |
860 | MAX_DBG_BUS_PRE_TRIGGER_TYPES | |
861 | }; | |
862 | ||
863 | ||
864 | /* | |
865 | * Debug bus SEMI frame modes | |
866 | */ | |
867 | enum dbg_bus_semi_frame_modes { | |
868 | /* 0 slow dwords, 4 fast dwords */ | |
869 | DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0, | |
870 | /* 4 slow dwords, 0 fast dwords */ | |
871 | DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3, | |
872 | MAX_DBG_BUS_SEMI_FRAME_MODES | |
873 | }; | |
874 | ||
875 | ||
876 | /* | |
877 | * Debug bus states | |
878 | */ | |
879 | enum dbg_bus_states { | |
880 | DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */, | |
881 | /* debug bus is ready for configuration and recording */ | |
882 | DBG_BUS_STATE_READY, | |
883 | DBG_BUS_STATE_RECORDING /* debug bus is currently recording */, | |
884 | DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */, | |
885 | MAX_DBG_BUS_STATES | |
886 | }; | |
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | /* | |
894 | * Debug Bus Storm modes | |
895 | */ | |
896 | enum dbg_bus_storm_modes { | |
897 | DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */, | |
898 | DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */, | |
899 | DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */, | |
900 | DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */, | |
901 | DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */, | |
902 | DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */, | |
903 | DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */, | |
904 | DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */, | |
905 | DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */, | |
906 | MAX_DBG_BUS_STORM_MODES | |
907 | }; | |
908 | ||
909 | ||
910 | /* | |
911 | * Debug bus target IDs | |
912 | */ | |
913 | enum dbg_bus_targets { | |
914 | /* records debug bus to DBG block internal buffer */ | |
915 | DBG_BUS_TARGET_ID_INT_BUF, | |
916 | DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */, | |
917 | DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */, | |
918 | MAX_DBG_BUS_TARGETS | |
919 | }; | |
920 | ||
921 | ||
11fdf7f2 | 922 | |
7c673cae FG |
923 | /* |
924 | * GRC Dump data | |
925 | */ | |
926 | struct dbg_grc_data { | |
11fdf7f2 TL |
927 | /* Indicates if the GRC parameters were initialized */ |
928 | u8 params_initialized; | |
929 | u8 reserved1; | |
930 | u16 reserved2; | |
931 | /* Value of each GRC parameter. Array size must match the enum dbg_grc_params. | |
7c673cae | 932 | */ |
11fdf7f2 | 933 | u32 param_val[48]; |
7c673cae FG |
934 | }; |
935 | ||
936 | ||
937 | /* | |
938 | * Debug GRC params | |
939 | */ | |
940 | enum dbg_grc_params { | |
941 | DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */, | |
942 | DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */, | |
943 | DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */, | |
944 | DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */, | |
945 | DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */, | |
946 | DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */, | |
947 | DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */, | |
948 | DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */, | |
949 | DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */, | |
950 | DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */, | |
951 | DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */, | |
952 | DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */, | |
953 | DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */, | |
954 | DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */, | |
955 | DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, | |
956 | DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, | |
957 | DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, | |
11fdf7f2 TL |
958 | /* MCP Trace meta data size in bytes */ |
959 | DBG_GRC_PARAM_MCP_TRACE_META_SIZE, | |
7c673cae FG |
960 | DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, |
961 | DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, | |
962 | DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, | |
963 | DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */, | |
964 | DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */, | |
965 | DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */, | |
966 | DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */, | |
967 | DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */, | |
968 | DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */, | |
969 | DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */, | |
970 | DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */, | |
971 | DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */, | |
972 | DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */, | |
973 | DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */, | |
974 | DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */, | |
975 | DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */, | |
976 | /* preset: exclude all memories from dump (1 only) */ | |
977 | DBG_GRC_PARAM_EXCLUDE_ALL, | |
978 | /* preset: include memories for crash dump (1 only) */ | |
979 | DBG_GRC_PARAM_CRASH, | |
980 | /* perform dump only if MFW is responding (0/1) */ | |
981 | DBG_GRC_PARAM_PARITY_SAFE, | |
982 | DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */, | |
983 | DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */, | |
11fdf7f2 TL |
984 | DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */, |
985 | DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, | |
7c673cae FG |
986 | MAX_DBG_GRC_PARAMS |
987 | }; | |
988 | ||
989 | ||
990 | /* | |
991 | * Debug reset registers | |
992 | */ | |
993 | enum dbg_reset_regs { | |
994 | DBG_RESET_REG_MISCS_PL_UA, | |
995 | DBG_RESET_REG_MISCS_PL_HV, | |
996 | DBG_RESET_REG_MISCS_PL_HV_2, | |
997 | DBG_RESET_REG_MISC_PL_UA, | |
998 | DBG_RESET_REG_MISC_PL_HV, | |
999 | DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, | |
1000 | DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, | |
1001 | DBG_RESET_REG_MISC_PL_PDA_VAUX, | |
1002 | MAX_DBG_RESET_REGS | |
1003 | }; | |
1004 | ||
1005 | ||
1006 | /* | |
1007 | * Debug status codes | |
1008 | */ | |
1009 | enum dbg_status { | |
1010 | DBG_STATUS_OK, | |
1011 | DBG_STATUS_APP_VERSION_NOT_SET, | |
1012 | DBG_STATUS_UNSUPPORTED_APP_VERSION, | |
1013 | DBG_STATUS_DBG_BLOCK_NOT_RESET, | |
1014 | DBG_STATUS_INVALID_ARGS, | |
1015 | DBG_STATUS_OUTPUT_ALREADY_SET, | |
1016 | DBG_STATUS_INVALID_PCI_BUF_SIZE, | |
1017 | DBG_STATUS_PCI_BUF_ALLOC_FAILED, | |
1018 | DBG_STATUS_PCI_BUF_NOT_ALLOCATED, | |
1019 | DBG_STATUS_TOO_MANY_INPUTS, | |
1020 | DBG_STATUS_INPUT_OVERLAP, | |
1021 | DBG_STATUS_HW_ONLY_RECORDING, | |
1022 | DBG_STATUS_STORM_ALREADY_ENABLED, | |
1023 | DBG_STATUS_STORM_NOT_ENABLED, | |
1024 | DBG_STATUS_BLOCK_ALREADY_ENABLED, | |
1025 | DBG_STATUS_BLOCK_NOT_ENABLED, | |
1026 | DBG_STATUS_NO_INPUT_ENABLED, | |
1027 | DBG_STATUS_NO_FILTER_TRIGGER_64B, | |
1028 | DBG_STATUS_FILTER_ALREADY_ENABLED, | |
1029 | DBG_STATUS_TRIGGER_ALREADY_ENABLED, | |
1030 | DBG_STATUS_TRIGGER_NOT_ENABLED, | |
1031 | DBG_STATUS_CANT_ADD_CONSTRAINT, | |
1032 | DBG_STATUS_TOO_MANY_TRIGGER_STATES, | |
1033 | DBG_STATUS_TOO_MANY_CONSTRAINTS, | |
1034 | DBG_STATUS_RECORDING_NOT_STARTED, | |
1035 | DBG_STATUS_DATA_DIDNT_TRIGGER, | |
1036 | DBG_STATUS_NO_DATA_RECORDED, | |
1037 | DBG_STATUS_DUMP_BUF_TOO_SMALL, | |
1038 | DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, | |
1039 | DBG_STATUS_UNKNOWN_CHIP, | |
1040 | DBG_STATUS_VIRT_MEM_ALLOC_FAILED, | |
1041 | DBG_STATUS_BLOCK_IN_RESET, | |
1042 | DBG_STATUS_INVALID_TRACE_SIGNATURE, | |
1043 | DBG_STATUS_INVALID_NVRAM_BUNDLE, | |
1044 | DBG_STATUS_NVRAM_GET_IMAGE_FAILED, | |
1045 | DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, | |
1046 | DBG_STATUS_NVRAM_READ_FAILED, | |
1047 | DBG_STATUS_IDLE_CHK_PARSE_FAILED, | |
1048 | DBG_STATUS_MCP_TRACE_BAD_DATA, | |
1049 | DBG_STATUS_MCP_TRACE_NO_META, | |
1050 | DBG_STATUS_MCP_COULD_NOT_HALT, | |
1051 | DBG_STATUS_MCP_COULD_NOT_RESUME, | |
11fdf7f2 | 1052 | DBG_STATUS_RESERVED2, |
7c673cae FG |
1053 | DBG_STATUS_SEMI_FIFO_NOT_EMPTY, |
1054 | DBG_STATUS_IGU_FIFO_BAD_DATA, | |
1055 | DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, | |
1056 | DBG_STATUS_FW_ASSERTS_PARSE_FAILED, | |
1057 | DBG_STATUS_REG_FIFO_BAD_DATA, | |
1058 | DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, | |
1059 | DBG_STATUS_DBG_ARRAY_NOT_SET, | |
11fdf7f2 TL |
1060 | DBG_STATUS_FILTER_BUG, |
1061 | DBG_STATUS_NON_MATCHING_LINES, | |
1062 | DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, | |
1063 | DBG_STATUS_DBG_BUS_IN_USE, | |
7c673cae FG |
1064 | MAX_DBG_STATUS |
1065 | }; | |
1066 | ||
1067 | ||
1068 | /* | |
1069 | * Debug Storms IDs | |
1070 | */ | |
1071 | enum dbg_storms { | |
1072 | DBG_TSTORM_ID, | |
1073 | DBG_MSTORM_ID, | |
1074 | DBG_USTORM_ID, | |
1075 | DBG_XSTORM_ID, | |
1076 | DBG_YSTORM_ID, | |
1077 | DBG_PSTORM_ID, | |
1078 | MAX_DBG_STORMS | |
1079 | }; | |
1080 | ||
1081 | ||
1082 | /* | |
1083 | * Idle Check data | |
1084 | */ | |
1085 | struct idle_chk_data { | |
11fdf7f2 | 1086 | u32 buf_size /* Idle check buffer size in dwords */; |
7c673cae FG |
1087 | /* Indicates if the idle check buffer size was set (0/1) */ |
1088 | u8 buf_size_set; | |
1089 | u8 reserved1; | |
11fdf7f2 | 1090 | u16 reserved2; |
7c673cae FG |
1091 | }; |
1092 | ||
9f95a23c TL |
1093 | /* |
1094 | * Pretend parameters | |
1095 | */ | |
1096 | struct pretend_params { | |
1097 | u8 split_type /* Pretend split type (from enum init_split_types) */; | |
1098 | u8 reserved; | |
1099 | u16 split_id /* Preted split ID (within the pretend split type) */; | |
1100 | }; | |
1101 | ||
7c673cae FG |
1102 | /* |
1103 | * Debug Tools data (per HW function) | |
1104 | */ | |
1105 | struct dbg_tools_data { | |
1106 | struct dbg_grc_data grc /* GRC Dump data */; | |
1107 | struct dbg_bus_data bus /* Debug Bus data */; | |
1108 | struct idle_chk_data idle_chk /* Idle Check data */; | |
1109 | u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */; | |
1110 | /* Indicates if a block is in reset state (0/1) */ | |
11fdf7f2 | 1111 | u8 block_in_reset[88]; |
7c673cae | 1112 | u8 chip_id /* Chip ID (from enum chip_ids) */; |
11fdf7f2 | 1113 | u8 platform_id /* Platform ID */; |
9f95a23c TL |
1114 | u8 num_ports /* Number of ports in the chip */; |
1115 | u8 num_pfs_per_port /* Number of PFs in each port */; | |
1116 | u8 num_vfs /* Number of VFs in the chip */; | |
7c673cae | 1117 | u8 initialized /* Indicates if the data was initialized */; |
11fdf7f2 | 1118 | u8 use_dmae /* Indicates if DMAE should be used */; |
9f95a23c TL |
1119 | u8 reserved; |
1120 | struct pretend_params pretend /* Current pretend parameters */; | |
11fdf7f2 TL |
1121 | /* Numbers of registers that were read since last log */ |
1122 | u32 num_regs_read; | |
7c673cae FG |
1123 | }; |
1124 | ||
1125 | ||
9f95a23c | 1126 | |
7c673cae | 1127 | #endif /* __ECORE_HSI_DEBUG_TOOLS__ */ |