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1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright (c) 2016 - 2018 Cavium Inc. | |
3 | * All rights reserved. | |
4 | * www.cavium.com | |
5 | */ | |
6 | ||
7 | #ifndef __ECORE_HSI_ETH__ | |
8 | #define __ECORE_HSI_ETH__ | |
9 | /************************************************************************/ | |
10 | /* Add include to common eth target for both eCore and protocol driver */ | |
11 | /************************************************************************/ | |
12 | #include "eth_common.h" | |
13 | ||
14 | /* | |
15 | * The eth storm context for the Tstorm | |
16 | */ | |
17 | struct tstorm_eth_conn_st_ctx { | |
18 | __le32 reserved[4]; | |
19 | }; | |
20 | ||
21 | /* | |
22 | * The eth storm context for the Pstorm | |
23 | */ | |
24 | struct pstorm_eth_conn_st_ctx { | |
25 | __le32 reserved[8]; | |
26 | }; | |
27 | ||
28 | /* | |
29 | * The eth storm context for the Xstorm | |
30 | */ | |
31 | struct xstorm_eth_conn_st_ctx { | |
32 | __le32 reserved[60]; | |
33 | }; | |
34 | ||
35 | struct e4_xstorm_eth_conn_ag_ctx { | |
36 | u8 reserved0 /* cdu_validation */; | |
37 | u8 eth_state /* state */; | |
38 | u8 flags0; | |
39 | /* exist_in_qm0 */ | |
40 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
41 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
42 | /* exist_in_qm1 */ | |
43 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
44 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
45 | /* exist_in_qm2 */ | |
46 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
47 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
48 | /* exist_in_qm3 */ | |
49 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
50 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
51 | /* bit4 */ | |
52 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
53 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
54 | /* cf_array_active */ | |
55 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
56 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
57 | /* bit6 */ | |
58 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
59 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
60 | /* bit7 */ | |
61 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
62 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
63 | u8 flags1; | |
64 | /* bit8 */ | |
65 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 | |
66 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
67 | /* bit9 */ | |
68 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
69 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
70 | /* bit10 */ | |
71 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
72 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
73 | /* bit11 */ | |
74 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 | |
75 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 | |
76 | /* bit12 */ | |
77 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 | |
78 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4 | |
79 | /* bit13 */ | |
80 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 | |
81 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5 | |
82 | /* bit14 */ | |
83 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 | |
84 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 | |
85 | /* bit15 */ | |
86 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 | |
87 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 | |
88 | u8 flags2; | |
89 | /* timer0cf */ | |
90 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 | |
91 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 | |
92 | /* timer1cf */ | |
93 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 | |
94 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 | |
95 | /* timer2cf */ | |
96 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
97 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 | |
98 | /* timer_stop_all */ | |
99 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 | |
100 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 | |
101 | u8 flags3; | |
102 | /* cf4 */ | |
103 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 | |
104 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 | |
105 | /* cf5 */ | |
106 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 | |
107 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 | |
108 | /* cf6 */ | |
109 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 | |
110 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 | |
111 | /* cf7 */ | |
112 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 | |
113 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 | |
114 | u8 flags4; | |
115 | /* cf8 */ | |
116 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 | |
117 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 | |
118 | /* cf9 */ | |
119 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 | |
120 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 | |
121 | /* cf10 */ | |
122 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 | |
123 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 | |
124 | /* cf11 */ | |
125 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 | |
126 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 | |
127 | u8 flags5; | |
128 | /* cf12 */ | |
129 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 | |
130 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 | |
131 | /* cf13 */ | |
132 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 | |
133 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 | |
134 | /* cf14 */ | |
135 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 | |
136 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 | |
137 | /* cf15 */ | |
138 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 | |
139 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 | |
140 | u8 flags6; | |
141 | /* cf16 */ | |
142 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 | |
143 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 | |
144 | /* cf_array_cf */ | |
145 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 | |
146 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 | |
147 | /* cf18 */ | |
148 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 | |
149 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 | |
150 | /* cf19 */ | |
151 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 | |
152 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 | |
153 | u8 flags7; | |
154 | /* cf20 */ | |
155 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 | |
156 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
157 | /* cf21 */ | |
158 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 | |
159 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
160 | /* cf22 */ | |
161 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
162 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
163 | /* cf0en */ | |
164 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 | |
165 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 | |
166 | /* cf1en */ | |
167 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 | |
168 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 | |
169 | u8 flags8; | |
170 | /* cf2en */ | |
171 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
172 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 | |
173 | /* cf3en */ | |
174 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
175 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 | |
176 | /* cf4en */ | |
177 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 | |
178 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 | |
179 | /* cf5en */ | |
180 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 | |
181 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 | |
182 | /* cf6en */ | |
183 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 | |
184 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 | |
185 | /* cf7en */ | |
186 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 | |
187 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 | |
188 | /* cf8en */ | |
189 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 | |
190 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 | |
191 | /* cf9en */ | |
192 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 | |
193 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 | |
194 | u8 flags9; | |
195 | /* cf10en */ | |
196 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 | |
197 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 | |
198 | /* cf11en */ | |
199 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 | |
200 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 | |
201 | /* cf12en */ | |
202 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 | |
203 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 | |
204 | /* cf13en */ | |
205 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 | |
206 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 | |
207 | /* cf14en */ | |
208 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 | |
209 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 | |
210 | /* cf15en */ | |
211 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 | |
212 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 | |
213 | /* cf16en */ | |
214 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 | |
215 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 | |
216 | /* cf_array_cf_en */ | |
217 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 | |
218 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 | |
219 | u8 flags10; | |
220 | /* cf18en */ | |
221 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 | |
222 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 | |
223 | /* cf19en */ | |
224 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 | |
225 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 | |
226 | /* cf20en */ | |
227 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
228 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
229 | /* cf21en */ | |
230 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
231 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
232 | /* cf22en */ | |
233 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
234 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
235 | /* cf23en */ | |
236 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 | |
237 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 | |
238 | /* rule0en */ | |
239 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 | |
240 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
241 | /* rule1en */ | |
242 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
243 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
244 | u8 flags11; | |
245 | /* rule2en */ | |
246 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 | |
247 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
248 | /* rule3en */ | |
249 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
250 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
251 | /* rule4en */ | |
252 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 | |
253 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 | |
254 | /* rule5en */ | |
255 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
256 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
257 | /* rule6en */ | |
258 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
259 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
260 | /* rule7en */ | |
261 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
262 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
263 | /* rule8en */ | |
264 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
265 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
266 | /* rule9en */ | |
267 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
268 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
269 | u8 flags12; | |
270 | /* rule10en */ | |
271 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 | |
272 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
273 | /* rule11en */ | |
274 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
275 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
276 | /* rule12en */ | |
277 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
278 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
279 | /* rule13en */ | |
280 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
281 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
282 | /* rule14en */ | |
283 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
284 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
285 | /* rule15en */ | |
286 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
287 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
288 | /* rule16en */ | |
289 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
290 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
291 | /* rule17en */ | |
292 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
293 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
294 | u8 flags13; | |
295 | /* rule18en */ | |
296 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 | |
297 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
298 | /* rule19en */ | |
299 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
300 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
301 | /* rule20en */ | |
302 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
303 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
304 | /* rule21en */ | |
305 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
306 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
307 | /* rule22en */ | |
308 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
309 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
310 | /* rule23en */ | |
311 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
312 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
313 | /* rule24en */ | |
314 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
315 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
316 | /* rule25en */ | |
317 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
318 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
319 | u8 flags14; | |
320 | /* bit16 */ | |
321 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 | |
322 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 | |
323 | /* bit17 */ | |
324 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 | |
325 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 | |
326 | /* bit18 */ | |
327 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 | |
328 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 | |
329 | /* bit19 */ | |
330 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 | |
331 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 | |
332 | /* bit20 */ | |
333 | #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 | |
334 | #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 | |
335 | /* bit21 */ | |
336 | #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
337 | #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
338 | /* cf23 */ | |
339 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 | |
340 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 | |
341 | u8 edpm_event_id /* byte2 */; | |
342 | __le16 physical_q0 /* physical_q0 */; | |
343 | __le16 e5_reserved1 /* physical_q1 */; | |
344 | __le16 edpm_num_bds /* physical_q2 */; | |
345 | __le16 tx_bd_cons /* word3 */; | |
346 | __le16 tx_bd_prod /* word4 */; | |
347 | __le16 updated_qm_pq_id /* word5 */; | |
348 | __le16 conn_dpi /* conn_dpi */; | |
349 | u8 byte3 /* byte3 */; | |
350 | u8 byte4 /* byte4 */; | |
351 | u8 byte5 /* byte5 */; | |
352 | u8 byte6 /* byte6 */; | |
353 | __le32 reg0 /* reg0 */; | |
354 | __le32 reg1 /* reg1 */; | |
355 | __le32 reg2 /* reg2 */; | |
356 | __le32 reg3 /* reg3 */; | |
357 | __le32 reg4 /* reg4 */; | |
358 | __le32 reg5 /* cf_array0 */; | |
359 | __le32 reg6 /* cf_array1 */; | |
360 | __le16 word7 /* word7 */; | |
361 | __le16 word8 /* word8 */; | |
362 | __le16 word9 /* word9 */; | |
363 | __le16 word10 /* word10 */; | |
364 | __le32 reg7 /* reg7 */; | |
365 | __le32 reg8 /* reg8 */; | |
366 | __le32 reg9 /* reg9 */; | |
367 | u8 byte7 /* byte7 */; | |
368 | u8 byte8 /* byte8 */; | |
369 | u8 byte9 /* byte9 */; | |
370 | u8 byte10 /* byte10 */; | |
371 | u8 byte11 /* byte11 */; | |
372 | u8 byte12 /* byte12 */; | |
373 | u8 byte13 /* byte13 */; | |
374 | u8 byte14 /* byte14 */; | |
375 | u8 byte15 /* byte15 */; | |
376 | u8 e5_reserved /* e5_reserved */; | |
377 | __le16 word11 /* word11 */; | |
378 | __le32 reg10 /* reg10 */; | |
379 | __le32 reg11 /* reg11 */; | |
380 | __le32 reg12 /* reg12 */; | |
381 | __le32 reg13 /* reg13 */; | |
382 | __le32 reg14 /* reg14 */; | |
383 | __le32 reg15 /* reg15 */; | |
384 | __le32 reg16 /* reg16 */; | |
385 | __le32 reg17 /* reg17 */; | |
386 | __le32 reg18 /* reg18 */; | |
387 | __le32 reg19 /* reg19 */; | |
388 | __le16 word12 /* word12 */; | |
389 | __le16 word13 /* word13 */; | |
390 | __le16 word14 /* word14 */; | |
391 | __le16 word15 /* word15 */; | |
392 | }; | |
393 | ||
394 | /* | |
395 | * The eth storm context for the Ystorm | |
396 | */ | |
397 | struct ystorm_eth_conn_st_ctx { | |
398 | __le32 reserved[8]; | |
399 | }; | |
400 | ||
401 | struct e4_ystorm_eth_conn_ag_ctx { | |
402 | u8 byte0 /* cdu_validation */; | |
403 | u8 state /* state */; | |
404 | u8 flags0; | |
405 | /* exist_in_qm0 */ | |
406 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 | |
407 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
408 | /* exist_in_qm1 */ | |
409 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
410 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
411 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ | |
412 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 | |
413 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ | |
414 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 | |
415 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ | |
416 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
417 | u8 flags1; | |
418 | /* cf0en */ | |
419 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 | |
420 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 | |
421 | /* cf1en */ | |
422 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 | |
423 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 | |
424 | /* cf2en */ | |
425 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
426 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
427 | /* rule0en */ | |
428 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
429 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
430 | /* rule1en */ | |
431 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
432 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
433 | /* rule2en */ | |
434 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
435 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
436 | /* rule3en */ | |
437 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
438 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
439 | /* rule4en */ | |
440 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
441 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
442 | u8 tx_q0_int_coallecing_timeset /* byte2 */; | |
443 | u8 byte3 /* byte3 */; | |
444 | __le16 word0 /* word0 */; | |
445 | __le32 terminate_spqe /* reg0 */; | |
446 | __le32 reg1 /* reg1 */; | |
447 | __le16 tx_bd_cons_upd /* word1 */; | |
448 | __le16 word2 /* word2 */; | |
449 | __le16 word3 /* word3 */; | |
450 | __le16 word4 /* word4 */; | |
451 | __le32 reg2 /* reg2 */; | |
452 | __le32 reg3 /* reg3 */; | |
453 | }; | |
454 | ||
455 | struct e4_tstorm_eth_conn_ag_ctx { | |
456 | u8 byte0 /* cdu_validation */; | |
457 | u8 byte1 /* state */; | |
458 | u8 flags0; | |
459 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ | |
460 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
461 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ | |
462 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
463 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ | |
464 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 | |
465 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ | |
466 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 | |
467 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ | |
468 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 | |
469 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ | |
470 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 | |
471 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ | |
472 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 | |
473 | u8 flags1; | |
474 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ | |
475 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 | |
476 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ | |
477 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 | |
478 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ | |
479 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 | |
480 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ | |
481 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 | |
482 | u8 flags2; | |
483 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ | |
484 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 | |
485 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ | |
486 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 | |
487 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ | |
488 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 | |
489 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ | |
490 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 | |
491 | u8 flags3; | |
492 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ | |
493 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 | |
494 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ | |
495 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 | |
496 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ | |
497 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 | |
498 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ | |
499 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 | |
500 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ | |
501 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 | |
502 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ | |
503 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 | |
504 | u8 flags4; | |
505 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ | |
506 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 | |
507 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ | |
508 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 | |
509 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ | |
510 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 | |
511 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ | |
512 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 | |
513 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ | |
514 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 | |
515 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ | |
516 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 | |
517 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ | |
518 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 | |
519 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ | |
520 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
521 | u8 flags5; | |
522 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ | |
523 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
524 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ | |
525 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
526 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ | |
527 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
528 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ | |
529 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
530 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ | |
531 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
532 | #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ | |
533 | #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 | |
534 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ | |
535 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
536 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ | |
537 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
538 | __le32 reg0 /* reg0 */; | |
539 | __le32 reg1 /* reg1 */; | |
540 | __le32 reg2 /* reg2 */; | |
541 | __le32 reg3 /* reg3 */; | |
542 | __le32 reg4 /* reg4 */; | |
543 | __le32 reg5 /* reg5 */; | |
544 | __le32 reg6 /* reg6 */; | |
545 | __le32 reg7 /* reg7 */; | |
546 | __le32 reg8 /* reg8 */; | |
547 | u8 byte2 /* byte2 */; | |
548 | u8 byte3 /* byte3 */; | |
549 | __le16 rx_bd_cons /* word0 */; | |
550 | u8 byte4 /* byte4 */; | |
551 | u8 byte5 /* byte5 */; | |
552 | __le16 rx_bd_prod /* word1 */; | |
553 | __le16 word2 /* conn_dpi */; | |
554 | __le16 word3 /* word3 */; | |
555 | __le32 reg9 /* reg9 */; | |
556 | __le32 reg10 /* reg10 */; | |
557 | }; | |
558 | ||
559 | struct e4_ustorm_eth_conn_ag_ctx { | |
560 | u8 byte0 /* cdu_validation */; | |
561 | u8 byte1 /* state */; | |
562 | u8 flags0; | |
563 | /* exist_in_qm0 */ | |
564 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 | |
565 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
566 | /* exist_in_qm1 */ | |
567 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
568 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
569 | /* timer0cf */ | |
570 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 | |
571 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 | |
572 | /* timer1cf */ | |
573 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 | |
574 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 | |
575 | /* timer2cf */ | |
576 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
577 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
578 | u8 flags1; | |
579 | /* timer_stop_all */ | |
580 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 | |
581 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 | |
582 | /* cf4 */ | |
583 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 | |
584 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 | |
585 | /* cf5 */ | |
586 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 | |
587 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 | |
588 | /* cf6 */ | |
589 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 | |
590 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 | |
591 | u8 flags2; | |
592 | /* cf0en */ | |
593 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 | |
594 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 | |
595 | /* cf1en */ | |
596 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 | |
597 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 | |
598 | /* cf2en */ | |
599 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
600 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
601 | /* cf3en */ | |
602 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
603 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 | |
604 | /* cf4en */ | |
605 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 | |
606 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 | |
607 | /* cf5en */ | |
608 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 | |
609 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 | |
610 | /* cf6en */ | |
611 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 | |
612 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 | |
613 | /* rule0en */ | |
614 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
615 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
616 | u8 flags3; | |
617 | /* rule1en */ | |
618 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
619 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
620 | /* rule2en */ | |
621 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
622 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
623 | /* rule3en */ | |
624 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
625 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
626 | /* rule4en */ | |
627 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
628 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
629 | /* rule5en */ | |
630 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
631 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
632 | /* rule6en */ | |
633 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
634 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
635 | /* rule7en */ | |
636 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
637 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
638 | /* rule8en */ | |
639 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
640 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
641 | u8 byte2 /* byte2 */; | |
642 | u8 byte3 /* byte3 */; | |
643 | __le16 word0 /* conn_dpi */; | |
644 | __le16 tx_bd_cons /* word1 */; | |
645 | __le32 reg0 /* reg0 */; | |
646 | __le32 reg1 /* reg1 */; | |
647 | __le32 reg2 /* reg2 */; | |
648 | __le32 tx_int_coallecing_timeset /* reg3 */; | |
649 | __le16 tx_drv_bd_cons /* word2 */; | |
650 | __le16 rx_drv_cqe_cons /* word3 */; | |
651 | }; | |
652 | ||
653 | /* | |
654 | * The eth storm context for the Ustorm | |
655 | */ | |
656 | struct ustorm_eth_conn_st_ctx { | |
657 | __le32 reserved[40]; | |
658 | }; | |
659 | ||
660 | /* | |
661 | * The eth storm context for the Mstorm | |
662 | */ | |
663 | struct mstorm_eth_conn_st_ctx { | |
664 | __le32 reserved[8]; | |
665 | }; | |
666 | ||
667 | /* | |
668 | * eth connection context | |
669 | */ | |
670 | struct e4_eth_conn_context { | |
671 | /* tstorm storm context */ | |
672 | struct tstorm_eth_conn_st_ctx tstorm_st_context; | |
673 | struct regpair tstorm_st_padding[2] /* padding */; | |
674 | /* pstorm storm context */ | |
675 | struct pstorm_eth_conn_st_ctx pstorm_st_context; | |
676 | /* xstorm storm context */ | |
677 | struct xstorm_eth_conn_st_ctx xstorm_st_context; | |
678 | /* xstorm aggregative context */ | |
679 | struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context; | |
680 | /* ystorm storm context */ | |
681 | struct ystorm_eth_conn_st_ctx ystorm_st_context; | |
682 | /* ystorm aggregative context */ | |
683 | struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context; | |
684 | /* tstorm aggregative context */ | |
685 | struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context; | |
686 | /* ustorm aggregative context */ | |
687 | struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context; | |
688 | /* ustorm storm context */ | |
689 | struct ustorm_eth_conn_st_ctx ustorm_st_context; | |
690 | /* mstorm storm context */ | |
691 | struct mstorm_eth_conn_st_ctx mstorm_st_context; | |
692 | }; | |
693 | ||
694 | ||
695 | /* | |
696 | * Ethernet filter types: mac/vlan/pair | |
697 | */ | |
698 | enum eth_error_code { | |
699 | ETH_OK = 0x00 /* command succeeded */, | |
700 | /* mac add filters command failed due to cam full state */ | |
701 | ETH_FILTERS_MAC_ADD_FAIL_FULL, | |
702 | /* mac add filters command failed due to mtt2 full state */ | |
703 | ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, | |
704 | /* mac add filters command failed due to duplicate mac address */ | |
705 | ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, | |
706 | /* mac add filters command failed due to duplicate mac address */ | |
707 | ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, | |
708 | /* mac delete filters command failed due to not found state */ | |
709 | ETH_FILTERS_MAC_DEL_FAIL_NOF, | |
710 | /* mac delete filters command failed due to not found state */ | |
711 | ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, | |
712 | /* mac delete filters command failed due to not found state */ | |
713 | ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, | |
714 | /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */ | |
715 | ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, | |
716 | /* vlan add filters command failed due to cam full state */ | |
717 | ETH_FILTERS_VLAN_ADD_FAIL_FULL, | |
718 | /* vlan add filters command failed due to duplicate VLAN filter */ | |
719 | ETH_FILTERS_VLAN_ADD_FAIL_DUP, | |
720 | /* vlan delete filters command failed due to not found state */ | |
721 | ETH_FILTERS_VLAN_DEL_FAIL_NOF, | |
722 | /* vlan delete filters command failed due to not found state */ | |
723 | ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, | |
724 | /* pair add filters command failed due to duplicate request */ | |
725 | ETH_FILTERS_PAIR_ADD_FAIL_DUP, | |
726 | /* pair add filters command failed due to full state */ | |
727 | ETH_FILTERS_PAIR_ADD_FAIL_FULL, | |
728 | /* pair add filters command failed due to full state */ | |
729 | ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, | |
730 | /* pair add filters command failed due not found state */ | |
731 | ETH_FILTERS_PAIR_DEL_FAIL_NOF, | |
732 | /* pair add filters command failed due not found state */ | |
733 | ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, | |
734 | /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */ | |
735 | ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, | |
736 | /* vni add filters command failed due to cam full state */ | |
737 | ETH_FILTERS_VNI_ADD_FAIL_FULL, | |
738 | /* vni add filters command failed due to duplicate VNI filter */ | |
739 | ETH_FILTERS_VNI_ADD_FAIL_DUP, | |
740 | ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */, | |
741 | MAX_ETH_ERROR_CODE | |
742 | }; | |
743 | ||
744 | ||
745 | /* | |
746 | * opcodes for the event ring | |
747 | */ | |
748 | enum eth_event_opcode { | |
749 | ETH_EVENT_UNUSED, | |
750 | ETH_EVENT_VPORT_START, | |
751 | ETH_EVENT_VPORT_UPDATE, | |
752 | ETH_EVENT_VPORT_STOP, | |
753 | ETH_EVENT_TX_QUEUE_START, | |
754 | ETH_EVENT_TX_QUEUE_STOP, | |
755 | ETH_EVENT_RX_QUEUE_START, | |
756 | ETH_EVENT_RX_QUEUE_UPDATE, | |
757 | ETH_EVENT_RX_QUEUE_STOP, | |
758 | ETH_EVENT_FILTERS_UPDATE, | |
759 | ETH_EVENT_RX_ADD_OPENFLOW_FILTER, | |
760 | ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, | |
761 | ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, | |
762 | ETH_EVENT_RX_ADD_UDP_FILTER, | |
763 | ETH_EVENT_RX_DELETE_UDP_FILTER, | |
764 | ETH_EVENT_RX_CREATE_GFT_ACTION, | |
765 | ETH_EVENT_RX_GFT_UPDATE_FILTER, | |
766 | ETH_EVENT_TX_QUEUE_UPDATE, | |
767 | MAX_ETH_EVENT_OPCODE | |
768 | }; | |
769 | ||
770 | ||
771 | /* | |
772 | * Classify rule types in E2/E3 | |
773 | */ | |
774 | enum eth_filter_action { | |
775 | ETH_FILTER_ACTION_UNUSED, | |
776 | ETH_FILTER_ACTION_REMOVE, | |
777 | ETH_FILTER_ACTION_ADD, | |
778 | /* Remove all filters of given type and vport ID. */ | |
779 | ETH_FILTER_ACTION_REMOVE_ALL, | |
780 | MAX_ETH_FILTER_ACTION | |
781 | }; | |
782 | ||
783 | ||
784 | /* | |
785 | * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ | |
786 | */ | |
787 | struct eth_filter_cmd { | |
788 | u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */; | |
789 | u8 vport_id /* the vport id */; | |
790 | u8 action /* filter command action: add/remove/replace */; | |
791 | u8 reserved0; | |
792 | __le32 vni; | |
793 | __le16 mac_lsb; | |
794 | __le16 mac_mid; | |
795 | __le16 mac_msb; | |
796 | __le16 vlan_id; | |
797 | }; | |
798 | ||
799 | ||
800 | /* | |
801 | * $$KEEP_ENDIANNESS$$ | |
802 | */ | |
803 | struct eth_filter_cmd_header { | |
804 | u8 rx /* If set, apply these commands to the RX path */; | |
805 | u8 tx /* If set, apply these commands to the TX path */; | |
806 | u8 cmd_cnt /* Number of filter commands */; | |
807 | /* 0 - dont assert in case of filter configuration error. Just return an error | |
808 | * code. 1 - assert in case of filter configuration error. | |
809 | */ | |
810 | u8 assert_on_error; | |
811 | u8 reserved1[4]; | |
812 | }; | |
813 | ||
814 | ||
815 | /* | |
816 | * Ethernet filter types: mac/vlan/pair | |
817 | */ | |
818 | enum eth_filter_type { | |
819 | ETH_FILTER_TYPE_UNUSED, | |
820 | ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */, | |
821 | ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */, | |
822 | ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */, | |
823 | ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */, | |
824 | ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */, | |
825 | ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */, | |
826 | /* Add/remove a inner MAC-VNI pair */ | |
827 | ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, | |
828 | ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */, | |
829 | ETH_FILTER_TYPE_VNI /* Add/remove a VNI */, | |
830 | MAX_ETH_FILTER_TYPE | |
831 | }; | |
832 | ||
833 | ||
834 | /* | |
835 | * eth IPv4 Fragment Type | |
836 | */ | |
837 | enum eth_ipv4_frag_type { | |
838 | ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */, | |
839 | /* First Fragment of IPv4 Packet (contains headers) */ | |
840 | ETH_IPV4_FIRST_FRAG, | |
841 | /* Non-First Fragment of IPv4 Packet (does not contain headers) */ | |
842 | ETH_IPV4_NON_FIRST_FRAG, | |
843 | MAX_ETH_IPV4_FRAG_TYPE | |
844 | }; | |
845 | ||
846 | ||
847 | /* | |
848 | * eth IPv4 Fragment Type | |
849 | */ | |
850 | enum eth_ip_type { | |
851 | ETH_IPV4 /* IPv4 */, | |
852 | ETH_IPV6 /* IPv6 */, | |
853 | MAX_ETH_IP_TYPE | |
854 | }; | |
855 | ||
856 | ||
857 | /* | |
858 | * Ethernet Ramrod Command IDs | |
859 | */ | |
860 | enum eth_ramrod_cmd_id { | |
861 | ETH_RAMROD_UNUSED, | |
862 | ETH_RAMROD_VPORT_START /* VPort Start Ramrod */, | |
863 | ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */, | |
864 | ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */, | |
865 | ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, | |
866 | ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, | |
867 | ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, | |
868 | ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, | |
869 | ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */, | |
870 | ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */, | |
871 | /* RX - Create an Openflow Action */ | |
872 | ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, | |
873 | /* RX - Add an Openflow Filter to the Searcher */ | |
874 | ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, | |
875 | /* RX - Delete an Openflow Filter to the Searcher */ | |
876 | ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, | |
877 | /* RX - Add a UDP Filter to the Searcher */ | |
878 | ETH_RAMROD_RX_ADD_UDP_FILTER, | |
879 | /* RX - Delete a UDP Filter to the Searcher */ | |
880 | ETH_RAMROD_RX_DELETE_UDP_FILTER, | |
881 | ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */, | |
882 | /* RX - Add/Delete a GFT Filter to the Searcher */ | |
883 | ETH_RAMROD_GFT_UPDATE_FILTER, | |
884 | ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */, | |
885 | MAX_ETH_RAMROD_CMD_ID | |
886 | }; | |
887 | ||
888 | ||
889 | /* | |
890 | * return code from eth sp ramrods | |
891 | */ | |
892 | struct eth_return_code { | |
893 | u8 value; | |
894 | /* error code (use enum eth_error_code) */ | |
895 | #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F | |
896 | #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 | |
897 | #define ETH_RETURN_CODE_RESERVED_MASK 0x3 | |
898 | #define ETH_RETURN_CODE_RESERVED_SHIFT 5 | |
899 | /* rx path - 0, tx path - 1 */ | |
900 | #define ETH_RETURN_CODE_RX_TX_MASK 0x1 | |
901 | #define ETH_RETURN_CODE_RX_TX_SHIFT 7 | |
902 | }; | |
903 | ||
904 | ||
905 | /* | |
906 | * What to do in case an error occurs | |
907 | */ | |
908 | enum eth_tx_err { | |
909 | ETH_TX_ERR_DROP /* Drop erroneous packet. */, | |
910 | /* Assert an interrupt for PF, declare as malicious for VF */ | |
911 | ETH_TX_ERR_ASSERT_MALICIOUS, | |
912 | MAX_ETH_TX_ERR | |
913 | }; | |
914 | ||
915 | ||
916 | /* | |
917 | * Array of the different error type behaviors | |
918 | */ | |
919 | struct eth_tx_err_vals { | |
920 | __le16 values; | |
921 | /* Wrong VLAN insertion mode (use enum eth_tx_err) */ | |
922 | #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 | |
923 | #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 | |
924 | /* Packet is below minimal size (use enum eth_tx_err) */ | |
925 | #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 | |
926 | #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 | |
927 | /* Vport has sent spoofed packet (use enum eth_tx_err) */ | |
928 | #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 | |
929 | #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 | |
930 | /* Packet with illegal type of inband tag (use enum eth_tx_err) */ | |
931 | #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 | |
932 | #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 | |
933 | /* Packet marked for VLAN insertion when inband tag is present | |
934 | * (use enum eth_tx_err) | |
935 | */ | |
936 | #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 | |
937 | #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 | |
938 | /* Non LSO packet larger than MTU (use enum eth_tx_err) */ | |
939 | #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 | |
940 | #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 | |
941 | /* VF/PF has sent LLDP/PFC or any other type of control packet which is not | |
942 | * allowed to (use enum eth_tx_err) | |
943 | */ | |
944 | #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 | |
945 | #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 | |
946 | #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF | |
947 | #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 | |
948 | }; | |
949 | ||
950 | ||
951 | /* | |
952 | * vport rss configuration data | |
953 | */ | |
954 | struct eth_vport_rss_config { | |
955 | __le16 capabilities; | |
956 | /* configuration of the IpV4 2-tuple capability */ | |
957 | #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 | |
958 | #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 | |
959 | /* configuration of the IpV6 2-tuple capability */ | |
960 | #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 | |
961 | #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 | |
962 | /* configuration of the IpV4 4-tuple capability for TCP */ | |
963 | #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 | |
964 | #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 | |
965 | /* configuration of the IpV6 4-tuple capability for TCP */ | |
966 | #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 | |
967 | #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 | |
968 | /* configuration of the IpV4 4-tuple capability for UDP */ | |
969 | #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 | |
970 | #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 | |
971 | /* configuration of the IpV6 4-tuple capability for UDP */ | |
972 | #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 | |
973 | #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 | |
974 | /* configuration of the 5-tuple capability */ | |
975 | #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 | |
976 | #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 | |
977 | /* if set update the rss keys */ | |
978 | #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF | |
979 | #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 | |
980 | /* The RSS engine ID. Must be allocated to each vport with RSS enabled. | |
981 | * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type. | |
982 | */ | |
983 | u8 rss_id; | |
984 | u8 rss_mode /* The RSS mode for this function */; | |
985 | u8 update_rss_key /* if set update the rss key */; | |
986 | /* if set update the indirection table values */ | |
987 | u8 update_rss_ind_table; | |
988 | /* if set update the capabilities and indirection table size. */ | |
989 | u8 update_rss_capabilities; | |
990 | u8 tbl_size /* rss mask (Tbl size) */; | |
991 | __le32 reserved2[2]; | |
992 | /* RSS indirection table */ | |
993 | __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; | |
994 | /* RSS key supplied to us by OS */ | |
995 | __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; | |
996 | __le32 reserved3[2]; | |
997 | }; | |
998 | ||
999 | ||
1000 | /* | |
1001 | * eth vport RSS mode | |
1002 | */ | |
1003 | enum eth_vport_rss_mode { | |
1004 | ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */, | |
1005 | ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, | |
1006 | MAX_ETH_VPORT_RSS_MODE | |
1007 | }; | |
1008 | ||
1009 | ||
1010 | /* | |
1011 | * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ | |
1012 | */ | |
1013 | struct eth_vport_rx_mode { | |
1014 | __le16 state; | |
1015 | /* drop all unicast packets */ | |
1016 | #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 | |
1017 | #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 | |
1018 | /* accept all unicast packets (subject to vlan) */ | |
1019 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 | |
1020 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 | |
1021 | /* accept all unmatched unicast packets */ | |
1022 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 | |
1023 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
1024 | /* drop all multicast packets */ | |
1025 | #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 | |
1026 | #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 | |
1027 | /* accept all multicast packets (subject to vlan) */ | |
1028 | #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 | |
1029 | #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 | |
1030 | /* accept all broadcast packets (subject to vlan) */ | |
1031 | #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 | |
1032 | #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 | |
1033 | #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF | |
1034 | #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 | |
1035 | }; | |
1036 | ||
1037 | ||
1038 | /* | |
1039 | * Command for setting tpa parameters | |
1040 | */ | |
1041 | struct eth_vport_tpa_param { | |
1042 | u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */; | |
1043 | u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */; | |
1044 | u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */; | |
1045 | u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; | |
1046 | /* If set, start each TPA segment on new BD (GRO mode). One BD per segment | |
1047 | * allowed. | |
1048 | */ | |
1049 | u8 tpa_pkt_split_flg; | |
1050 | /* If set, put header of first TPA segment on first BD and data on second BD. */ | |
1051 | u8 tpa_hdr_data_split_flg; | |
1052 | /* If set, GRO data consistent will checked for TPA continue */ | |
1053 | u8 tpa_gro_consistent_flg; | |
1054 | /* maximum number of opened aggregations per v-port */ | |
1055 | u8 tpa_max_aggs_num; | |
1056 | __le16 tpa_max_size /* maximal size for the aggregated TPA packets */; | |
1057 | /* minimum TCP payload size for a packet to start aggregation */ | |
1058 | __le16 tpa_min_size_to_start; | |
1059 | /* minimum TCP payload size for a packet to continue aggregation */ | |
1060 | __le16 tpa_min_size_to_cont; | |
1061 | /* maximal number of buffers that can be used for one aggregation */ | |
1062 | u8 max_buff_num; | |
1063 | u8 reserved; | |
1064 | }; | |
1065 | ||
1066 | ||
1067 | /* | |
1068 | * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ | |
1069 | */ | |
1070 | struct eth_vport_tx_mode { | |
1071 | __le16 state; | |
1072 | /* drop all unicast packets */ | |
1073 | #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 | |
1074 | #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 | |
1075 | /* accept all unicast packets (subject to vlan) */ | |
1076 | #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 | |
1077 | #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 | |
1078 | /* drop all multicast packets */ | |
1079 | #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 | |
1080 | #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 | |
1081 | /* accept all multicast packets (subject to vlan) */ | |
1082 | #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 | |
1083 | #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 | |
1084 | /* accept all broadcast packets (subject to vlan) */ | |
1085 | #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 | |
1086 | #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 | |
1087 | #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF | |
1088 | #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 | |
1089 | }; | |
1090 | ||
1091 | ||
1092 | /* | |
1093 | * GFT filter update action type. | |
1094 | */ | |
1095 | enum gft_filter_update_action { | |
1096 | GFT_ADD_FILTER, | |
1097 | GFT_DELETE_FILTER, | |
1098 | MAX_GFT_FILTER_UPDATE_ACTION | |
1099 | }; | |
1100 | ||
1101 | ||
1102 | ||
1103 | ||
1104 | /* | |
1105 | * Ramrod data for rx add openflow filter | |
1106 | */ | |
1107 | struct rx_add_openflow_filter_data { | |
1108 | __le16 action_icid /* CID of Action to run for this filter */; | |
1109 | u8 priority /* Searcher String - Packet priority */; | |
1110 | u8 reserved0; | |
1111 | __le32 tenant_id /* Searcher String - Tenant ID */; | |
1112 | /* Searcher String - Destination Mac Bytes 0 to 1 */ | |
1113 | __le16 dst_mac_hi; | |
1114 | /* Searcher String - Destination Mac Bytes 2 to 3 */ | |
1115 | __le16 dst_mac_mid; | |
1116 | /* Searcher String - Destination Mac Bytes 4 to 5 */ | |
1117 | __le16 dst_mac_lo; | |
1118 | __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */; | |
1119 | __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */; | |
1120 | __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */; | |
1121 | __le16 vlan_id /* Searcher String - Vlan ID */; | |
1122 | __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */; | |
1123 | u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */; | |
1124 | u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */; | |
1125 | u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */; | |
1126 | u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; | |
1127 | __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */; | |
1128 | __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */; | |
1129 | __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */; | |
1130 | __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */; | |
1131 | }; | |
1132 | ||
1133 | ||
1134 | /* | |
1135 | * Ramrod data for rx create gft action | |
1136 | */ | |
1137 | struct rx_create_gft_action_data { | |
1138 | u8 vport_id /* Vport Id of GFT Action */; | |
1139 | u8 reserved[7]; | |
1140 | }; | |
1141 | ||
1142 | ||
1143 | /* | |
1144 | * Ramrod data for rx create openflow action | |
1145 | */ | |
1146 | struct rx_create_openflow_action_data { | |
1147 | u8 vport_id /* ID of RX queue */; | |
1148 | u8 reserved[7]; | |
1149 | }; | |
1150 | ||
1151 | ||
1152 | /* | |
1153 | * Ramrod data for rx queue start ramrod | |
1154 | */ | |
1155 | struct rx_queue_start_ramrod_data { | |
1156 | __le16 rx_queue_id /* ID of RX queue */; | |
1157 | __le16 num_of_pbl_pages /* Number of pages in CQE PBL */; | |
1158 | __le16 bd_max_bytes /* maximal bytes that can be places on the bd */; | |
1159 | __le16 sb_id /* Status block ID */; | |
1160 | u8 sb_index /* index of the protocol index */; | |
1161 | u8 vport_id /* ID of virtual port */; | |
1162 | u8 default_rss_queue_flg /* set queue as default rss queue if set */; | |
1163 | u8 complete_cqe_flg /* post completion to the CQE ring if set */; | |
1164 | u8 complete_event_flg /* post completion to the event ring if set */; | |
1165 | u8 stats_counter_id /* Statistics counter ID */; | |
1166 | u8 pin_context /* Pin context in CCFC to improve performance */; | |
1167 | u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */; | |
1168 | /* PXP command TPH Valid - for packet placement */ | |
1169 | u8 pxp_tph_valid_pkt; | |
1170 | /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */ | |
1171 | u8 pxp_st_hint; | |
1172 | __le16 pxp_st_index /* PXP command Steering tag index */; | |
1173 | /* Indicates that current queue belongs to poll-mode driver */ | |
1174 | u8 pmd_mode; | |
1175 | /* Indicates that the current queue is using the TX notification queue | |
1176 | * mechanism - should be set only for PMD queue | |
1177 | */ | |
1178 | u8 notify_en; | |
1179 | /* Initial value for the toggle valid bit - used in PMD mode */ | |
1180 | u8 toggle_val; | |
1181 | /* Index of RX producers in VF zone. Used for VF only. */ | |
1182 | u8 vf_rx_prod_index; | |
1183 | /* Backward compatibility mode. If set, unprotected mStorm queue zone will used | |
1184 | * for VF RX producers instead of VF zone. | |
1185 | */ | |
1186 | u8 vf_rx_prod_use_zone_a; | |
1187 | u8 reserved[5]; | |
1188 | __le16 reserved1 /* FW reserved. */; | |
1189 | struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; | |
1190 | struct regpair bd_base /* bd address of the first bd page */; | |
1191 | struct regpair reserved2 /* FW reserved. */; | |
1192 | }; | |
1193 | ||
1194 | ||
1195 | /* | |
1196 | * Ramrod data for rx queue stop ramrod | |
1197 | */ | |
1198 | struct rx_queue_stop_ramrod_data { | |
1199 | __le16 rx_queue_id /* ID of RX queue */; | |
1200 | u8 complete_cqe_flg /* post completion to the CQE ring if set */; | |
1201 | u8 complete_event_flg /* post completion to the event ring if set */; | |
1202 | u8 vport_id /* ID of virtual port */; | |
1203 | u8 reserved[3]; | |
1204 | }; | |
1205 | ||
1206 | ||
1207 | /* | |
1208 | * Ramrod data for rx queue update ramrod | |
1209 | */ | |
1210 | struct rx_queue_update_ramrod_data { | |
1211 | __le16 rx_queue_id /* ID of RX queue */; | |
1212 | u8 complete_cqe_flg /* post completion to the CQE ring if set */; | |
1213 | u8 complete_event_flg /* post completion to the event ring if set */; | |
1214 | u8 vport_id /* ID of virtual port */; | |
1215 | /* If set, update default rss queue to this RX queue. */ | |
1216 | u8 set_default_rss_queue; | |
1217 | u8 reserved[3]; | |
1218 | u8 reserved1 /* FW reserved. */; | |
1219 | u8 reserved2 /* FW reserved. */; | |
1220 | u8 reserved3 /* FW reserved. */; | |
1221 | __le16 reserved4 /* FW reserved. */; | |
1222 | __le16 reserved5 /* FW reserved. */; | |
1223 | struct regpair reserved6 /* FW reserved. */; | |
1224 | }; | |
1225 | ||
1226 | ||
1227 | /* | |
1228 | * Ramrod data for rx Add UDP Filter | |
1229 | */ | |
1230 | struct rx_udp_filter_data { | |
1231 | __le16 action_icid /* CID of Action to run for this filter */; | |
1232 | __le16 vlan_id /* Searcher String - Vlan ID */; | |
1233 | u8 ip_type /* Searcher String - IP Type */; | |
1234 | u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; | |
1235 | __le16 reserved1; | |
1236 | /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */ | |
1237 | __le32 ip_dst_addr[4]; | |
1238 | /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */ | |
1239 | __le32 ip_src_addr[4]; | |
1240 | __le16 udp_dst_port /* Searcher String - UDP Destination Port */; | |
1241 | __le16 udp_src_port /* Searcher String - UDP Source Port */; | |
1242 | __le32 tenant_id /* Searcher String - Tenant ID */; | |
1243 | }; | |
1244 | ||
1245 | ||
1246 | /* | |
1247 | * add or delete GFT filter - filter is packet header of type of packet wished | |
1248 | * to pass certain FW flow | |
1249 | */ | |
1250 | struct rx_update_gft_filter_data { | |
1251 | /* Pointer to Packet Header That Defines GFT Filter */ | |
1252 | struct regpair pkt_hdr_addr; | |
1253 | __le16 pkt_hdr_length /* Packet Header Length */; | |
1254 | /* Action icid. Valid if action_icid_valid flag set. */ | |
1255 | __le16 action_icid; | |
1256 | __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */; | |
1257 | __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */; | |
1258 | /* RX vport Id. For drop flow, set to ETH_GFT_TRASHCAN_VPORT. */ | |
1259 | __le16 vport_id; | |
1260 | /* If set, action_icid will used for GFT filter update. */ | |
1261 | u8 action_icid_valid; | |
1262 | /* If set, rx_qid will used for traffic steering, in additional to vport_id. | |
1263 | * flow_id_valid must be cleared. If cleared, queue ID will selected by RSS. | |
1264 | */ | |
1265 | u8 rx_qid_valid; | |
1266 | /* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If | |
1267 | * cleared, flow_id 0 will reported by CQE. | |
1268 | */ | |
1269 | u8 flow_id_valid; | |
1270 | u8 filter_action /* Use to set type of action on filter */; | |
1271 | /* 0 - dont assert in case of error. Just return an error code. 1 - assert in | |
1272 | * case of error. | |
1273 | */ | |
1274 | u8 assert_on_error; | |
1275 | /* If set, inner VLAN will be removed regardless to VPORT configuration. | |
1276 | * Supported by E4 only. | |
1277 | */ | |
1278 | u8 inner_vlan_removal_en; | |
1279 | }; | |
1280 | ||
1281 | ||
1282 | ||
1283 | /* | |
1284 | * Ramrod data for tx queue start ramrod | |
1285 | */ | |
1286 | struct tx_queue_start_ramrod_data { | |
1287 | __le16 sb_id /* Status block ID */; | |
1288 | u8 sb_index /* Status block protocol index */; | |
1289 | u8 vport_id /* VPort ID */; | |
1290 | u8 reserved0 /* FW reserved. (qcn_rl_en) */; | |
1291 | u8 stats_counter_id /* Statistics counter ID to use */; | |
1292 | __le16 qm_pq_id /* QM PQ ID */; | |
1293 | u8 flags; | |
1294 | /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */ | |
1295 | #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 | |
1296 | #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 | |
1297 | /* If set, Test Mode - packets will be duplicated by Xstorm handler */ | |
1298 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 | |
1299 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 | |
1300 | /* If set, Test Mode - packets destination will be determined by dest_port_mode | |
1301 | * field from Tx BD | |
1302 | */ | |
1303 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 | |
1304 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 | |
1305 | /* Indicates that current queue belongs to poll-mode driver */ | |
1306 | #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 | |
1307 | #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 | |
1308 | /* Indicates that the current queue is using the TX notification queue | |
1309 | * mechanism - should be set only for PMD queue | |
1310 | */ | |
1311 | #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 | |
1312 | #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 | |
1313 | /* Pin context in CCFC to improve performance */ | |
1314 | #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 | |
1315 | #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 | |
1316 | #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 | |
1317 | #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 | |
1318 | u8 pxp_st_hint /* PXP command Steering tag hint */; | |
1319 | u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */; | |
1320 | u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */; | |
1321 | __le16 pxp_st_index /* PXP command Steering tag index */; | |
1322 | /* TX completion min agg size - for PMD queues */ | |
1323 | __le16 comp_agg_size; | |
1324 | __le16 queue_zone_id /* queue zone ID to use */; | |
1325 | __le16 reserved2 /* FW reserved. (test_dup_count) */; | |
1326 | __le16 pbl_size /* Number of BD pages pointed by PBL */; | |
1327 | /* unique Queue ID - currently used only by PMD flow */ | |
1328 | __le16 tx_queue_id; | |
1329 | /* Unique Same-As-Last Resource ID - improves performance for same-as-last | |
1330 | * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs | |
1331 | * available) | |
1332 | */ | |
1333 | __le16 same_as_last_id; | |
1334 | __le16 reserved[3]; | |
1335 | struct regpair pbl_base_addr /* address of the pbl page */; | |
1336 | /* BD consumer address in host - for PMD queues */ | |
1337 | struct regpair bd_cons_address; | |
1338 | }; | |
1339 | ||
1340 | ||
1341 | /* | |
1342 | * Ramrod data for tx queue stop ramrod | |
1343 | */ | |
1344 | struct tx_queue_stop_ramrod_data { | |
1345 | __le16 reserved[4]; | |
1346 | }; | |
1347 | ||
1348 | ||
1349 | /* | |
1350 | * Ramrod data for tx queue update ramrod | |
1351 | */ | |
1352 | struct tx_queue_update_ramrod_data { | |
1353 | __le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */; | |
1354 | __le16 qm_pq_id /* Updated QM PQ ID */; | |
1355 | __le32 reserved0; | |
1356 | struct regpair reserved1[5]; | |
1357 | }; | |
1358 | ||
1359 | ||
1360 | ||
1361 | /* | |
1362 | * Ramrod data for vport update ramrod | |
1363 | */ | |
1364 | struct vport_filter_update_ramrod_data { | |
1365 | /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */ | |
1366 | struct eth_filter_cmd_header filter_cmd_hdr; | |
1367 | /* Filter Commands */ | |
1368 | struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; | |
1369 | }; | |
1370 | ||
1371 | ||
1372 | /* | |
1373 | * Ramrod data for vport start ramrod | |
1374 | */ | |
1375 | struct vport_start_ramrod_data { | |
1376 | u8 vport_id; | |
1377 | u8 sw_fid; | |
1378 | __le16 mtu; | |
1379 | u8 drop_ttl0_en /* if set, drop packet with ttl=0 */; | |
1380 | u8 inner_vlan_removal_en; | |
1381 | struct eth_vport_rx_mode rx_mode /* Rx filter data */; | |
1382 | struct eth_vport_tx_mode tx_mode /* Tx filter data */; | |
1383 | /* TPA configuration parameters */ | |
1384 | struct eth_vport_tpa_param tpa_param; | |
1385 | __le16 default_vlan /* Default Vlan value to be forced by FW */; | |
1386 | u8 tx_switching_en /* Tx switching is enabled for current Vport */; | |
1387 | /* Anti-spoofing verification is set for current Vport */ | |
1388 | u8 anti_spoofing_en; | |
1389 | /* If set, the default Vlan value is forced by the FW */ | |
1390 | u8 default_vlan_en; | |
1391 | /* If set, the vport handles PTP Timesync Packets */ | |
1392 | u8 handle_ptp_pkts; | |
1393 | /* If enable then innerVlan will be striped and not written to cqe */ | |
1394 | u8 silent_vlan_removal_en; | |
1395 | /* If set untagged filter (vlan0) is added to current Vport, otherwise port is | |
1396 | * marked as any-vlan | |
1397 | */ | |
1398 | u8 untagged; | |
1399 | /* Desired behavior per TX error type */ | |
1400 | struct eth_tx_err_vals tx_err_behav; | |
1401 | /* If set, ETH header padding will not inserted. placement_offset will be zero. | |
1402 | */ | |
1403 | u8 zero_placement_offset; | |
1404 | /* If set, control frames will be filtered according to MAC check. */ | |
1405 | u8 ctl_frame_mac_check_en; | |
1406 | /* If set, control frames will be filtered according to ethtype check. */ | |
1407 | u8 ctl_frame_ethtype_check_en; | |
1408 | u8 reserved[1]; | |
1409 | }; | |
1410 | ||
1411 | ||
1412 | /* | |
1413 | * Ramrod data for vport stop ramrod | |
1414 | */ | |
1415 | struct vport_stop_ramrod_data { | |
1416 | u8 vport_id; | |
1417 | u8 reserved[7]; | |
1418 | }; | |
1419 | ||
1420 | ||
1421 | /* | |
1422 | * Ramrod data for vport update ramrod | |
1423 | */ | |
1424 | struct vport_update_ramrod_data_cmn { | |
1425 | u8 vport_id; | |
1426 | u8 update_rx_active_flg /* set if rx active flag should be handled */; | |
1427 | u8 rx_active_flg /* rx active flag value */; | |
1428 | u8 update_tx_active_flg /* set if tx active flag should be handled */; | |
1429 | u8 tx_active_flg /* tx active flag value */; | |
1430 | u8 update_rx_mode_flg /* set if rx state data should be handled */; | |
1431 | u8 update_tx_mode_flg /* set if tx state data should be handled */; | |
1432 | /* set if approx. mcast data should be handled */ | |
1433 | u8 update_approx_mcast_flg; | |
1434 | u8 update_rss_flg /* set if rss data should be handled */; | |
1435 | /* set if inner_vlan_removal_en should be handled */ | |
1436 | u8 update_inner_vlan_removal_en_flg; | |
1437 | u8 inner_vlan_removal_en; | |
1438 | /* set if tpa parameters should be handled, TPA must be disable before */ | |
1439 | u8 update_tpa_param_flg; | |
1440 | u8 update_tpa_en_flg /* set if tpa enable changes */; | |
1441 | /* set if tx switching en flag should be handled */ | |
1442 | u8 update_tx_switching_en_flg; | |
1443 | u8 tx_switching_en /* tx switching en value */; | |
1444 | /* set if anti spoofing flag should be handled */ | |
1445 | u8 update_anti_spoofing_en_flg; | |
1446 | u8 anti_spoofing_en /* Anti-spoofing verification en value */; | |
1447 | /* set if handle_ptp_pkts should be handled. */ | |
1448 | u8 update_handle_ptp_pkts; | |
1449 | /* If set, the vport handles PTP Timesync Packets */ | |
1450 | u8 handle_ptp_pkts; | |
1451 | /* If set, the default Vlan enable flag is updated */ | |
1452 | u8 update_default_vlan_en_flg; | |
1453 | /* If set, the default Vlan value is forced by the FW */ | |
1454 | u8 default_vlan_en; | |
1455 | /* If set, the default Vlan value is updated */ | |
1456 | u8 update_default_vlan_flg; | |
1457 | __le16 default_vlan /* Default Vlan value to be forced by FW */; | |
1458 | /* set if accept_any_vlan should be handled */ | |
1459 | u8 update_accept_any_vlan_flg; | |
1460 | u8 accept_any_vlan /* accept_any_vlan updated value */; | |
1461 | /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled | |
1462 | * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data | |
1463 | */ | |
1464 | u8 silent_vlan_removal_en; | |
1465 | /* If set, MTU will be updated. Vport must be not active. */ | |
1466 | u8 update_mtu_flg; | |
1467 | __le16 mtu /* New MTU value. Used if update_mtu_flg are set */; | |
1468 | /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be | |
1469 | * updated | |
1470 | */ | |
1471 | u8 update_ctl_frame_checks_en_flg; | |
1472 | /* If set, control frames will be filtered according to MAC check. */ | |
1473 | u8 ctl_frame_mac_check_en; | |
1474 | /* If set, control frames will be filtered according to ethtype check. */ | |
1475 | u8 ctl_frame_ethtype_check_en; | |
1476 | u8 reserved[15]; | |
1477 | }; | |
1478 | ||
1479 | struct vport_update_ramrod_mcast { | |
1480 | __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */; | |
1481 | }; | |
1482 | ||
1483 | /* | |
1484 | * Ramrod data for vport update ramrod | |
1485 | */ | |
1486 | struct vport_update_ramrod_data { | |
1487 | /* Common data for all vport update ramrods */ | |
1488 | struct vport_update_ramrod_data_cmn common; | |
1489 | struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */; | |
1490 | struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */; | |
1491 | __le32 reserved[3]; | |
1492 | /* TPA configuration parameters */ | |
1493 | struct eth_vport_tpa_param tpa_param; | |
1494 | struct vport_update_ramrod_mcast approx_mcast; | |
1495 | struct eth_vport_rss_config rss_config /* rss config data */; | |
1496 | }; | |
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | struct E4XstormEthConnAgCtxDqExtLdPart { | |
1504 | u8 reserved0 /* cdu_validation */; | |
1505 | u8 eth_state /* state */; | |
1506 | u8 flags0; | |
1507 | /* exist_in_qm0 */ | |
1508 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 | |
1509 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 | |
1510 | /* exist_in_qm1 */ | |
1511 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 | |
1512 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 | |
1513 | /* exist_in_qm2 */ | |
1514 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 | |
1515 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 | |
1516 | /* exist_in_qm3 */ | |
1517 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 | |
1518 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 | |
1519 | /* bit4 */ | |
1520 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 | |
1521 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 | |
1522 | /* cf_array_active */ | |
1523 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 | |
1524 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 | |
1525 | /* bit6 */ | |
1526 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 | |
1527 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 | |
1528 | /* bit7 */ | |
1529 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 | |
1530 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 | |
1531 | u8 flags1; | |
1532 | /* bit8 */ | |
1533 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 | |
1534 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 | |
1535 | /* bit9 */ | |
1536 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 | |
1537 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 | |
1538 | /* bit10 */ | |
1539 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 | |
1540 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 | |
1541 | /* bit11 */ | |
1542 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 | |
1543 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 | |
1544 | /* bit12 */ | |
1545 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 | |
1546 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 | |
1547 | /* bit13 */ | |
1548 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 | |
1549 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 | |
1550 | /* bit14 */ | |
1551 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 | |
1552 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 | |
1553 | /* bit15 */ | |
1554 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 | |
1555 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 | |
1556 | u8 flags2; | |
1557 | /* timer0cf */ | |
1558 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 | |
1559 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 | |
1560 | /* timer1cf */ | |
1561 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 | |
1562 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 | |
1563 | /* timer2cf */ | |
1564 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 | |
1565 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 | |
1566 | /* timer_stop_all */ | |
1567 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 | |
1568 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 | |
1569 | u8 flags3; | |
1570 | /* cf4 */ | |
1571 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 | |
1572 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 | |
1573 | /* cf5 */ | |
1574 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 | |
1575 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 | |
1576 | /* cf6 */ | |
1577 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 | |
1578 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 | |
1579 | /* cf7 */ | |
1580 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 | |
1581 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 | |
1582 | u8 flags4; | |
1583 | /* cf8 */ | |
1584 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 | |
1585 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 | |
1586 | /* cf9 */ | |
1587 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 | |
1588 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 | |
1589 | /* cf10 */ | |
1590 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 | |
1591 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 | |
1592 | /* cf11 */ | |
1593 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 | |
1594 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 | |
1595 | u8 flags5; | |
1596 | /* cf12 */ | |
1597 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 | |
1598 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 | |
1599 | /* cf13 */ | |
1600 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 | |
1601 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 | |
1602 | /* cf14 */ | |
1603 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 | |
1604 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 | |
1605 | /* cf15 */ | |
1606 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 | |
1607 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 | |
1608 | u8 flags6; | |
1609 | /* cf16 */ | |
1610 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 | |
1611 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 | |
1612 | /* cf_array_cf */ | |
1613 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 | |
1614 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 | |
1615 | /* cf18 */ | |
1616 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 | |
1617 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 | |
1618 | /* cf19 */ | |
1619 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 | |
1620 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 | |
1621 | u8 flags7; | |
1622 | /* cf20 */ | |
1623 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 | |
1624 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 | |
1625 | /* cf21 */ | |
1626 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 | |
1627 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 | |
1628 | /* cf22 */ | |
1629 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 | |
1630 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 | |
1631 | /* cf0en */ | |
1632 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 | |
1633 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 | |
1634 | /* cf1en */ | |
1635 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 | |
1636 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 | |
1637 | u8 flags8; | |
1638 | /* cf2en */ | |
1639 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 | |
1640 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 | |
1641 | /* cf3en */ | |
1642 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 | |
1643 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 | |
1644 | /* cf4en */ | |
1645 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 | |
1646 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 | |
1647 | /* cf5en */ | |
1648 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 | |
1649 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 | |
1650 | /* cf6en */ | |
1651 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 | |
1652 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 | |
1653 | /* cf7en */ | |
1654 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 | |
1655 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 | |
1656 | /* cf8en */ | |
1657 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 | |
1658 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 | |
1659 | /* cf9en */ | |
1660 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 | |
1661 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 | |
1662 | u8 flags9; | |
1663 | /* cf10en */ | |
1664 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 | |
1665 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 | |
1666 | /* cf11en */ | |
1667 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 | |
1668 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 | |
1669 | /* cf12en */ | |
1670 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 | |
1671 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 | |
1672 | /* cf13en */ | |
1673 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 | |
1674 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 | |
1675 | /* cf14en */ | |
1676 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 | |
1677 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 | |
1678 | /* cf15en */ | |
1679 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 | |
1680 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 | |
1681 | /* cf16en */ | |
1682 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 | |
1683 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 | |
1684 | /* cf_array_cf_en */ | |
1685 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 | |
1686 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 | |
1687 | u8 flags10; | |
1688 | /* cf18en */ | |
1689 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 | |
1690 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 | |
1691 | /* cf19en */ | |
1692 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 | |
1693 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 | |
1694 | /* cf20en */ | |
1695 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 | |
1696 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 | |
1697 | /* cf21en */ | |
1698 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 | |
1699 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 | |
1700 | /* cf22en */ | |
1701 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 | |
1702 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 | |
1703 | /* cf23en */ | |
1704 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 | |
1705 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 | |
1706 | /* rule0en */ | |
1707 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 | |
1708 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 | |
1709 | /* rule1en */ | |
1710 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 | |
1711 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 | |
1712 | u8 flags11; | |
1713 | /* rule2en */ | |
1714 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 | |
1715 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 | |
1716 | /* rule3en */ | |
1717 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 | |
1718 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 | |
1719 | /* rule4en */ | |
1720 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 | |
1721 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 | |
1722 | /* rule5en */ | |
1723 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 | |
1724 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 | |
1725 | /* rule6en */ | |
1726 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 | |
1727 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 | |
1728 | /* rule7en */ | |
1729 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 | |
1730 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 | |
1731 | /* rule8en */ | |
1732 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 | |
1733 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 | |
1734 | /* rule9en */ | |
1735 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 | |
1736 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 | |
1737 | u8 flags12; | |
1738 | /* rule10en */ | |
1739 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 | |
1740 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 | |
1741 | /* rule11en */ | |
1742 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 | |
1743 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 | |
1744 | /* rule12en */ | |
1745 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 | |
1746 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 | |
1747 | /* rule13en */ | |
1748 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 | |
1749 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 | |
1750 | /* rule14en */ | |
1751 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 | |
1752 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 | |
1753 | /* rule15en */ | |
1754 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 | |
1755 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 | |
1756 | /* rule16en */ | |
1757 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 | |
1758 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 | |
1759 | /* rule17en */ | |
1760 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 | |
1761 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 | |
1762 | u8 flags13; | |
1763 | /* rule18en */ | |
1764 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 | |
1765 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 | |
1766 | /* rule19en */ | |
1767 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 | |
1768 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 | |
1769 | /* rule20en */ | |
1770 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 | |
1771 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 | |
1772 | /* rule21en */ | |
1773 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 | |
1774 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 | |
1775 | /* rule22en */ | |
1776 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 | |
1777 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 | |
1778 | /* rule23en */ | |
1779 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 | |
1780 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 | |
1781 | /* rule24en */ | |
1782 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 | |
1783 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 | |
1784 | /* rule25en */ | |
1785 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 | |
1786 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 | |
1787 | u8 flags14; | |
1788 | /* bit16 */ | |
1789 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 | |
1790 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 | |
1791 | /* bit17 */ | |
1792 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 | |
1793 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 | |
1794 | /* bit18 */ | |
1795 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 | |
1796 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 | |
1797 | /* bit19 */ | |
1798 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 | |
1799 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 | |
1800 | /* bit20 */ | |
1801 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 | |
1802 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 | |
1803 | /* bit21 */ | |
1804 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 | |
1805 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 | |
1806 | /* cf23 */ | |
1807 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 | |
1808 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 | |
1809 | u8 edpm_event_id /* byte2 */; | |
1810 | __le16 physical_q0 /* physical_q0 */; | |
1811 | __le16 e5_reserved1 /* physical_q1 */; | |
1812 | __le16 edpm_num_bds /* physical_q2 */; | |
1813 | __le16 tx_bd_cons /* word3 */; | |
1814 | __le16 tx_bd_prod /* word4 */; | |
1815 | __le16 updated_qm_pq_id /* word5 */; | |
1816 | __le16 conn_dpi /* conn_dpi */; | |
1817 | u8 byte3 /* byte3 */; | |
1818 | u8 byte4 /* byte4 */; | |
1819 | u8 byte5 /* byte5 */; | |
1820 | u8 byte6 /* byte6 */; | |
1821 | __le32 reg0 /* reg0 */; | |
1822 | __le32 reg1 /* reg1 */; | |
1823 | __le32 reg2 /* reg2 */; | |
1824 | __le32 reg3 /* reg3 */; | |
1825 | __le32 reg4 /* reg4 */; | |
1826 | }; | |
1827 | ||
1828 | ||
1829 | struct e4_mstorm_eth_conn_ag_ctx { | |
1830 | u8 byte0 /* cdu_validation */; | |
1831 | u8 byte1 /* state */; | |
1832 | u8 flags0; | |
1833 | #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ | |
1834 | #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
1835 | #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ | |
1836 | #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
1837 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ | |
1838 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 | |
1839 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ | |
1840 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 | |
1841 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ | |
1842 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
1843 | u8 flags1; | |
1844 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ | |
1845 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 | |
1846 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ | |
1847 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 | |
1848 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ | |
1849 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
1850 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ | |
1851 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
1852 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ | |
1853 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
1854 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ | |
1855 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
1856 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ | |
1857 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
1858 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ | |
1859 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
1860 | __le16 word0 /* word0 */; | |
1861 | __le16 word1 /* word1 */; | |
1862 | __le32 reg0 /* reg0 */; | |
1863 | __le32 reg1 /* reg1 */; | |
1864 | }; | |
1865 | ||
1866 | ||
1867 | ||
1868 | ||
1869 | ||
1870 | struct e4_xstorm_eth_hw_conn_ag_ctx { | |
1871 | u8 reserved0 /* cdu_validation */; | |
1872 | u8 eth_state /* state */; | |
1873 | u8 flags0; | |
1874 | /* exist_in_qm0 */ | |
1875 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
1876 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
1877 | /* exist_in_qm1 */ | |
1878 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
1879 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
1880 | /* exist_in_qm2 */ | |
1881 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
1882 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
1883 | /* exist_in_qm3 */ | |
1884 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
1885 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
1886 | /* bit4 */ | |
1887 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
1888 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
1889 | /* cf_array_active */ | |
1890 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
1891 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
1892 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ | |
1893 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
1894 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ | |
1895 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
1896 | u8 flags1; | |
1897 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ | |
1898 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
1899 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ | |
1900 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
1901 | /* bit10 */ | |
1902 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
1903 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
1904 | /* bit11 */ | |
1905 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 | |
1906 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 | |
1907 | /* bit12 */ | |
1908 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1 | |
1909 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4 | |
1910 | /* bit13 */ | |
1911 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1 | |
1912 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5 | |
1913 | /* bit14 */ | |
1914 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 | |
1915 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 | |
1916 | /* bit15 */ | |
1917 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 | |
1918 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 | |
1919 | u8 flags2; | |
1920 | /* timer0cf */ | |
1921 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 | |
1922 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 | |
1923 | /* timer1cf */ | |
1924 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 | |
1925 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 | |
1926 | /* timer2cf */ | |
1927 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 | |
1928 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 | |
1929 | /* timer_stop_all */ | |
1930 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 | |
1931 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 | |
1932 | u8 flags3; | |
1933 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ | |
1934 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 | |
1935 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ | |
1936 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 | |
1937 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ | |
1938 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 | |
1939 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ | |
1940 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 | |
1941 | u8 flags4; | |
1942 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ | |
1943 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 | |
1944 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ | |
1945 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 | |
1946 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ | |
1947 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 | |
1948 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ | |
1949 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 | |
1950 | u8 flags5; | |
1951 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ | |
1952 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 | |
1953 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ | |
1954 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 | |
1955 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ | |
1956 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 | |
1957 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ | |
1958 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 | |
1959 | u8 flags6; | |
1960 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ | |
1961 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 | |
1962 | /* cf_array_cf */ | |
1963 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 | |
1964 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 | |
1965 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ | |
1966 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 | |
1967 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ | |
1968 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 | |
1969 | u8 flags7; | |
1970 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ | |
1971 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
1972 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ | |
1973 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
1974 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ | |
1975 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
1976 | /* cf0en */ | |
1977 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 | |
1978 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 | |
1979 | /* cf1en */ | |
1980 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 | |
1981 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 | |
1982 | u8 flags8; | |
1983 | /* cf2en */ | |
1984 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 | |
1985 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 | |
1986 | /* cf3en */ | |
1987 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 | |
1988 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 | |
1989 | /* cf4en */ | |
1990 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 | |
1991 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 | |
1992 | /* cf5en */ | |
1993 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 | |
1994 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 | |
1995 | /* cf6en */ | |
1996 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 | |
1997 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 | |
1998 | /* cf7en */ | |
1999 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 | |
2000 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 | |
2001 | /* cf8en */ | |
2002 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 | |
2003 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 | |
2004 | /* cf9en */ | |
2005 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 | |
2006 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 | |
2007 | u8 flags9; | |
2008 | /* cf10en */ | |
2009 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 | |
2010 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 | |
2011 | /* cf11en */ | |
2012 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 | |
2013 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 | |
2014 | /* cf12en */ | |
2015 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 | |
2016 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 | |
2017 | /* cf13en */ | |
2018 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 | |
2019 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 | |
2020 | /* cf14en */ | |
2021 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 | |
2022 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 | |
2023 | /* cf15en */ | |
2024 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 | |
2025 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 | |
2026 | /* cf16en */ | |
2027 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 | |
2028 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 | |
2029 | /* cf_array_cf_en */ | |
2030 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 | |
2031 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 | |
2032 | u8 flags10; | |
2033 | /* cf18en */ | |
2034 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 | |
2035 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 | |
2036 | /* cf19en */ | |
2037 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 | |
2038 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 | |
2039 | /* cf20en */ | |
2040 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
2041 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
2042 | /* cf21en */ | |
2043 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
2044 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
2045 | /* cf22en */ | |
2046 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
2047 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
2048 | /* cf23en */ | |
2049 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 | |
2050 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 | |
2051 | /* rule0en */ | |
2052 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 | |
2053 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
2054 | /* rule1en */ | |
2055 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
2056 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
2057 | u8 flags11; | |
2058 | /* rule2en */ | |
2059 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 | |
2060 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
2061 | /* rule3en */ | |
2062 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
2063 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
2064 | /* rule4en */ | |
2065 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 | |
2066 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 | |
2067 | /* rule5en */ | |
2068 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
2069 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
2070 | /* rule6en */ | |
2071 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
2072 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
2073 | /* rule7en */ | |
2074 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
2075 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
2076 | /* rule8en */ | |
2077 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
2078 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
2079 | /* rule9en */ | |
2080 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
2081 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
2082 | u8 flags12; | |
2083 | /* rule10en */ | |
2084 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 | |
2085 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
2086 | /* rule11en */ | |
2087 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
2088 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
2089 | /* rule12en */ | |
2090 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
2091 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
2092 | /* rule13en */ | |
2093 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
2094 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
2095 | /* rule14en */ | |
2096 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
2097 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
2098 | /* rule15en */ | |
2099 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
2100 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
2101 | /* rule16en */ | |
2102 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
2103 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
2104 | /* rule17en */ | |
2105 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
2106 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
2107 | u8 flags13; | |
2108 | /* rule18en */ | |
2109 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 | |
2110 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
2111 | /* rule19en */ | |
2112 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
2113 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
2114 | /* rule20en */ | |
2115 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
2116 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
2117 | /* rule21en */ | |
2118 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
2119 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
2120 | /* rule22en */ | |
2121 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
2122 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
2123 | /* rule23en */ | |
2124 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
2125 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
2126 | /* rule24en */ | |
2127 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
2128 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
2129 | /* rule25en */ | |
2130 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
2131 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
2132 | u8 flags14; | |
2133 | /* bit16 */ | |
2134 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 | |
2135 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 | |
2136 | /* bit17 */ | |
2137 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 | |
2138 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 | |
2139 | /* bit18 */ | |
2140 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 | |
2141 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 | |
2142 | /* bit19 */ | |
2143 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 | |
2144 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 | |
2145 | /* bit20 */ | |
2146 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 | |
2147 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 | |
2148 | /* bit21 */ | |
2149 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
2150 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
2151 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ | |
2152 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 | |
2153 | u8 edpm_event_id /* byte2 */; | |
2154 | __le16 physical_q0 /* physical_q0 */; | |
2155 | __le16 e5_reserved1 /* physical_q1 */; | |
2156 | __le16 edpm_num_bds /* physical_q2 */; | |
2157 | __le16 tx_bd_cons /* word3 */; | |
2158 | __le16 tx_bd_prod /* word4 */; | |
2159 | __le16 updated_qm_pq_id /* word5 */; | |
2160 | __le16 conn_dpi /* conn_dpi */; | |
2161 | }; | |
2162 | ||
2163 | ||
2164 | ||
2165 | /* | |
2166 | * GFT CAM line struct | |
2167 | */ | |
2168 | struct gft_cam_line { | |
2169 | __le32 camline; | |
2170 | /* Indication if the line is valid. */ | |
2171 | #define GFT_CAM_LINE_VALID_MASK 0x1 | |
2172 | #define GFT_CAM_LINE_VALID_SHIFT 0 | |
2173 | /* Data bits, the word that compared with the profile key */ | |
2174 | #define GFT_CAM_LINE_DATA_MASK 0x3FFF | |
2175 | #define GFT_CAM_LINE_DATA_SHIFT 1 | |
2176 | /* Mask bits, indicate the bits in the data that are Dont-Care */ | |
2177 | #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF | |
2178 | #define GFT_CAM_LINE_MASK_BITS_SHIFT 15 | |
2179 | #define GFT_CAM_LINE_RESERVED1_MASK 0x7 | |
2180 | #define GFT_CAM_LINE_RESERVED1_SHIFT 29 | |
2181 | }; | |
2182 | ||
2183 | ||
2184 | /* | |
2185 | * GFT CAM line struct (for driversim use) | |
2186 | */ | |
2187 | struct gft_cam_line_mapped { | |
2188 | __le32 camline; | |
2189 | /* Indication if the line is valid. */ | |
2190 | #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 | |
2191 | #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 | |
2192 | /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ | |
2193 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 | |
2194 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 | |
2195 | /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ | |
2196 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 | |
2197 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 | |
2198 | /* use enum gft_profile_upper_protocol_type | |
2199 | * (use enum gft_profile_upper_protocol_type) | |
2200 | */ | |
2201 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF | |
2202 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 | |
2203 | /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ | |
2204 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF | |
2205 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 | |
2206 | #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF | |
2207 | #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 | |
2208 | /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ | |
2209 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 | |
2210 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 | |
2211 | /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ | |
2212 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 | |
2213 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 | |
2214 | /* use enum gft_profile_upper_protocol_type | |
2215 | * (use enum gft_profile_upper_protocol_type) | |
2216 | */ | |
2217 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF | |
2218 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 | |
2219 | /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ | |
2220 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF | |
2221 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 | |
2222 | #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF | |
2223 | #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 | |
2224 | #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 | |
2225 | #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 | |
2226 | }; | |
2227 | ||
2228 | ||
2229 | union gft_cam_line_union { | |
2230 | struct gft_cam_line cam_line; | |
2231 | struct gft_cam_line_mapped cam_line_mapped; | |
2232 | }; | |
2233 | ||
2234 | ||
2235 | /* | |
2236 | * Used in gft_profile_key: Indication for ip version | |
2237 | */ | |
2238 | enum gft_profile_ip_version { | |
2239 | GFT_PROFILE_IPV4 = 0, | |
2240 | GFT_PROFILE_IPV6 = 1, | |
2241 | MAX_GFT_PROFILE_IP_VERSION | |
2242 | }; | |
2243 | ||
2244 | ||
2245 | /* | |
2246 | * Profile key stucr fot GFT logic in Prs | |
2247 | */ | |
2248 | struct gft_profile_key { | |
2249 | __le16 profile_key; | |
2250 | /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ | |
2251 | #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 | |
2252 | #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 | |
2253 | /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ | |
2254 | #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 | |
2255 | #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 | |
2256 | /* use enum gft_profile_upper_protocol_type | |
2257 | * (use enum gft_profile_upper_protocol_type) | |
2258 | */ | |
2259 | #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF | |
2260 | #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 | |
2261 | /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ | |
2262 | #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF | |
2263 | #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 | |
2264 | #define GFT_PROFILE_KEY_PF_ID_MASK 0xF | |
2265 | #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 | |
2266 | #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 | |
2267 | #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 | |
2268 | }; | |
2269 | ||
2270 | ||
2271 | /* | |
2272 | * Used in gft_profile_key: Indication for tunnel type | |
2273 | */ | |
2274 | enum gft_profile_tunnel_type { | |
2275 | GFT_PROFILE_NO_TUNNEL = 0, | |
2276 | GFT_PROFILE_VXLAN_TUNNEL = 1, | |
2277 | GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2, | |
2278 | GFT_PROFILE_GRE_IP_TUNNEL = 3, | |
2279 | GFT_PROFILE_GENEVE_MAC_TUNNEL = 4, | |
2280 | GFT_PROFILE_GENEVE_IP_TUNNEL = 5, | |
2281 | MAX_GFT_PROFILE_TUNNEL_TYPE | |
2282 | }; | |
2283 | ||
2284 | ||
2285 | /* | |
2286 | * Used in gft_profile_key: Indication for protocol type | |
2287 | */ | |
2288 | enum gft_profile_upper_protocol_type { | |
2289 | GFT_PROFILE_ROCE_PROTOCOL = 0, | |
2290 | GFT_PROFILE_RROCE_PROTOCOL = 1, | |
2291 | GFT_PROFILE_FCOE_PROTOCOL = 2, | |
2292 | GFT_PROFILE_ICMP_PROTOCOL = 3, | |
2293 | GFT_PROFILE_ARP_PROTOCOL = 4, | |
2294 | GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5, | |
2295 | GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6, | |
2296 | GFT_PROFILE_TCP_PROTOCOL = 7, | |
2297 | GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8, | |
2298 | GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9, | |
2299 | GFT_PROFILE_UDP_PROTOCOL = 10, | |
2300 | GFT_PROFILE_USER_IP_1_INNER = 11, | |
2301 | GFT_PROFILE_USER_IP_2_OUTER = 12, | |
2302 | GFT_PROFILE_USER_ETH_1_INNER = 13, | |
2303 | GFT_PROFILE_USER_ETH_2_OUTER = 14, | |
2304 | GFT_PROFILE_RAW = 15, | |
2305 | MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE | |
2306 | }; | |
2307 | ||
2308 | ||
2309 | /* | |
2310 | * GFT RAM line struct | |
2311 | */ | |
2312 | struct gft_ram_line { | |
2313 | __le32 lo; | |
2314 | #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 | |
2315 | #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 | |
2316 | #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 | |
2317 | #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 | |
2318 | #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 | |
2319 | #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 | |
2320 | #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 | |
2321 | #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 | |
2322 | #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 | |
2323 | #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 | |
2324 | #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 | |
2325 | #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 | |
2326 | #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 | |
2327 | #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 | |
2328 | #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 | |
2329 | #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 | |
2330 | #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 | |
2331 | #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 | |
2332 | #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 | |
2333 | #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 | |
2334 | #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 | |
2335 | #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 | |
2336 | #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 | |
2337 | #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 | |
2338 | #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 | |
2339 | #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 | |
2340 | #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 | |
2341 | #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 | |
2342 | #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 | |
2343 | #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 | |
2344 | #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 | |
2345 | #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 | |
2346 | #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 | |
2347 | #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 | |
2348 | #define GFT_RAM_LINE_TTL_MASK 0x1 | |
2349 | #define GFT_RAM_LINE_TTL_SHIFT 18 | |
2350 | #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 | |
2351 | #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 | |
2352 | #define GFT_RAM_LINE_RESERVED0_MASK 0x1 | |
2353 | #define GFT_RAM_LINE_RESERVED0_SHIFT 20 | |
2354 | #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 | |
2355 | #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 | |
2356 | #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 | |
2357 | #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 | |
2358 | #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 | |
2359 | #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 | |
2360 | #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 | |
2361 | #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 | |
2362 | #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 | |
2363 | #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 | |
2364 | #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 | |
2365 | #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 | |
2366 | #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 | |
2367 | #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 | |
2368 | #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 | |
2369 | #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 | |
2370 | #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 | |
2371 | #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 | |
2372 | #define GFT_RAM_LINE_DST_PORT_MASK 0x1 | |
2373 | #define GFT_RAM_LINE_DST_PORT_SHIFT 30 | |
2374 | #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 | |
2375 | #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 | |
2376 | __le32 hi; | |
2377 | #define GFT_RAM_LINE_DSCP_MASK 0x1 | |
2378 | #define GFT_RAM_LINE_DSCP_SHIFT 0 | |
2379 | #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 | |
2380 | #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 | |
2381 | #define GFT_RAM_LINE_DST_IP_MASK 0x1 | |
2382 | #define GFT_RAM_LINE_DST_IP_SHIFT 2 | |
2383 | #define GFT_RAM_LINE_SRC_IP_MASK 0x1 | |
2384 | #define GFT_RAM_LINE_SRC_IP_SHIFT 3 | |
2385 | #define GFT_RAM_LINE_PRIORITY_MASK 0x1 | |
2386 | #define GFT_RAM_LINE_PRIORITY_SHIFT 4 | |
2387 | #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 | |
2388 | #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 | |
2389 | #define GFT_RAM_LINE_VLAN_MASK 0x1 | |
2390 | #define GFT_RAM_LINE_VLAN_SHIFT 6 | |
2391 | #define GFT_RAM_LINE_DST_MAC_MASK 0x1 | |
2392 | #define GFT_RAM_LINE_DST_MAC_SHIFT 7 | |
2393 | #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 | |
2394 | #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 | |
2395 | #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 | |
2396 | #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 | |
2397 | #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF | |
2398 | #define GFT_RAM_LINE_RESERVED1_SHIFT 10 | |
2399 | }; | |
2400 | ||
2401 | ||
2402 | /* | |
2403 | * Used in the first 2 bits for gft_ram_line: Indication for vlan mask | |
2404 | */ | |
2405 | enum gft_vlan_select { | |
2406 | INNER_PROVIDER_VLAN = 0, | |
2407 | INNER_VLAN = 1, | |
2408 | OUTER_PROVIDER_VLAN = 2, | |
2409 | OUTER_VLAN = 3, | |
2410 | MAX_GFT_VLAN_SELECT | |
2411 | }; | |
2412 | ||
2413 | ||
2414 | #endif /* __ECORE_HSI_ETH__ */ |