[ceph.git] / ceph / src / spdk / dpdk / drivers / net / qede / base / ecore_iro.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright (c) 2016 - 2018 Cavium Inc.
 * All rights reserved.
 * www.cavium.com
 */

#ifndef __IRO_H__
#define __IRO_H__

/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
/* Tstorm port statistics */
#define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
/* Tstorm ll2 port statistics */
#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) (IRO[2].base + \
	((port_id) * IRO[2].m1))
#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
/* Ustorm VF-PF Channel ready flag */
#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) (IRO[3].base + \
	((vf_id) * IRO[3].m1))
#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
/* Ustorm Final flr cleanup ack */
#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
/* Ustorm Event ring consumer */
#define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
#define USTORM_EQE_CONS_SIZE (IRO[5].size)
/* Ustorm eth queue zone */
#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) (IRO[6].base + \
	((queue_zone_id) * IRO[6].m1))
#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
/* Ustorm Common Queue ring consumer */
#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) (IRO[7].base + \
	((queue_zone_id) * IRO[7].m1))
#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
/* Xstorm common PQ info */
#define XSTORM_PQ_INFO_OFFSET(pq_id) (IRO[8].base + ((pq_id) * IRO[8].m1))
#define XSTORM_PQ_INFO_SIZE (IRO[8].size)
/* Xstorm Integration Test Data */
#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
/* Ystorm Integration Test Data */
#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
/* Pstorm Integration Test Data */
#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
/* Tstorm Integration Test Data */
#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
/* Mstorm Integration Test Data */
#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
/* Ustorm Integration Test Data */
#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base)
#define USTORM_INTEG_TEST_DATA_SIZE (IRO[14].size)
/* Xstorm overlay buffer host address */
#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[15].base)
#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[15].size)
/* Ystorm overlay buffer host address */
#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[16].base)
#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[16].size)
/* Pstorm overlay buffer host address */
#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[17].base)
#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[17].size)
/* Tstorm overlay buffer host address */
#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[18].base)
#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[18].size)
/* Mstorm overlay buffer host address */
#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[19].base)
#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[19].size)
/* Ustorm overlay buffer host address */
#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[20].base)
#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[20].size)
/* Tstorm producers */
#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) (IRO[21].base + \
	((core_rx_queue_id) * IRO[21].m1))
#define TSTORM_LL2_RX_PRODS_SIZE (IRO[21].size)
/* Tstorm LightL2 queue statistics */
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
	(IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[22].size)
/* Ustorm LiteL2 queue statistics */
#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
	(IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[23].size)
/* Pstorm LiteL2 queue statistics */
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
	(IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[24].size)
/* Mstorm queue statistics */
#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[25].base + \
	((stat_counter_id) * IRO[25].m1))
#define MSTORM_QUEUE_STAT_SIZE (IRO[25].size)
/* TPA agregation timeout in us resolution (on ASIC) */
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[26].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[26].size)
/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
 * mode.
 */
#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) (IRO[27].base + \
	((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
#define MSTORM_ETH_VF_PRODS_SIZE (IRO[27].size)
/* Mstorm ETH PF queues producers */
#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) (IRO[28].base + \
	((queue_id) * IRO[28].m1))
#define MSTORM_ETH_PF_PRODS_SIZE (IRO[28].size)
/* Mstorm pf statistics */
#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[29].base + ((pf_id) * IRO[29].m1))
#define MSTORM_ETH_PF_STAT_SIZE (IRO[29].size)
/* Ustorm queue statistics */
#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[30].base + \
	((stat_counter_id) * IRO[30].m1))
#define USTORM_QUEUE_STAT_SIZE (IRO[30].size)
/* Ustorm pf statistics */
#define USTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[31].base + ((pf_id) * IRO[31].m1))
#define USTORM_ETH_PF_STAT_SIZE (IRO[31].size)
/* Pstorm queue statistics */
#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[32].base + \
	((stat_counter_id) * IRO[32].m1))
#define PSTORM_QUEUE_STAT_SIZE (IRO[32].size)
/* Pstorm pf statistics */
#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[33].base + ((pf_id) * IRO[33].m1))
#define PSTORM_ETH_PF_STAT_SIZE (IRO[33].size)
/* Control frame's EthType configuration for TX control frame security */
#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) (IRO[34].base + \
	((ethType_id) * IRO[34].m1))
#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[34].size)
/* Tstorm last parser message */
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[35].base)
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[35].size)
/* Tstorm Eth limit Rx rate */
#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[36].base + ((pf_id) * IRO[36].m1))
#define ETH_RX_RATE_LIMIT_SIZE (IRO[36].size)
/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
 * Use eth_tstorm_rss_update_data for update.
 */
#define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) (IRO[37].base + \
	((pf_id) * IRO[37].m1))
#define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[37].size)
/* Xstorm queue zone */
#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[38].base + \
	((queue_id) * IRO[38].m1))
#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[38].size)
/* Ystorm cqe producer */
#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[39].base + \
	((rss_id) * IRO[39].m1))
#define YSTORM_TOE_CQ_PROD_SIZE (IRO[39].size)
/* Ustorm cqe producer */
#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[40].base + \
	((rss_id) * IRO[40].m1))
#define USTORM_TOE_CQ_PROD_SIZE (IRO[40].size)
/* Ustorm grq producer */
#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[41].base + \
	((pf_id) * IRO[41].m1))
#define USTORM_TOE_GRQ_PROD_SIZE (IRO[41].size)
/* Tstorm cmdq-cons of given command queue-id */
#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[42].base + \
	((cmdq_queue_id) * IRO[42].m1))
#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[42].size)
/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
 * BDqueue-id
 */
#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
	(IRO[43].base + ((storage_func_id) * IRO[43].m1) + \
	((bdq_id) * IRO[43].m2))
#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[43].size)
/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
	(IRO[44].base + ((storage_func_id) * IRO[44].m1) + \
	((bdq_id) * IRO[44].m2))
#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[44].size)
/* Tstorm iSCSI RX stats */
#define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) (IRO[45].base + \
	((storage_func_id) * IRO[45].m1))
#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[45].size)
/* Mstorm iSCSI RX stats */
#define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) (IRO[46].base + \
	((storage_func_id) * IRO[46].m1))
#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[46].size)
/* Ustorm iSCSI RX stats */
#define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) (IRO[47].base + \
	((storage_func_id) * IRO[47].m1))
#define USTORM_ISCSI_RX_STATS_SIZE (IRO[47].size)
/* Xstorm iSCSI TX stats */
#define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) (IRO[48].base + \
	((storage_func_id) * IRO[48].m1))
#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[48].size)
/* Ystorm iSCSI TX stats */
#define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) (IRO[49].base + \
	((storage_func_id) * IRO[49].m1))
#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[49].size)
/* Pstorm iSCSI TX stats */
#define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) (IRO[50].base + \
	((storage_func_id) * IRO[50].m1))
#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[50].size)
/* Tstorm FCoE RX stats */
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[51].base + \
	((pf_id) * IRO[51].m1))
#define TSTORM_FCOE_RX_STATS_SIZE (IRO[51].size)
/* Pstorm FCoE TX stats */
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[52].base + \
	((pf_id) * IRO[52].m1))
#define PSTORM_FCOE_TX_STATS_SIZE (IRO[52].size)
/* Pstorm RDMA queue statistics */
#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[53].base + \
	((rdma_stat_counter_id) * IRO[53].m1))
#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[53].size)
/* Tstorm RDMA queue statistics */
#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[54].base + \
	((rdma_stat_counter_id) * IRO[54].m1))
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[54].size)
/* Xstorm error level for assert */
#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[55].base + \
	((pf_id) * IRO[55].m1))
#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[55].size)
/* Ystorm error level for assert */
#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[56].base + \
	((pf_id) * IRO[56].m1))
#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[56].size)
/* Pstorm error level for assert */
#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[57].base + \
	((pf_id) * IRO[57].m1))
#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[57].size)
/* Tstorm error level for assert */
#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[58].base + \
	((pf_id) * IRO[58].m1))
#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[58].size)
/* Mstorm error level for assert */
#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[59].base + \
	((pf_id) * IRO[59].m1))
#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[59].size)
/* Ustorm error level for assert */
#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[60].base + \
	((pf_id) * IRO[60].m1))
#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[60].size)
/* Xstorm iWARP rxmit stats */
#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) (IRO[61].base + \
	((pf_id) * IRO[61].m1))
#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[61].size)
/* Tstorm RoCE Event Statistics */
#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) (IRO[62].base + \
	((roce_pf_id) * IRO[62].m1))
#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[62].size)
/* DCQCN Received Statistics */
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) (IRO[63].base + \
	((roce_pf_id) * IRO[63].m1))
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[63].size)
/* RoCE Error Statistics */
#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) (IRO[64].base + \
	((roce_pf_id) * IRO[64].m1))
#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[64].size)
/* DCQCN Sent Statistics */
#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) (IRO[65].base + \
	((roce_pf_id) * IRO[65].m1))
#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[65].size)
/* RoCE CQEs Statistics */
#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) (IRO[66].base + \
	((roce_pf_id) * IRO[66].m1))
#define USTORM_ROCE_CQE_STATS_SIZE (IRO[66].size)
/* Tstorm NVMf per port per producer consumer data */
#define TSTORM_NVMF_PORT_TASKPOOL_PRODUCER_CONSUMER_OFFSET(port_num_id, \
	taskpool_index) (IRO[67].base + ((port_num_id) * IRO[67].m1) + \
	((taskpool_index) * IRO[67].m2))
#define TSTORM_NVMF_PORT_TASKPOOL_PRODUCER_CONSUMER_SIZE (IRO[67].size)
/* Ustorm NVMf per port counters */
#define USTORM_NVMF_PORT_COUNTERS_OFFSET(port_num_id) (IRO[68].base + \
	((port_num_id) * IRO[68].m1))
#define USTORM_NVMF_PORT_COUNTERS_SIZE (IRO[68].size)

#endif
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
11fdf7f2 TL	2	* Copyright (c) 2016 - 2018 Cavium Inc.
7c673cae	3	* All rights reserved.
11fdf7f2	4	* www.cavium.com
7c673cae FG	5	*/
	6
	7	#ifndef __IRO_H__
	8	#define __IRO_H__
	9
	10	/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
	11	#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
	12	#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
	13	/* Tstorm port statistics */
	14	#define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
	15	#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
	16	/* Tstorm ll2 port statistics */
	17	#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) (IRO[2].base + \
	18	((port_id) * IRO[2].m1))
	19	#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
	20	/* Ustorm VF-PF Channel ready flag */
	21	#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) (IRO[3].base + \
	22	((vf_id) * IRO[3].m1))
	23	#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
	24	/* Ustorm Final flr cleanup ack */
	25	#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
	26	#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
	27	/* Ustorm Event ring consumer */
	28	#define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
	29	#define USTORM_EQE_CONS_SIZE (IRO[5].size)
	30	/* Ustorm eth queue zone */
	31	#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) (IRO[6].base + \
	32	((queue_zone_id) * IRO[6].m1))
	33	#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
	34	/* Ustorm Common Queue ring consumer */
	35	#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) (IRO[7].base + \
	36	((queue_zone_id) * IRO[7].m1))
	37	#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
f67539c2 TL	38	/* Xstorm common PQ info */
	39	#define XSTORM_PQ_INFO_OFFSET(pq_id) (IRO[8].base + ((pq_id) * IRO[8].m1))
	40	#define XSTORM_PQ_INFO_SIZE (IRO[8].size)
7c673cae	41	/* Xstorm Integration Test Data */
f67539c2 TL	42	#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
f67539c2 TL	43	#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
7c673cae	44	/* Ystorm Integration Test Data */
f67539c2 TL	45	#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
f67539c2 TL	46	#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
7c673cae	47	/* Pstorm Integration Test Data */
f67539c2 TL	48	#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
f67539c2 TL	49	#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
7c673cae	50	/* Tstorm Integration Test Data */
f67539c2 TL	51	#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
f67539c2 TL	52	#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
7c673cae	53	/* Mstorm Integration Test Data */
f67539c2 TL	54	#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
f67539c2 TL	55	#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
7c673cae	56	/* Ustorm Integration Test Data */
f67539c2 TL	57	#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base)
	58	#define USTORM_INTEG_TEST_DATA_SIZE (IRO[14].size)
	59	/* Xstorm overlay buffer host address */
	60	#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[15].base)
	61	#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[15].size)
	62	/* Ystorm overlay buffer host address */
	63	#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[16].base)
	64	#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[16].size)
	65	/* Pstorm overlay buffer host address */
	66	#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[17].base)
	67	#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[17].size)
	68	/* Tstorm overlay buffer host address */
	69	#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[18].base)
	70	#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[18].size)
	71	/* Mstorm overlay buffer host address */
	72	#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[19].base)
	73	#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[19].size)
	74	/* Ustorm overlay buffer host address */
	75	#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[20].base)
	76	#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[20].size)
7c673cae	77	/* Tstorm producers */
f67539c2 TL	78	#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) (IRO[21].base + \
	79	((core_rx_queue_id) * IRO[21].m1))
	80	#define TSTORM_LL2_RX_PRODS_SIZE (IRO[21].size)
7c673cae FG	81	/* Tstorm LightL2 queue statistics */
7c673cae FG	82	#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
f67539c2 TL	83	(IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
f67539c2 TL	84	#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[22].size)
7c673cae FG	85	/* Ustorm LiteL2 queue statistics */
7c673cae FG	86	#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
f67539c2 TL	87	(IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
f67539c2 TL	88	#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[23].size)
7c673cae FG	89	/* Pstorm LiteL2 queue statistics */
7c673cae FG	90	#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
f67539c2 TL	91	(IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
f67539c2 TL	92	#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[24].size)
7c673cae	93	/* Mstorm queue statistics */
f67539c2 TL	94	#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[25].base + \
	95	((stat_counter_id) * IRO[25].m1))
	96	#define MSTORM_QUEUE_STAT_SIZE (IRO[25].size)
	97	/* TPA agregation timeout in us resolution (on ASIC) */
	98	#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[26].base)
	99	#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[26].size)
7c673cae FG	100	/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
	101	* mode.
	102	*/
f67539c2 TL	103	#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) (IRO[27].base + \
	104	((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
	105	#define MSTORM_ETH_VF_PRODS_SIZE (IRO[27].size)
	106	/* Mstorm ETH PF queues producers */
	107	#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) (IRO[28].base + \
	108	((queue_id) * IRO[28].m1))
	109	#define MSTORM_ETH_PF_PRODS_SIZE (IRO[28].size)
7c673cae	110	/* Mstorm pf statistics */
f67539c2 TL	111	#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[29].base + ((pf_id) * IRO[29].m1))
f67539c2 TL	112	#define MSTORM_ETH_PF_STAT_SIZE (IRO[29].size)
7c673cae	113	/* Ustorm queue statistics */
f67539c2 TL	114	#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[30].base + \
	115	((stat_counter_id) * IRO[30].m1))
	116	#define USTORM_QUEUE_STAT_SIZE (IRO[30].size)
7c673cae	117	/* Ustorm pf statistics */
f67539c2 TL	118	#define USTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[31].base + ((pf_id) * IRO[31].m1))
f67539c2 TL	119	#define USTORM_ETH_PF_STAT_SIZE (IRO[31].size)
7c673cae	120	/* Pstorm queue statistics */
f67539c2 TL	121	#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[32].base + \
	122	((stat_counter_id) * IRO[32].m1))
	123	#define PSTORM_QUEUE_STAT_SIZE (IRO[32].size)
7c673cae	124	/* Pstorm pf statistics */
f67539c2 TL	125	#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[33].base + ((pf_id) * IRO[33].m1))
f67539c2 TL	126	#define PSTORM_ETH_PF_STAT_SIZE (IRO[33].size)
7c673cae	127	/* Control frame's EthType configuration for TX control frame security */
f67539c2 TL	128	#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) (IRO[34].base + \
	129	((ethType_id) * IRO[34].m1))
	130	#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[34].size)
7c673cae	131	/* Tstorm last parser message */
f67539c2 TL	132	#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[35].base)
f67539c2 TL	133	#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[35].size)
7c673cae	134	/* Tstorm Eth limit Rx rate */
f67539c2 TL	135	#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[36].base + ((pf_id) * IRO[36].m1))
f67539c2 TL	136	#define ETH_RX_RATE_LIMIT_SIZE (IRO[36].size)
9f95a23c TL	137	/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
	138	* Use eth_tstorm_rss_update_data for update.
	139	*/
f67539c2 TL	140	#define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) (IRO[37].base + \
	141	((pf_id) * IRO[37].m1))
	142	#define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[37].size)
7c673cae	143	/* Xstorm queue zone */
f67539c2 TL	144	#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[38].base + \
	145	((queue_id) * IRO[38].m1))
	146	#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[38].size)
7c673cae	147	/* Ystorm cqe producer */
f67539c2 TL	148	#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[39].base + \
	149	((rss_id) * IRO[39].m1))
	150	#define YSTORM_TOE_CQ_PROD_SIZE (IRO[39].size)
9f95a23c	151	/* Ustorm cqe producer */
f67539c2 TL	152	#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[40].base + \
	153	((rss_id) * IRO[40].m1))
	154	#define USTORM_TOE_CQ_PROD_SIZE (IRO[40].size)
7c673cae	155	/* Ustorm grq producer */
f67539c2 TL	156	#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[41].base + \
	157	((pf_id) * IRO[41].m1))
	158	#define USTORM_TOE_GRQ_PROD_SIZE (IRO[41].size)
7c673cae	159	/* Tstorm cmdq-cons of given command queue-id */
f67539c2 TL	160	#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[42].base + \
	161	((cmdq_queue_id) * IRO[42].m1))
	162	#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[42].size)
7c673cae FG	163	/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
	164	* BDqueue-id
	165	*/
f67539c2 TL	166	#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
	167	(IRO[43].base + ((storage_func_id) * IRO[43].m1) + \
	168	((bdq_id) * IRO[43].m2))
	169	#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[43].size)
9f95a23c	170	/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
f67539c2 TL	171	#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
	172	(IRO[44].base + ((storage_func_id) * IRO[44].m1) + \
	173	((bdq_id) * IRO[44].m2))
	174	#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[44].size)
7c673cae	175	/* Tstorm iSCSI RX stats */
f67539c2 TL	176	#define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) (IRO[45].base + \
	177	((storage_func_id) * IRO[45].m1))
	178	#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[45].size)
9f95a23c	179	/* Mstorm iSCSI RX stats */
f67539c2 TL	180	#define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) (IRO[46].base + \
	181	((storage_func_id) * IRO[46].m1))
	182	#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[46].size)
9f95a23c	183	/* Ustorm iSCSI RX stats */
f67539c2 TL	184	#define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) (IRO[47].base + \
	185	((storage_func_id) * IRO[47].m1))
	186	#define USTORM_ISCSI_RX_STATS_SIZE (IRO[47].size)
9f95a23c	187	/* Xstorm iSCSI TX stats */
f67539c2 TL	188	#define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) (IRO[48].base + \
	189	((storage_func_id) * IRO[48].m1))
	190	#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[48].size)
9f95a23c	191	/* Ystorm iSCSI TX stats */
f67539c2 TL	192	#define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) (IRO[49].base + \
	193	((storage_func_id) * IRO[49].m1))
	194	#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[49].size)
9f95a23c	195	/* Pstorm iSCSI TX stats */
f67539c2 TL	196	#define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) (IRO[50].base + \
	197	((storage_func_id) * IRO[50].m1))
	198	#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[50].size)
9f95a23c	199	/* Tstorm FCoE RX stats */
f67539c2 TL	200	#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[51].base + \
	201	((pf_id) * IRO[51].m1))
	202	#define TSTORM_FCOE_RX_STATS_SIZE (IRO[51].size)
9f95a23c	203	/* Pstorm FCoE TX stats */
f67539c2 TL	204	#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[52].base + \
	205	((pf_id) * IRO[52].m1))
	206	#define PSTORM_FCOE_TX_STATS_SIZE (IRO[52].size)
7c673cae	207	/* Pstorm RDMA queue statistics */
f67539c2 TL	208	#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[53].base + \
	209	((rdma_stat_counter_id) * IRO[53].m1))
	210	#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[53].size)
9f95a23c	211	/* Tstorm RDMA queue statistics */
f67539c2 TL	212	#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[54].base + \
	213	((rdma_stat_counter_id) * IRO[54].m1))
	214	#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[54].size)
9f95a23c	215	/* Xstorm error level for assert */
f67539c2 TL	216	#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[55].base + \
	217	((pf_id) * IRO[55].m1))
	218	#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[55].size)
9f95a23c	219	/* Ystorm error level for assert */
f67539c2 TL	220	#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[56].base + \
	221	((pf_id) * IRO[56].m1))
	222	#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[56].size)
9f95a23c	223	/* Pstorm error level for assert */
f67539c2 TL	224	#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[57].base + \
	225	((pf_id) * IRO[57].m1))
	226	#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[57].size)
9f95a23c	227	/* Tstorm error level for assert */
f67539c2 TL	228	#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[58].base + \
	229	((pf_id) * IRO[58].m1))
	230	#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[58].size)
9f95a23c	231	/* Mstorm error level for assert */
f67539c2 TL	232	#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[59].base + \
	233	((pf_id) * IRO[59].m1))
	234	#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[59].size)
9f95a23c	235	/* Ustorm error level for assert */
f67539c2 TL	236	#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[60].base + \
	237	((pf_id) * IRO[60].m1))
	238	#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[60].size)
11fdf7f2	239	/* Xstorm iWARP rxmit stats */
f67539c2 TL	240	#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) (IRO[61].base + \
	241	((pf_id) * IRO[61].m1))
	242	#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[61].size)
11fdf7f2	243	/* Tstorm RoCE Event Statistics */
f67539c2 TL	244	#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) (IRO[62].base + \
	245	((roce_pf_id) * IRO[62].m1))
	246	#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[62].size)
11fdf7f2	247	/* DCQCN Received Statistics */
f67539c2 TL	248	#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) (IRO[63].base + \
	249	((roce_pf_id) * IRO[63].m1))
	250	#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[63].size)
9f95a23c	251	/* RoCE Error Statistics */
f67539c2 TL	252	#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) (IRO[64].base + \
	253	((roce_pf_id) * IRO[64].m1))
	254	#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[64].size)
11fdf7f2	255	/* DCQCN Sent Statistics */
f67539c2 TL	256	#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) (IRO[65].base + \
	257	((roce_pf_id) * IRO[65].m1))
	258	#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[65].size)
9f95a23c	259	/* RoCE CQEs Statistics */
f67539c2 TL	260	#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) (IRO[66].base + \
	261	((roce_pf_id) * IRO[66].m1))
	262	#define USTORM_ROCE_CQE_STATS_SIZE (IRO[66].size)
	263	/* Tstorm NVMf per port per producer consumer data */
	264	#define TSTORM_NVMF_PORT_TASKPOOL_PRODUCER_CONSUMER_OFFSET(port_num_id, \
	265	taskpool_index) (IRO[67].base + ((port_num_id) * IRO[67].m1) + \
	266	((taskpool_index) * IRO[67].m2))
	267	#define TSTORM_NVMF_PORT_TASKPOOL_PRODUCER_CONSUMER_SIZE (IRO[67].size)
	268	/* Ustorm NVMf per port counters */
	269	#define USTORM_NVMF_PORT_COUNTERS_OFFSET(port_num_id) (IRO[68].base + \
	270	((port_num_id) * IRO[68].m1))
	271	#define USTORM_NVMF_PORT_COUNTERS_SIZE (IRO[68].size)
7c673cae	272
f67539c2	273	#endif