[ceph.git] / ceph / src / spdk / dpdk / drivers / net / qede / base / ecore_sp_commands.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright (c) 2016 - 2018 Cavium Inc.
 * All rights reserved.
 * www.cavium.com
 */

#ifndef __ECORE_SP_COMMANDS_H__
#define __ECORE_SP_COMMANDS_H__

#include "ecore.h"
#include "ecore_spq.h"
#include "ecore_sp_api.h"

#define ECORE_SP_EQ_COMPLETION  0x01
#define ECORE_SP_CQE_COMPLETION 0x02

struct ecore_sp_init_data {
	/* The CID and FID aren't necessarily derived from hwfn,
	 * e.g., in IOV scenarios. CID might defer between SPQ and
	 * other elements.
	 */
	u32				cid;
	u16				opaque_fid;

	/* Information regarding operation upon sending & completion */
	enum spq_mode			comp_mode;
	struct ecore_spq_comp_cb	*p_comp_data;

};

/**
 * @brief Acquire and initialize and SPQ entry for a given ramrod.
 *
 * @param p_hwfn
 * @param pp_ent - will be filled with a pointer to an entry upon success
 * @param cmd - dependent upon protocol
 * @param protocol
 * @param p_data - various configuration required for ramrod
 *
 * @return ECORE_SUCCESS upon success, otherwise failure.
 */
enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
					   struct ecore_spq_entry **pp_ent,
					   u8 cmd,
					   u8 protocol,
					   struct ecore_sp_init_data *p_data);

/**
 * @brief ecore_sp_pf_start - PF Function Start Ramrod
 *
 * This ramrod is sent to initialize a physical function (PF). It will
 * configure the function related parameters and write its completion to the
 * event ring specified in the parameters.
 *
 * Ramrods complete on the common event ring for the PF. This ring is
 * allocated by the driver on host memory and its parameters are written
 * to the internal RAM of the UStorm by the Function Start Ramrod.
 *
 * @param p_hwfn
 * @param p_ptt
 * @param p_tunn - pf start tunneling configuration
 * @param allow_npar_tx_switch - npar tx switching to be used
 *	  for vports configured for tx-switching.
 *
 * @return enum _ecore_status_t
 */

enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
				       struct ecore_ptt *p_ptt,
				       struct ecore_tunnel_info *p_tunn,
				       bool allow_npar_tx_switch);

/**
 * @brief ecore_sp_pf_update - PF Function Update Ramrod
 *
 * This ramrod updates function-related parameters. Every parameter can be
 * updated independently, according to configuration flags.
 *
 * @note Final phase API.
 *
 * @param p_hwfn
 *
 * @return enum _ecore_status_t
 */

enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn);

/**
 * @brief ecore_sp_pf_stop - PF Function Stop Ramrod
 *
 * This ramrod is sent to close a Physical Function (PF). It is the last ramrod
 * sent and the last completion written to the PFs Event Ring. This ramrod also
 * deletes the context for the Slowhwfn connection on this PF.
 *
 * @note Not required for first packet.
 *
 * @param p_hwfn
 *
 * @return enum _ecore_status_t
 */

enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn);

/**
 * @brief ecore_sp_heartbeat_ramrod - Send empty Ramrod
 *
 * @param p_hwfn
 *
 * @return enum _ecore_status_t
 */

enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn);

struct ecore_rl_update_params {
	u8 qcn_update_param_flg;
	u8 dcqcn_update_param_flg;
	u8 rl_init_flg;
	u8 rl_start_flg;
	u8 rl_stop_flg;
	u8 rl_id_first;
	u8 rl_id_last;
	u8 dcqcn_reset_alpha_on_idle;
	u8 rl_bc_stage_th;
	u8 rl_timer_stage_th;
	u8 rl_dc_qcn_flg; /* If set, RL will used for DCQCN */
	u32 rl_bc_rate; /* Byte Counter Limit */
	u32 rl_max_rate; /* Maximum rate in Mbps resolution */
	u32 rl_r_ai; /* Active increase rate */
	u32 rl_r_hai; /* Hyper active increase rate */
	u32 dcqcn_gd; /* DCQCN Alpha update gain */
	u32 dcqcn_k_us; /* DCQCN Alpha update interval */
	u32 dcqcn_timeuot_us;
	u32 qcn_timeuot_us;
};

/**
 * @brief ecore_sp_rl_update - Update rate limiters
 *
 * @param p_hwfn
 * @param params
 *
 * @return enum _ecore_status_t
 */
enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
					struct ecore_rl_update_params *params);

/**
 * @brief ecore_sp_pf_update_stag - PF STAG value update Ramrod
 *
 * @param p_hwfn
 *
 * @return enum _ecore_status_t
 */

enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn);

/**
 * @brief ecore_sp_pf_update_ufp - PF ufp update Ramrod
 *
 * @param p_hwfn
 *
 * @return enum _ecore_status_t
 */
enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn);

#endif /*__ECORE_SP_COMMANDS_H__*/
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
11fdf7f2 TL	2	* Copyright (c) 2016 - 2018 Cavium Inc.
7c673cae	3	* All rights reserved.
11fdf7f2	4	* www.cavium.com
7c673cae FG	5	*/
	6
	7	#ifndef __ECORE_SP_COMMANDS_H__
	8	#define __ECORE_SP_COMMANDS_H__
	9
	10	#include "ecore.h"
	11	#include "ecore_spq.h"
	12	#include "ecore_sp_api.h"
	13
	14	#define ECORE_SP_EQ_COMPLETION 0x01
	15	#define ECORE_SP_CQE_COMPLETION 0x02
	16
	17	struct ecore_sp_init_data {
	18	/* The CID and FID aren't necessarily derived from hwfn,
	19	* e.g., in IOV scenarios. CID might defer between SPQ and
	20	* other elements.
	21	*/
	22	u32 cid;
	23	u16 opaque_fid;
	24
	25	/* Information regarding operation upon sending & completion */
	26	enum spq_mode comp_mode;
	27	struct ecore_spq_comp_cb *p_comp_data;
	28
	29	};
	30
	31	/**
	32	* @brief Acquire and initialize and SPQ entry for a given ramrod.
	33	*
	34	* @param p_hwfn
	35	* @param pp_ent - will be filled with a pointer to an entry upon success
	36	* @param cmd - dependent upon protocol
	37	* @param protocol
	38	* @param p_data - various configuration required for ramrod
	39	*
	40	* @return ECORE_SUCCESS upon success, otherwise failure.
	41	*/
	42	enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
	43	struct ecore_spq_entry **pp_ent,
	44	u8 cmd,
	45	u8 protocol,
	46	struct ecore_sp_init_data *p_data);
	47
	48	/**
	49	* @brief ecore_sp_pf_start - PF Function Start Ramrod
	50	*
	51	* This ramrod is sent to initialize a physical function (PF). It will
	52	* configure the function related parameters and write its completion to the
	53	* event ring specified in the parameters.
	54	*
	55	* Ramrods complete on the common event ring for the PF. This ring is
	56	* allocated by the driver on host memory and its parameters are written
	57	* to the internal RAM of the UStorm by the Function Start Ramrod.
	58	*
	59	* @param p_hwfn
11fdf7f2	60	* @param p_ptt
7c673cae	61	* @param p_tunn - pf start tunneling configuration
7c673cae FG	62	* @param allow_npar_tx_switch - npar tx switching to be used
	63	* for vports configured for tx-switching.
	64	*
	65	* @return enum _ecore_status_t
	66	*/
	67
	68	enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
11fdf7f2 TL	69	struct ecore_ptt *p_ptt,
11fdf7f2 TL	70	struct ecore_tunnel_info *p_tunn,
7c673cae FG	71	bool allow_npar_tx_switch);
7c673cae FG	72
7c673cae FG	73	/**
	74	* @brief ecore_sp_pf_update - PF Function Update Ramrod
	75	*
	76	* This ramrod updates function-related parameters. Every parameter can be
	77	* updated independently, according to configuration flags.
	78	*
	79	* @note Final phase API.
	80	*
	81	* @param p_hwfn
	82	*
	83	* @return enum _ecore_status_t
	84	*/
	85
11fdf7f2	86	enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn);
7c673cae FG	87
	88	/**
	89	* @brief ecore_sp_pf_stop - PF Function Stop Ramrod
	90	*
	91	* This ramrod is sent to close a Physical Function (PF). It is the last ramrod
	92	* sent and the last completion written to the PFs Event Ring. This ramrod also
	93	* deletes the context for the Slowhwfn connection on this PF.
	94	*
	95	* @note Not required for first packet.
	96	*
	97	* @param p_hwfn
	98	*
	99	* @return enum _ecore_status_t
	100	*/
	101
	102	enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn);
	103
	104	/**
	105	* @brief ecore_sp_heartbeat_ramrod - Send empty Ramrod
	106	*
	107	* @param p_hwfn
	108	*
	109	* @return enum _ecore_status_t
	110	*/
	111
	112	enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn);
	113
	114	struct ecore_rl_update_params {
	115	u8 qcn_update_param_flg;
	116	u8 dcqcn_update_param_flg;
	117	u8 rl_init_flg;
	118	u8 rl_start_flg;
	119	u8 rl_stop_flg;
	120	u8 rl_id_first;
	121	u8 rl_id_last;
9f95a23c TL	122	u8 dcqcn_reset_alpha_on_idle;
	123	u8 rl_bc_stage_th;
	124	u8 rl_timer_stage_th;
7c673cae FG	125	u8 rl_dc_qcn_flg; /* If set, RL will used for DCQCN */
7c673cae FG	126	u32 rl_bc_rate; /* Byte Counter Limit */
11fdf7f2 TL	127	u32 rl_max_rate; /* Maximum rate in Mbps resolution */
	128	u32 rl_r_ai; /* Active increase rate */
	129	u32 rl_r_hai; /* Hyper active increase rate */
	130	u32 dcqcn_gd; /* DCQCN Alpha update gain */
7c673cae FG	131	u32 dcqcn_k_us; /* DCQCN Alpha update interval */
	132	u32 dcqcn_timeuot_us;
	133	u32 qcn_timeuot_us;
	134	};
	135
	136	/**
	137	* @brief ecore_sp_rl_update - Update rate limiters
	138	*
	139	* @param p_hwfn
	140	* @param params
	141	*
	142	* @return enum _ecore_status_t
	143	*/
	144	enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
	145	struct ecore_rl_update_params *params);
	146
11fdf7f2 TL	147	/**
	148	* @brief ecore_sp_pf_update_stag - PF STAG value update Ramrod
	149	*
	150	* @param p_hwfn
	151	*
	152	* @return enum _ecore_status_t
	153	*/
	154
	155	enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn);
	156
	157	/**
	158	* @brief ecore_sp_pf_update_ufp - PF ufp update Ramrod
	159	*
	160	* @param p_hwfn
	161	*
	162	* @return enum _ecore_status_t
	163	*/
	164	enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn);
	165
7c673cae	166	#endif /__ECORE_SP_COMMANDS_H__/