[ceph.git] / ceph / src / spdk / dpdk / drivers / net / qede / qede_ethdev.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright (c) 2016 - 2018 Cavium Inc.
 * All rights reserved.
 * www.cavium.com
 */


#ifndef _QEDE_ETHDEV_H_
#define _QEDE_ETHDEV_H_

#include <sys/queue.h>

#include <rte_ether.h>
#include <rte_ethdev_driver.h>
#include <rte_ethdev_pci.h>
#include <rte_dev.h>
#include <rte_ip.h>

/* ecore includes */
#include "base/bcm_osal.h"
#include "base/ecore.h"
#include "base/ecore_dev_api.h"
#include "base/ecore_l2_api.h"
#include "base/ecore_vf_api.h"
#include "base/ecore_hsi_common.h"
#include "base/ecore_int_api.h"
#include "base/ecore_chain.h"
#include "base/ecore_status.h"
#include "base/ecore_hsi_eth.h"
#include "base/ecore_iov_api.h"
#include "base/ecore_cxt.h"
#include "base/nvm_cfg.h"
#include "base/ecore_sp_commands.h"
#include "base/ecore_l2.h"
#include "base/ecore_vf.h"

#include "qede_logs.h"
#include "qede_if.h"
#include "qede_rxtx.h"

#define qede_stringify1(x...)		#x
#define qede_stringify(x...)		qede_stringify1(x)

/* Driver versions */
#define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE /* 128 */
#define QEDE_PMD_VER_PREFIX		"QEDE PMD"
#define QEDE_PMD_VERSION_MAJOR		2
#define QEDE_PMD_VERSION_MINOR	        11
#define QEDE_PMD_VERSION_REVISION       3
#define QEDE_PMD_VERSION_PATCH	        1

#define QEDE_PMD_DRV_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "."     \
			     qede_stringify(QEDE_PMD_VERSION_MINOR) "."     \
			     qede_stringify(QEDE_PMD_VERSION_REVISION) "."  \
			     qede_stringify(QEDE_PMD_VERSION_PATCH)

#define QEDE_PMD_BASE_VERSION qede_stringify(ECORE_MAJOR_VERSION) "."       \
			      qede_stringify(ECORE_MINOR_VERSION) "."       \
			      qede_stringify(ECORE_REVISION_VERSION) "."    \
			      qede_stringify(ECORE_ENGINEERING_VERSION)

#define QEDE_PMD_FW_VERSION qede_stringify(FW_MAJOR_VERSION) "."            \
			    qede_stringify(FW_MINOR_VERSION) "."            \
			    qede_stringify(FW_REVISION_VERSION) "."         \
			    qede_stringify(FW_ENGINEERING_VERSION)

#define QEDE_RSS_INDIR_INITED     (1 << 0)
#define QEDE_RSS_KEY_INITED       (1 << 1)
#define QEDE_RSS_CAPS_INITED      (1 << 2)

#define QEDE_MAX_RSS_CNT(edev)  ((edev)->dev_info.num_queues)
#define QEDE_MAX_TSS_CNT(edev)  ((edev)->dev_info.num_queues * \
					(edev)->dev_info.num_tc)

#define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues)
#define QEDE_RSS_COUNT(dev) ((dev)->data->nb_rx_queues)
#define QEDE_TSS_COUNT(dev) ((dev)->data->nb_tx_queues)

#define QEDE_DUPLEX_FULL	1
#define QEDE_DUPLEX_HALF	2
#define QEDE_DUPLEX_UNKNOWN     0xff

#define QEDE_SUPPORTED_AUTONEG (1 << 6)
#define QEDE_SUPPORTED_PAUSE   (1 << 13)

#define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private)

#define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev)

#define QEDE_INIT(eth_dev) {					\
	struct qede_dev *qdev = eth_dev->data->dev_private;	\
	struct ecore_dev *edev = &qdev->edev;			\
}

/************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/
#define PCI_VENDOR_ID_QLOGIC                   0x1077

#define CHIP_NUM_57980E                        0x1634
#define CHIP_NUM_57980S                        0x1629
#define CHIP_NUM_VF                            0x1630
#define CHIP_NUM_57980S_40                     0x1634
#define CHIP_NUM_57980S_25                     0x1656
#define CHIP_NUM_57980S_IOV                    0x1664
#define CHIP_NUM_57980S_100                    0x1644
#define CHIP_NUM_57980S_50                     0x1654
#define CHIP_NUM_AH_50G	                       0x8070
#define CHIP_NUM_AH_10G                        0x8071
#define CHIP_NUM_AH_40G			       0x8072
#define CHIP_NUM_AH_25G			       0x8073
#define CHIP_NUM_AH_IOV			       0x8090

#define PCI_DEVICE_ID_QLOGIC_NX2_57980E        CHIP_NUM_57980E
#define PCI_DEVICE_ID_QLOGIC_NX2_57980S        CHIP_NUM_57980S
#define PCI_DEVICE_ID_QLOGIC_NX2_VF            CHIP_NUM_VF
#define PCI_DEVICE_ID_QLOGIC_57980S_40         CHIP_NUM_57980S_40
#define PCI_DEVICE_ID_QLOGIC_57980S_25         CHIP_NUM_57980S_25
#define PCI_DEVICE_ID_QLOGIC_57980S_IOV        CHIP_NUM_57980S_IOV
#define PCI_DEVICE_ID_QLOGIC_57980S_100        CHIP_NUM_57980S_100
#define PCI_DEVICE_ID_QLOGIC_57980S_50         CHIP_NUM_57980S_50
#define PCI_DEVICE_ID_QLOGIC_AH_50G            CHIP_NUM_AH_50G
#define PCI_DEVICE_ID_QLOGIC_AH_10G            CHIP_NUM_AH_10G
#define PCI_DEVICE_ID_QLOGIC_AH_40G            CHIP_NUM_AH_40G
#define PCI_DEVICE_ID_QLOGIC_AH_25G            CHIP_NUM_AH_25G
#define PCI_DEVICE_ID_QLOGIC_AH_IOV            CHIP_NUM_AH_IOV


extern char qede_fw_file[];

/* Number of PF connections - 32 RX + 32 TX */
#define QEDE_PF_NUM_CONNS		(64)

/* Maximum number of flowdir filters */
#define QEDE_RFS_MAX_FLTR		(256)

#define QEDE_MAX_MCAST_FILTERS		(64)

enum qed_filter_rx_mode_type {
	QED_FILTER_RX_MODE_TYPE_REGULAR,
	QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC,
	QED_FILTER_RX_MODE_TYPE_PROMISC,
};

struct qede_vlan_entry {
	SLIST_ENTRY(qede_vlan_entry) list;
	uint16_t vid;
};

struct qede_mcast_entry {
	struct rte_ether_addr mac;
	SLIST_ENTRY(qede_mcast_entry) list;
};

struct qede_ucast_entry {
	struct rte_ether_addr mac;
	uint16_t vlan;
	uint16_t vni;
	SLIST_ENTRY(qede_ucast_entry) list;
};

#ifndef IPV6_ADDR_LEN
#define IPV6_ADDR_LEN				(16)
#endif

struct qede_arfs_tuple {
	union {
		uint32_t src_ipv4;
		uint8_t src_ipv6[IPV6_ADDR_LEN];
	};

	union {
		uint32_t dst_ipv4;
		uint8_t dst_ipv6[IPV6_ADDR_LEN];
	};

	uint16_t	src_port;
	uint16_t	dst_port;
	uint16_t	eth_proto;
	uint8_t		ip_proto;

	/* Describe filtering mode needed for this kind of filter */
	enum ecore_filter_config_mode mode;
};

struct qede_arfs_entry {
	uint32_t soft_id; /* unused for now */
	uint16_t pkt_len; /* actual packet length to match */
	uint16_t rx_queue; /* queue to be steered to */
	bool is_drop; /* drop action */
	const struct rte_memzone *mz; /* mz used to hold L2 frame */
	struct qede_arfs_tuple tuple;
	SLIST_ENTRY(qede_arfs_entry) list;
};

/* Opaque handle for rte flow managed by PMD */
struct rte_flow {
	struct qede_arfs_entry entry;
};

struct qede_arfs_info {
	struct ecore_arfs_config_params arfs;
	uint16_t filter_count;
	SLIST_HEAD(arfs_list_head, qede_arfs_entry)arfs_list_head;
};

/* IANA assigned default UDP ports for encapsulation protocols */
#define QEDE_VXLAN_DEF_PORT			(4789)
#define QEDE_GENEVE_DEF_PORT			(6081)

struct qede_tunn_params {
	bool enable;
	uint16_t num_filters;
	uint16_t filter_type;
	uint16_t udp_port;
};

/*
 *  Structure to store private data for each port.
 */
struct qede_dev {
	struct ecore_dev edev;
	const struct qed_eth_ops *ops;
	struct qed_dev_eth_info dev_info;
	struct ecore_sb_info *sb_array;
	struct qede_fastpath *fp_array;
	struct qede_fastpath_cmt *fp_array_cmt;
	uint16_t mtu;
	uint16_t new_mtu;
	bool enable_tx_switching;
	bool rss_enable;
	struct rte_eth_rss_conf rss_conf;
	uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];
	uint64_t rss_hf;
	uint8_t rss_key_len;
	bool enable_lro;
	uint8_t num_rx_queues;
	uint8_t num_tx_queues;
	SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head;
	uint16_t configured_vlans;
	bool accept_any_vlan;
	struct rte_ether_addr primary_mac;
	SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head;
	uint16_t num_mc_addr;
	SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head;
	uint16_t num_uc_addr;
	bool handle_hw_err;
	struct qede_tunn_params vxlan;
	struct qede_tunn_params geneve;
	struct qede_tunn_params ipgre;
	struct qede_arfs_info arfs_info;
	bool vlan_strip_flg;
	char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
	bool vport_started;
	int vlan_offload_mask;
	void *ethdev;
};

static inline void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
{
	memset(ucast, 0, sizeof(struct ecore_filter_ucast));
	ucast->is_rx_filter = true;
	ucast->is_tx_filter = true;
	/* ucast->assert_on_error = true; - For debug */
}


/* Non-static functions */
int qede_config_rss(struct rte_eth_dev *eth_dev);

int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
			 struct rte_eth_rss_conf *rss_conf);

int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
			 struct rte_eth_rss_reta_entry64 *reta_conf,
			 uint16_t reta_size);

int qed_fill_eth_dev_info(struct ecore_dev *edev,
				 struct qed_dev_eth_info *info);
int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up);

int qede_link_update(struct rte_eth_dev *eth_dev,
		     __rte_unused int wait_to_complete);

int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type,
			 enum rte_filter_op op, void *arg);

int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev,
			    enum rte_filter_op filter_op, void *arg);

int qede_check_fdir_support(struct rte_eth_dev *eth_dev);

uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev,
				 struct rte_eth_fdir_filter *fdir,
				 void *buff,
				 struct ecore_arfs_config_params *params);

void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev);

int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg);

int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu);

int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg);
int qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
			  struct rte_eth_udp_tunnel *tunnel_udp);
int qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
			  struct rte_eth_udp_tunnel *tunnel_udp);

enum _ecore_status_t
qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
		 bool add);
void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg);
int qede_ucast_filter(struct rte_eth_dev *eth_dev,
		      struct ecore_filter_ucast *ucast,
		      bool add);
#endif /* _QEDE_ETHDEV_H_ */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	* Copyright (c) 2016 - 2018 Cavium Inc.
	3	* All rights reserved.
	4	* www.cavium.com
	5	*/
	6
	7
	8	#ifndef _QEDE_ETHDEV_H_
	9	#define _QEDE_ETHDEV_H_
	10
	11	#include <sys/queue.h>
	12
	13	#include <rte_ether.h>
	14	#include <rte_ethdev_driver.h>
	15	#include <rte_ethdev_pci.h>
	16	#include <rte_dev.h>
	17	#include <rte_ip.h>
	18
	19	/* ecore includes */
	20	#include "base/bcm_osal.h"
	21	#include "base/ecore.h"
	22	#include "base/ecore_dev_api.h"
	23	#include "base/ecore_l2_api.h"
	24	#include "base/ecore_vf_api.h"
	25	#include "base/ecore_hsi_common.h"
	26	#include "base/ecore_int_api.h"
	27	#include "base/ecore_chain.h"
	28	#include "base/ecore_status.h"
	29	#include "base/ecore_hsi_eth.h"
	30	#include "base/ecore_iov_api.h"
	31	#include "base/ecore_cxt.h"
	32	#include "base/nvm_cfg.h"
	33	#include "base/ecore_sp_commands.h"
	34	#include "base/ecore_l2.h"
	35	#include "base/ecore_vf.h"
	36
	37	#include "qede_logs.h"
	38	#include "qede_if.h"
	39	#include "qede_rxtx.h"
	40
	41	#define qede_stringify1(x...) #x
	42	#define qede_stringify(x...) qede_stringify1(x)
	43
	44	/* Driver versions */
f67539c2	45	#define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE /* 128 */
11fdf7f2 TL	46	#define QEDE_PMD_VER_PREFIX "QEDE PMD"
11fdf7f2 TL	47	#define QEDE_PMD_VERSION_MAJOR 2
f67539c2 TL	48	#define QEDE_PMD_VERSION_MINOR 11
f67539c2 TL	49	#define QEDE_PMD_VERSION_REVISION 3
11fdf7f2 TL	50	#define QEDE_PMD_VERSION_PATCH 1
11fdf7f2 TL	51
f67539c2 TL	52	#define QEDE_PMD_DRV_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \
	53	qede_stringify(QEDE_PMD_VERSION_MINOR) "." \
	54	qede_stringify(QEDE_PMD_VERSION_REVISION) "." \
	55	qede_stringify(QEDE_PMD_VERSION_PATCH)
11fdf7f2	56
f67539c2 TL	57	#define QEDE_PMD_BASE_VERSION qede_stringify(ECORE_MAJOR_VERSION) "." \
	58	qede_stringify(ECORE_MINOR_VERSION) "." \
	59	qede_stringify(ECORE_REVISION_VERSION) "." \
	60	qede_stringify(ECORE_ENGINEERING_VERSION)
11fdf7f2	61
f67539c2 TL	62	#define QEDE_PMD_FW_VERSION qede_stringify(FW_MAJOR_VERSION) "." \
	63	qede_stringify(FW_MINOR_VERSION) "." \
	64	qede_stringify(FW_REVISION_VERSION) "." \
	65	qede_stringify(FW_ENGINEERING_VERSION)
11fdf7f2 TL	66
	67	#define QEDE_RSS_INDIR_INITED (1 << 0)
	68	#define QEDE_RSS_KEY_INITED (1 << 1)
	69	#define QEDE_RSS_CAPS_INITED (1 << 2)
	70
	71	#define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
	72	#define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
	73	(edev)->dev_info.num_tc)
	74
	75	#define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues)
f67539c2 TL	76	#define QEDE_RSS_COUNT(dev) ((dev)->data->nb_rx_queues)
f67539c2 TL	77	#define QEDE_TSS_COUNT(dev) ((dev)->data->nb_tx_queues)
11fdf7f2 TL	78
	79	#define QEDE_DUPLEX_FULL 1
	80	#define QEDE_DUPLEX_HALF 2
	81	#define QEDE_DUPLEX_UNKNOWN 0xff
	82
	83	#define QEDE_SUPPORTED_AUTONEG (1 << 6)
	84	#define QEDE_SUPPORTED_PAUSE (1 << 13)
	85
	86	#define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private)
	87
	88	#define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev)
	89
	90	#define QEDE_INIT(eth_dev) { \
	91	struct qede_dev *qdev = eth_dev->data->dev_private; \
	92	struct ecore_dev *edev = &qdev->edev; \
	93	}
	94
	95	/*********** QLogic 10G/25G/40G/50G/100G vendor/devices ids ***********/
	96	#define PCI_VENDOR_ID_QLOGIC 0x1077
	97
	98	#define CHIP_NUM_57980E 0x1634
	99	#define CHIP_NUM_57980S 0x1629
	100	#define CHIP_NUM_VF 0x1630
	101	#define CHIP_NUM_57980S_40 0x1634
	102	#define CHIP_NUM_57980S_25 0x1656
	103	#define CHIP_NUM_57980S_IOV 0x1664
	104	#define CHIP_NUM_57980S_100 0x1644
	105	#define CHIP_NUM_57980S_50 0x1654
	106	#define CHIP_NUM_AH_50G 0x8070
	107	#define CHIP_NUM_AH_10G 0x8071
	108	#define CHIP_NUM_AH_40G 0x8072
	109	#define CHIP_NUM_AH_25G 0x8073
	110	#define CHIP_NUM_AH_IOV 0x8090
	111
	112	#define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E
	113	#define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S
	114	#define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF
	115	#define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40
	116	#define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25
	117	#define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV
	118	#define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100
	119	#define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50
	120	#define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G
	121	#define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G
	122	#define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G
	123	#define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G
	124	#define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV
	125
	126
	127
9f95a23c	128	extern char qede_fw_file[];
11fdf7f2 TL	129
	130	/* Number of PF connections - 32 RX + 32 TX */
	131	#define QEDE_PF_NUM_CONNS (64)
	132
	133	/* Maximum number of flowdir filters */
	134	#define QEDE_RFS_MAX_FLTR (256)
	135
	136	#define QEDE_MAX_MCAST_FILTERS (64)
	137
	138	enum qed_filter_rx_mode_type {
	139	QED_FILTER_RX_MODE_TYPE_REGULAR,
	140	QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC,
	141	QED_FILTER_RX_MODE_TYPE_PROMISC,
	142	};
	143
	144	struct qede_vlan_entry {
	145	SLIST_ENTRY(qede_vlan_entry) list;
	146	uint16_t vid;
	147	};
	148
	149	struct qede_mcast_entry {
f67539c2	150	struct rte_ether_addr mac;
11fdf7f2 TL	151	SLIST_ENTRY(qede_mcast_entry) list;
	152	};
	153
	154	struct qede_ucast_entry {
f67539c2	155	struct rte_ether_addr mac;
11fdf7f2 TL	156	uint16_t vlan;
	157	uint16_t vni;
	158	SLIST_ENTRY(qede_ucast_entry) list;
	159	};
	160
9f95a23c TL	161	#ifndef IPV6_ADDR_LEN
	162	#define IPV6_ADDR_LEN (16)
	163	#endif
	164
	165	struct qede_arfs_tuple {
	166	union {
	167	uint32_t src_ipv4;
	168	uint8_t src_ipv6[IPV6_ADDR_LEN];
	169	};
	170
	171	union {
	172	uint32_t dst_ipv4;
	173	uint8_t dst_ipv6[IPV6_ADDR_LEN];
	174	};
	175
	176	uint16_t src_port;
	177	uint16_t dst_port;
	178	uint16_t eth_proto;
	179	uint8_t ip_proto;
	180
	181	/* Describe filtering mode needed for this kind of filter */
	182	enum ecore_filter_config_mode mode;
	183	};
	184
	185	struct qede_arfs_entry {
11fdf7f2 TL	186	uint32_t soft_id; /* unused for now */
	187	uint16_t pkt_len; /* actual packet length to match */
	188	uint16_t rx_queue; /* queue to be steered to */
f67539c2	189	bool is_drop; /* drop action */
11fdf7f2	190	const struct rte_memzone mz; / mz used to hold L2 frame */
9f95a23c TL	191	struct qede_arfs_tuple tuple;
9f95a23c TL	192	SLIST_ENTRY(qede_arfs_entry) list;
11fdf7f2 TL	193	};
11fdf7f2 TL	194
9f95a23c TL	195	/* Opaque handle for rte flow managed by PMD */
	196	struct rte_flow {
	197	struct qede_arfs_entry entry;
	198	};
	199
	200	struct qede_arfs_info {
11fdf7f2 TL	201	struct ecore_arfs_config_params arfs;
11fdf7f2 TL	202	uint16_t filter_count;
9f95a23c	203	SLIST_HEAD(arfs_list_head, qede_arfs_entry)arfs_list_head;
11fdf7f2 TL	204	};
	205
	206	/* IANA assigned default UDP ports for encapsulation protocols */
	207	#define QEDE_VXLAN_DEF_PORT (4789)
	208	#define QEDE_GENEVE_DEF_PORT (6081)
	209
	210	struct qede_tunn_params {
	211	bool enable;
	212	uint16_t num_filters;
	213	uint16_t filter_type;
	214	uint16_t udp_port;
	215	};
	216
	217	/*
	218	* Structure to store private data for each port.
	219	*/
	220	struct qede_dev {
	221	struct ecore_dev edev;
	222	const struct qed_eth_ops *ops;
	223	struct qed_dev_eth_info dev_info;
	224	struct ecore_sb_info *sb_array;
	225	struct qede_fastpath *fp_array;
f67539c2	226	struct qede_fastpath_cmt *fp_array_cmt;
11fdf7f2	227	uint16_t mtu;
f67539c2	228	uint16_t new_mtu;
11fdf7f2 TL	229	bool enable_tx_switching;
	230	bool rss_enable;
	231	struct rte_eth_rss_conf rss_conf;
	232	uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];
	233	uint64_t rss_hf;
	234	uint8_t rss_key_len;
	235	bool enable_lro;
	236	uint8_t num_rx_queues;
	237	uint8_t num_tx_queues;
	238	SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head;
	239	uint16_t configured_vlans;
	240	bool accept_any_vlan;
f67539c2	241	struct rte_ether_addr primary_mac;
11fdf7f2 TL	242	SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head;
	243	uint16_t num_mc_addr;
	244	SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head;
	245	uint16_t num_uc_addr;
	246	bool handle_hw_err;
	247	struct qede_tunn_params vxlan;
	248	struct qede_tunn_params geneve;
	249	struct qede_tunn_params ipgre;
9f95a23c	250	struct qede_arfs_info arfs_info;
11fdf7f2 TL	251	bool vlan_strip_flg;
	252	char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
	253	bool vport_started;
	254	int vlan_offload_mask;
	255	void *ethdev;
	256	};
	257
9f95a23c TL	258	static inline void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
	259	{
	260	memset(ucast, 0, sizeof(struct ecore_filter_ucast));
	261	ucast->is_rx_filter = true;
	262	ucast->is_tx_filter = true;
	263	/* ucast->assert_on_error = true; - For debug */
	264	}
	265
	266
11fdf7f2 TL	267	/* Non-static functions */
	268	int qede_config_rss(struct rte_eth_dev *eth_dev);
	269
	270	int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
	271	struct rte_eth_rss_conf *rss_conf);
	272
	273	int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
	274	struct rte_eth_rss_reta_entry64 *reta_conf,
	275	uint16_t reta_size);
	276
	277	int qed_fill_eth_dev_info(struct ecore_dev *edev,
	278	struct qed_dev_eth_info *info);
	279	int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up);
	280
	281	int qede_link_update(struct rte_eth_dev *eth_dev,
	282	__rte_unused int wait_to_complete);
	283
	284	int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type,
	285	enum rte_filter_op op, void *arg);
	286
11fdf7f2 TL	287	int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev,
	288	enum rte_filter_op filter_op, void *arg);
	289
	290	int qede_check_fdir_support(struct rte_eth_dev *eth_dev);
	291
	292	uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev,
	293	struct rte_eth_fdir_filter *fdir,
	294	void *buff,
	295	struct ecore_arfs_config_params *params);
	296
	297	void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev);
	298
	299	int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg);
	300
	301	int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu);
	302
	303	int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg);
9f95a23c TL	304	int qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
	305	struct rte_eth_udp_tunnel *tunnel_udp);
	306	int qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
	307	struct rte_eth_udp_tunnel *tunnel_udp);
	308
	309	enum _ecore_status_t
	310	qede_mac_int_ops(struct rte_eth_dev eth_dev, struct ecore_filter_ucast ucast,
	311	bool add);
	312	void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg);
	313	int qede_ucast_filter(struct rte_eth_dev *eth_dev,
	314	struct ecore_filter_ucast *ucast,
	315	bool add);
11fdf7f2	316	#endif /* _QEDE_ETHDEV_H_ */