[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / ef10_firmware_ids.h

/* SPDX-License-Identifier: BSD-3-Clause
 *
 * Copyright(c) 2019-2020 Xilinx, Inc.
 * Copyright(c) 2012-2019 Solarflare Communications Inc.
 */

/*
 * This is NOT the original source file. Do NOT edit it.
 * To update the board and firmware ids, please edit the copy in
 * the sfregistry repo and then, in that repo,
 * "make id_headers" or "make export" to
 * regenerate and export all types of headers.
 */

#ifndef CI_MGMT_FIRMWARE_IDS_H
#define CI_MGMT_FIRMWARE_IDS_H

/* Reference: SF-103588-PS
 *
 * This header file is the input for v5s/scripts/genfwdef. So if you touch it,
 * ensure that v5/scripts/genfwdef still works.
 */

enum {
  FIRMWARE_TYPE_PHY = 0,
  FIRMWARE_TYPE_PHY_LOADER = 1,
  FIRMWARE_TYPE_BOOTROM = 2,
  FIRMWARE_TYPE_MCFW = 3,
  FIRMWARE_TYPE_MCFW_BACKUP = 4,
  FIRMWARE_TYPE_DISABLED_CALLISTO = 5,
  FIRMWARE_TYPE_FPGA = 6,
  FIRMWARE_TYPE_FPGA_BACKUP = 7,
  FIRMWARE_TYPE_FCFW = 8,
  FIRMWARE_TYPE_FCFW_BACKUP = 9,
  FIRMWARE_TYPE_CPLD = 10,
  FIRMWARE_TYPE_MUMFW = 11,
  FIRMWARE_TYPE_UEFIROM = 12,
  FIRMWARE_TYPE_BUNDLE = 13,
  FIRMWARE_TYPE_CMCFW = 14,
};

enum {
  FIRMWARE_PHY_SUBTYPE_SFX7101B = 0x3,
  FIRMWARE_PHY_SUBTYPE_SFT9001A = 0x8,
  FIRMWARE_PHY_SUBTYPE_QT2025C = 0x9,
  FIRMWARE_PHY_SUBTYPE_SFT9001B = 0xa,
  FIRMWARE_PHY_SUBTYPE_SFL9021 = 0x10,      /* used for loader only */
  FIRMWARE_PHY_SUBTYPE_QT2025_KR = 0x11,    /* QT2025 in KR rather than SFP+ mode */
  FIRMWARE_PHY_SUBTYPE_AEL3020 = 0x12,      /* As seen on the R2 HP blade NIC */
};

enum {
  FIRMWARE_BOOTROM_SUBTYPE_FALCON = 0,
  FIRMWARE_BOOTROM_SUBTYPE_BETHPAGE = 1,
  FIRMWARE_BOOTROM_SUBTYPE_SIENA = 2,
  FIRMWARE_BOOTROM_SUBTYPE_HUNTINGTON = 3,
  FIRMWARE_BOOTROM_SUBTYPE_FARMINGDALE = 4,
  FIRMWARE_BOOTROM_SUBTYPE_GREENPORT = 5,
  FIRMWARE_BOOTROM_SUBTYPE_MEDFORD = 6,
  FIRMWARE_BOOTROM_SUBTYPE_MEDFORD2 = 7,
  FIRMWARE_BOOTROM_SUBTYPE_RIVERHEAD = 8,
};

enum {
  FIRMWARE_MCFW_SUBTYPE_COSIM = 0,
  FIRMWARE_MCFW_SUBTYPE_HALFSPEED = 6,
  FIRMWARE_MCFW_SUBTYPE_FLORENCE = 7,
  FIRMWARE_MCFW_SUBTYPE_ZEBEDEE = 8,
  FIRMWARE_MCFW_SUBTYPE_ERMINTRUDE = 9,
  FIRMWARE_MCFW_SUBTYPE_DYLAN = 10,
  FIRMWARE_MCFW_SUBTYPE_BRIAN = 11,
  FIRMWARE_MCFW_SUBTYPE_DOUGAL = 12,
  FIRMWARE_MCFW_SUBTYPE_MR_RUSTY = 13,
  FIRMWARE_MCFW_SUBTYPE_BUXTON = 14,
  FIRMWARE_MCFW_SUBTYPE_HOPE = 15,
  FIRMWARE_MCFW_SUBTYPE_MR_MCHENRY = 16,
  FIRMWARE_MCFW_SUBTYPE_UNCLE_HAMISH = 17,
  FIRMWARE_MCFW_SUBTYPE_TUTTLE = 18,
  FIRMWARE_MCFW_SUBTYPE_FINLAY = 19,
  FIRMWARE_MCFW_SUBTYPE_KAPTEYN = 20,
  FIRMWARE_MCFW_SUBTYPE_JOHNSON = 21,
  FIRMWARE_MCFW_SUBTYPE_GEHRELS = 22,
  FIRMWARE_MCFW_SUBTYPE_WHIPPLE = 23,
  FIRMWARE_MCFW_SUBTYPE_FORBES = 24,
  FIRMWARE_MCFW_SUBTYPE_LONGMORE = 25,
  FIRMWARE_MCFW_SUBTYPE_HERSCHEL = 26,
  FIRMWARE_MCFW_SUBTYPE_SHOEMAKER = 27,
  FIRMWARE_MCFW_SUBTYPE_IKEYA = 28,
  FIRMWARE_MCFW_SUBTYPE_KOWALSKI = 29,
  FIRMWARE_MCFW_SUBTYPE_NIMRUD = 30,
  FIRMWARE_MCFW_SUBTYPE_SPARTA = 31,
  FIRMWARE_MCFW_SUBTYPE_THEBES = 32,
  FIRMWARE_MCFW_SUBTYPE_ICARUS = 33,
  FIRMWARE_MCFW_SUBTYPE_JERICHO = 34,
  FIRMWARE_MCFW_SUBTYPE_BYBLOS = 35,
  FIRMWARE_MCFW_SUBTYPE_GROAT = 36,
  FIRMWARE_MCFW_SUBTYPE_SHILLING = 37,
  FIRMWARE_MCFW_SUBTYPE_FLORIN = 38,
  FIRMWARE_MCFW_SUBTYPE_THREEPENCE = 39,
  FIRMWARE_MCFW_SUBTYPE_CYCLOPS = 40,
  FIRMWARE_MCFW_SUBTYPE_PENNY = 41,
  FIRMWARE_MCFW_SUBTYPE_BOB = 42,
  FIRMWARE_MCFW_SUBTYPE_HOG = 43,
  FIRMWARE_MCFW_SUBTYPE_SOVEREIGN = 44,
  FIRMWARE_MCFW_SUBTYPE_SOLIDUS = 45,
  FIRMWARE_MCFW_SUBTYPE_SIXPENCE = 46,
  FIRMWARE_MCFW_SUBTYPE_CROWN = 47,
  FIRMWARE_MCFW_SUBTYPE_SOL = 48,
  FIRMWARE_MCFW_SUBTYPE_TANNER = 49,
  FIRMWARE_MCFW_SUBTYPE_BELUGA = 64,
  FIRMWARE_MCFW_SUBTYPE_KALUGA = 65,
};

enum {
  FIRMWARE_DISABLED_CALLISTO_SUBTYPE_ALL = 0
};

enum {
  FIRMWARE_FPGA_SUBTYPE_PTP = 1,                /* PTP peripheral */
  FIRMWARE_FPGA_SUBTYPE_PTP_MR_MCHENRY = 2,     /* PTP peripheral on R7 boards */
  FIRMWARE_FPGA_SUBTYPE_FLORENCE = 3,           /* Modena FPGA */
  FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH = 4,       /* Modena FPGA: Unknown silicon */
  FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH_A7 = 5,    /* Modena FPGA: A7 silicon */
  FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH_A5 = 6,    /* Modena FPGA: A5 silicon */
  FIRMWARE_FPGA_SUBTYPE_SHOEMAKER = 7,          /* Sorrento FPGA: Unknown silicon */
  FIRMWARE_FPGA_SUBTYPE_SHOEMAKER_A5 = 8,       /* Sorrento FPGA: A5 silicon */
  FIRMWARE_FPGA_SUBTYPE_SHOEMAKER_A7 = 9,       /* Sorrento FPGA: A7 silicon */
};

enum {
  FIRMWARE_FCFW_SUBTYPE_MODENA = 1,
  FIRMWARE_FCFW_SUBTYPE_SORRENTO = 2,
};

enum {
  FIRMWARE_CPLD_SUBTYPE_SFA6902 = 1,            /* CPLD on Modena (2-port) */
};

enum {
  FIRMWARE_LICENSE_SUBTYPE_AOE = 1,            /* AOE */
};

enum {
  FIRMWARE_MUMFW_SUBTYPE_MADAM_BLUE = 1,       /* Sorrento MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_ICARUS = 2,           /* Malaga MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_JERICHO = 3,          /* Emma MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_BYBLOS = 4,           /* Pagnell MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_SHILLING = 5,         /* Bradford R1.x MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_FLORIN = 6,           /* Bingley MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_THREEPENCE = 7,       /* Baildon MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_CYCLOPS = 8,          /* Talbot MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_PENNY = 9,            /* Batley MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_BOB = 10,             /* Bradford R2.x MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_HOG = 11,             /* Roxburgh MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_SOVEREIGN = 12,       /* Stirling MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_SOLIDUS = 13,         /* Roxburgh R2 MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_SIXPENCE = 14,        /* Melrose MUM firmware for Dell cards */
  FIRMWARE_MUMFW_SUBTYPE_CROWN = 15,           /* Coldstream MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_SOL = 16,             /* Roxburgh R2 MUM firmware for Dell cards with signed-bundle-update */
  FIRMWARE_MUMFW_SUBTYPE_KALUGA = 17,          /* York MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_STERLET = 18,         /* Bourn MUM firmware */
  FIRMWARE_MUMFW_SUBTYPE_TANNER = 19,          /* Melrose MUM firmware for channel cards */

};


#define FIRMWARE_UEFIROM_SUBTYPE_ALL FIRMWARE_UEFIROM_SUBTYPE_EF10
enum {
  FIRMWARE_UEFIROM_SUBTYPE_EF10 = 0,
};

enum {
  FIRMWARE_BUNDLE_SUBTYPE_DELL_X2522_25G = 1,  /* X2522-25G for Dell with bundle update support */
  FIRMWARE_BUNDLE_SUBTYPE_X2552 = 2,           /* X2552 OCP NIC - firmware bundle */
  FIRMWARE_BUNDLE_SUBTYPE_DELL_X2562 = 3,      /* X2562 OCP NIC for Dell - firmware bundle */
  FIRMWARE_BUNDLE_SUBTYPE_X2562 = 4,           /* X2562 OCP NIC - firmware bundle */
};

enum {
  FIRMWARE_CMCFW_SUBTYPE_BELUGA = 1,           /* Riverhead VCU1525 CMC firmware */
  FIRMWARE_CMCFW_SUBTYPE_KALUGA = 2,           /* York (X3x42) board CMC firmware */
};

#endif
Commit	Line	Data
f67539c2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	*
	3	* Copyright(c) 2019-2020 Xilinx, Inc.
	4	* Copyright(c) 2012-2019 Solarflare Communications Inc.
	5	*/
	6
	7	/*
	8	* This is NOT the original source file. Do NOT edit it.
	9	* To update the board and firmware ids, please edit the copy in
	10	* the sfregistry repo and then, in that repo,
	11	* "make id_headers" or "make export" to
	12	* regenerate and export all types of headers.
	13	*/
	14
	15	#ifndef CI_MGMT_FIRMWARE_IDS_H
	16	#define CI_MGMT_FIRMWARE_IDS_H
	17
	18	/* Reference: SF-103588-PS
	19	*
	20	* This header file is the input for v5s/scripts/genfwdef. So if you touch it,
	21	* ensure that v5/scripts/genfwdef still works.
	22	*/
	23
	24	enum {
	25	FIRMWARE_TYPE_PHY = 0,
	26	FIRMWARE_TYPE_PHY_LOADER = 1,
	27	FIRMWARE_TYPE_BOOTROM = 2,
	28	FIRMWARE_TYPE_MCFW = 3,
	29	FIRMWARE_TYPE_MCFW_BACKUP = 4,
	30	FIRMWARE_TYPE_DISABLED_CALLISTO = 5,
	31	FIRMWARE_TYPE_FPGA = 6,
	32	FIRMWARE_TYPE_FPGA_BACKUP = 7,
	33	FIRMWARE_TYPE_FCFW = 8,
	34	FIRMWARE_TYPE_FCFW_BACKUP = 9,
	35	FIRMWARE_TYPE_CPLD = 10,
	36	FIRMWARE_TYPE_MUMFW = 11,
	37	FIRMWARE_TYPE_UEFIROM = 12,
	38	FIRMWARE_TYPE_BUNDLE = 13,
	39	FIRMWARE_TYPE_CMCFW = 14,
	40	};
	41
	42	enum {
	43	FIRMWARE_PHY_SUBTYPE_SFX7101B = 0x3,
	44	FIRMWARE_PHY_SUBTYPE_SFT9001A = 0x8,
	45	FIRMWARE_PHY_SUBTYPE_QT2025C = 0x9,
	46	FIRMWARE_PHY_SUBTYPE_SFT9001B = 0xa,
	47	FIRMWARE_PHY_SUBTYPE_SFL9021 = 0x10, /* used for loader only */
	48	FIRMWARE_PHY_SUBTYPE_QT2025_KR = 0x11, /* QT2025 in KR rather than SFP+ mode */
	49	FIRMWARE_PHY_SUBTYPE_AEL3020 = 0x12, /* As seen on the R2 HP blade NIC */
	50	};
	51
	52	enum {
	53	FIRMWARE_BOOTROM_SUBTYPE_FALCON = 0,
	54	FIRMWARE_BOOTROM_SUBTYPE_BETHPAGE = 1,
	55	FIRMWARE_BOOTROM_SUBTYPE_SIENA = 2,
	56	FIRMWARE_BOOTROM_SUBTYPE_HUNTINGTON = 3,
	57	FIRMWARE_BOOTROM_SUBTYPE_FARMINGDALE = 4,
	58	FIRMWARE_BOOTROM_SUBTYPE_GREENPORT = 5,
	59	FIRMWARE_BOOTROM_SUBTYPE_MEDFORD = 6,
	60	FIRMWARE_BOOTROM_SUBTYPE_MEDFORD2 = 7,
	61	FIRMWARE_BOOTROM_SUBTYPE_RIVERHEAD = 8,
	62	};
	63
	64	enum {
65	FIRMWARE_MCFW_SUBTYPE_COSIM = 0,
66	FIRMWARE_MCFW_SUBTYPE_HALFSPEED = 6,
67	FIRMWARE_MCFW_SUBTYPE_FLORENCE = 7,
68	FIRMWARE_MCFW_SUBTYPE_ZEBEDEE = 8,
69	FIRMWARE_MCFW_SUBTYPE_ERMINTRUDE = 9,
70	FIRMWARE_MCFW_SUBTYPE_DYLAN = 10,
71	FIRMWARE_MCFW_SUBTYPE_BRIAN = 11,
72	FIRMWARE_MCFW_SUBTYPE_DOUGAL = 12,
73	FIRMWARE_MCFW_SUBTYPE_MR_RUSTY = 13,
74	FIRMWARE_MCFW_SUBTYPE_BUXTON = 14,
75	FIRMWARE_MCFW_SUBTYPE_HOPE = 15,
76	FIRMWARE_MCFW_SUBTYPE_MR_MCHENRY = 16,
77	FIRMWARE_MCFW_SUBTYPE_UNCLE_HAMISH = 17,
78	FIRMWARE_MCFW_SUBTYPE_TUTTLE = 18,
79	FIRMWARE_MCFW_SUBTYPE_FINLAY = 19,
80	FIRMWARE_MCFW_SUBTYPE_KAPTEYN = 20,
81	FIRMWARE_MCFW_SUBTYPE_JOHNSON = 21,
82	FIRMWARE_MCFW_SUBTYPE_GEHRELS = 22,
83	FIRMWARE_MCFW_SUBTYPE_WHIPPLE = 23,
84	FIRMWARE_MCFW_SUBTYPE_FORBES = 24,
85	FIRMWARE_MCFW_SUBTYPE_LONGMORE = 25,
86	FIRMWARE_MCFW_SUBTYPE_HERSCHEL = 26,
87	FIRMWARE_MCFW_SUBTYPE_SHOEMAKER = 27,
88	FIRMWARE_MCFW_SUBTYPE_IKEYA = 28,
89	FIRMWARE_MCFW_SUBTYPE_KOWALSKI = 29,
90	FIRMWARE_MCFW_SUBTYPE_NIMRUD = 30,
91	FIRMWARE_MCFW_SUBTYPE_SPARTA = 31,
92	FIRMWARE_MCFW_SUBTYPE_THEBES = 32,
93	FIRMWARE_MCFW_SUBTYPE_ICARUS = 33,
94	FIRMWARE_MCFW_SUBTYPE_JERICHO = 34,
95	FIRMWARE_MCFW_SUBTYPE_BYBLOS = 35,
96	FIRMWARE_MCFW_SUBTYPE_GROAT = 36,
97	FIRMWARE_MCFW_SUBTYPE_SHILLING = 37,
98	FIRMWARE_MCFW_SUBTYPE_FLORIN = 38,
99	FIRMWARE_MCFW_SUBTYPE_THREEPENCE = 39,
100	FIRMWARE_MCFW_SUBTYPE_CYCLOPS = 40,
101	FIRMWARE_MCFW_SUBTYPE_PENNY = 41,
102	FIRMWARE_MCFW_SUBTYPE_BOB = 42,
103	FIRMWARE_MCFW_SUBTYPE_HOG = 43,
104	FIRMWARE_MCFW_SUBTYPE_SOVEREIGN = 44,
105	FIRMWARE_MCFW_SUBTYPE_SOLIDUS = 45,
106	FIRMWARE_MCFW_SUBTYPE_SIXPENCE = 46,
107	FIRMWARE_MCFW_SUBTYPE_CROWN = 47,
108	FIRMWARE_MCFW_SUBTYPE_SOL = 48,
109	FIRMWARE_MCFW_SUBTYPE_TANNER = 49,
110	FIRMWARE_MCFW_SUBTYPE_BELUGA = 64,
111	FIRMWARE_MCFW_SUBTYPE_KALUGA = 65,
112	};
113
114	enum {
115	FIRMWARE_DISABLED_CALLISTO_SUBTYPE_ALL = 0
116	};
117
118	enum {
119	FIRMWARE_FPGA_SUBTYPE_PTP = 1, /* PTP peripheral */
120	FIRMWARE_FPGA_SUBTYPE_PTP_MR_MCHENRY = 2, /* PTP peripheral on R7 boards */
121	FIRMWARE_FPGA_SUBTYPE_FLORENCE = 3, /* Modena FPGA */
122	FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH = 4, /* Modena FPGA: Unknown silicon */
123	FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH_A7 = 5, /* Modena FPGA: A7 silicon */
124	FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH_A5 = 6, /* Modena FPGA: A5 silicon */
125	FIRMWARE_FPGA_SUBTYPE_SHOEMAKER = 7, /* Sorrento FPGA: Unknown silicon */
126	FIRMWARE_FPGA_SUBTYPE_SHOEMAKER_A5 = 8, /* Sorrento FPGA: A5 silicon */
127	FIRMWARE_FPGA_SUBTYPE_SHOEMAKER_A7 = 9, /* Sorrento FPGA: A7 silicon */
128	};
129
130	enum {
131	FIRMWARE_FCFW_SUBTYPE_MODENA = 1,
132	FIRMWARE_FCFW_SUBTYPE_SORRENTO = 2,
133	};
134
135	enum {
136	FIRMWARE_CPLD_SUBTYPE_SFA6902 = 1, /* CPLD on Modena (2-port) */
137	};
138
139	enum {
140	FIRMWARE_LICENSE_SUBTYPE_AOE = 1, /* AOE */
141	};
142
143	enum {
144	FIRMWARE_MUMFW_SUBTYPE_MADAM_BLUE = 1, /* Sorrento MUM firmware */
145	FIRMWARE_MUMFW_SUBTYPE_ICARUS = 2, /* Malaga MUM firmware */
146	FIRMWARE_MUMFW_SUBTYPE_JERICHO = 3, /* Emma MUM firmware */
147	FIRMWARE_MUMFW_SUBTYPE_BYBLOS = 4, /* Pagnell MUM firmware */
148	FIRMWARE_MUMFW_SUBTYPE_SHILLING = 5, /* Bradford R1.x MUM firmware */
149	FIRMWARE_MUMFW_SUBTYPE_FLORIN = 6, /* Bingley MUM firmware */
150	FIRMWARE_MUMFW_SUBTYPE_THREEPENCE = 7, /* Baildon MUM firmware */
151	FIRMWARE_MUMFW_SUBTYPE_CYCLOPS = 8, /* Talbot MUM firmware */
152	FIRMWARE_MUMFW_SUBTYPE_PENNY = 9, /* Batley MUM firmware */
153	FIRMWARE_MUMFW_SUBTYPE_BOB = 10, /* Bradford R2.x MUM firmware */
154	FIRMWARE_MUMFW_SUBTYPE_HOG = 11, /* Roxburgh MUM firmware */
155	FIRMWARE_MUMFW_SUBTYPE_SOVEREIGN = 12, /* Stirling MUM firmware */
156	FIRMWARE_MUMFW_SUBTYPE_SOLIDUS = 13, /* Roxburgh R2 MUM firmware */
157	FIRMWARE_MUMFW_SUBTYPE_SIXPENCE = 14, /* Melrose MUM firmware for Dell cards */
158	FIRMWARE_MUMFW_SUBTYPE_CROWN = 15, /* Coldstream MUM firmware */
159	FIRMWARE_MUMFW_SUBTYPE_SOL = 16, /* Roxburgh R2 MUM firmware for Dell cards with signed-bundle-update */
160	FIRMWARE_MUMFW_SUBTYPE_KALUGA = 17, /* York MUM firmware */
161	FIRMWARE_MUMFW_SUBTYPE_STERLET = 18, /* Bourn MUM firmware */
162	FIRMWARE_MUMFW_SUBTYPE_TANNER = 19, /* Melrose MUM firmware for channel cards */
163
164	};
165
166
167	#define FIRMWARE_UEFIROM_SUBTYPE_ALL FIRMWARE_UEFIROM_SUBTYPE_EF10
168	enum {
169	FIRMWARE_UEFIROM_SUBTYPE_EF10 = 0,
170	};
171
172	enum {
173	FIRMWARE_BUNDLE_SUBTYPE_DELL_X2522_25G = 1, /* X2522-25G for Dell with bundle update support */
174	FIRMWARE_BUNDLE_SUBTYPE_X2552 = 2, /* X2552 OCP NIC - firmware bundle */
175	FIRMWARE_BUNDLE_SUBTYPE_DELL_X2562 = 3, /* X2562 OCP NIC for Dell - firmware bundle */
176	FIRMWARE_BUNDLE_SUBTYPE_X2562 = 4, /* X2562 OCP NIC - firmware bundle */
177	};
178
179	enum {
180	FIRMWARE_CMCFW_SUBTYPE_BELUGA = 1, /* Riverhead VCU1525 CMC firmware */
181	FIRMWARE_CMCFW_SUBTYPE_KALUGA = 2, /* York (X3x42) board CMC firmware */
182	};
183
184	#endif