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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / efx.h
CommitLineData
11fdf7f2
TL		 1/* SPDX-License-Identifier: BSD-3-Clause
2 *
f67539c2
TL		 3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
11fdf7f2
TL		 5 */
6
7#ifndef _SYS_EFX_H
8#define _SYS_EFX_H
9
9f95a23c 10#include "efx_annote.h"
11fdf7f2 11#include "efsys.h"
f67539c2 12#include "efx_types.h"
11fdf7f2
TL		 13#include "efx_check.h"
14#include "efx_phy_ids.h"
15
16#ifdef __cplusplus
17extern "C" {
18#endif
19
20#define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
22
23#define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
25
26#define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
28
29/* The macro expands divider twice */
30#define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
31
f67539c2
TL		 32/* Round value up to the nearest power of two. */
33#define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
35
36/* Align value down to the nearest power of two. */
37#define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
39
40/* Test if value is power of 2 aligned. */
41#define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
43
11fdf7f2
TL		 44/* Return codes */
45
46typedef __success(return == 0) int efx_rc_t;
47
48
49/* Chip families */
50
51typedef enum efx_family_e {
52 EFX_FAMILY_INVALID,
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
54 EFX_FAMILY_SIENA,
55 EFX_FAMILY_HUNTINGTON,
56 EFX_FAMILY_MEDFORD,
57 EFX_FAMILY_MEDFORD2,
58 EFX_FAMILY_NTYPES
59} efx_family_t;
60
61extern __checkReturn efx_rc_t
62efx_family(
63 __in uint16_t venid,
64 __in uint16_t devid,
65 __out efx_family_t *efp,
66 __out unsigned int *membarp);
67
68
69#define EFX_PCI_VENID_SFC 0x1924
70
71#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
72
73#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
74#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
75#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
76
77#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
78#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
79#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
80
81#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
82#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
83
84#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
85#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
86#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
87
88#define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
89#define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
90#define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
91
92
93#define EFX_MEM_BAR_SIENA 2
94
95#define EFX_MEM_BAR_HUNTINGTON_PF 2
96#define EFX_MEM_BAR_HUNTINGTON_VF 0
97
98#define EFX_MEM_BAR_MEDFORD_PF 2
99#define EFX_MEM_BAR_MEDFORD_VF 0
100
101#define EFX_MEM_BAR_MEDFORD2 0
102
103
104/* Error codes */
105
106enum {
107 EFX_ERR_INVALID,
108 EFX_ERR_SRAM_OOB,
109 EFX_ERR_BUFID_DC_OOB,
110 EFX_ERR_MEM_PERR,
111 EFX_ERR_RBUF_OWN,
112 EFX_ERR_TBUF_OWN,
113 EFX_ERR_RDESQ_OWN,
114 EFX_ERR_TDESQ_OWN,
115 EFX_ERR_EVQ_OWN,
116 EFX_ERR_EVFF_OFLO,
117 EFX_ERR_ILL_ADDR,
118 EFX_ERR_SRAM_PERR,
119 EFX_ERR_NCODES
120};
121
122/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
123extern __checkReturn uint32_t
124efx_crc32_calculate(
125 __in uint32_t crc_init,
126 __in_ecount(length) uint8_t const *input,
127 __in int length);
128
129
130/* Type prototypes */
131
132typedef struct efx_rxq_s efx_rxq_t;
133
134/* NIC */
135
136typedef struct efx_nic_s efx_nic_t;
137
138extern __checkReturn efx_rc_t
139efx_nic_create(
140 __in efx_family_t family,
141 __in efsys_identifier_t *esip,
142 __in efsys_bar_t *esbp,
143 __in efsys_lock_t *eslp,
144 __deref_out efx_nic_t **enpp);
145
146/* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
147typedef enum efx_fw_variant_e {
148 EFX_FW_VARIANT_FULL_FEATURED,
149 EFX_FW_VARIANT_LOW_LATENCY,
150 EFX_FW_VARIANT_PACKED_STREAM,
151 EFX_FW_VARIANT_HIGH_TX_RATE,
152 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
153 EFX_FW_VARIANT_RULES_ENGINE,
154 EFX_FW_VARIANT_DPDK,
155 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
156} efx_fw_variant_t;
157
158extern __checkReturn efx_rc_t
159efx_nic_probe(
160 __in efx_nic_t *enp,
161 __in efx_fw_variant_t efv);
162
163extern __checkReturn efx_rc_t
164efx_nic_init(
165 __in efx_nic_t *enp);
166
167extern __checkReturn efx_rc_t
168efx_nic_reset(
169 __in efx_nic_t *enp);
170
9f95a23c
TL		 171extern __checkReturn boolean_t
172efx_nic_hw_unavailable(
173 __in efx_nic_t *enp);
174
175extern void
176efx_nic_set_hw_unavailable(
177 __in efx_nic_t *enp);
178
11fdf7f2
TL		 179#if EFSYS_OPT_DIAG
180
181extern __checkReturn efx_rc_t
182efx_nic_register_test(
183 __in efx_nic_t *enp);
184
185#endif /* EFSYS_OPT_DIAG */
186
187extern void
188efx_nic_fini(
189 __in efx_nic_t *enp);
190
191extern void
192efx_nic_unprobe(
193 __in efx_nic_t *enp);
194
195extern void
196efx_nic_destroy(
197 __in efx_nic_t *enp);
198
199#define EFX_PCIE_LINK_SPEED_GEN1 1
200#define EFX_PCIE_LINK_SPEED_GEN2 2
201#define EFX_PCIE_LINK_SPEED_GEN3 3
202
203typedef enum efx_pcie_link_performance_e {
204 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
205 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
206 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
207 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
208} efx_pcie_link_performance_t;
209
210extern __checkReturn efx_rc_t
211efx_nic_calculate_pcie_link_bandwidth(
212 __in uint32_t pcie_link_width,
213 __in uint32_t pcie_link_gen,
214 __out uint32_t *bandwidth_mbpsp);
215
216extern __checkReturn efx_rc_t
217efx_nic_check_pcie_link_speed(
218 __in efx_nic_t *enp,
219 __in uint32_t pcie_link_width,
220 __in uint32_t pcie_link_gen,
221 __out efx_pcie_link_performance_t *resultp);
222
223#if EFSYS_OPT_MCDI
224
9f95a23c
TL		 225#if EFX_OPTS_EF10()
226/* EF10 architecture NICs require MCDIv2 commands */
11fdf7f2
TL		 227#define WITH_MCDI_V2 1
228#endif
229
230typedef struct efx_mcdi_req_s efx_mcdi_req_t;
231
232typedef enum efx_mcdi_exception_e {
233 EFX_MCDI_EXCEPTION_MC_REBOOT,
234 EFX_MCDI_EXCEPTION_MC_BADASSERT,
235} efx_mcdi_exception_t;
236
237#if EFSYS_OPT_MCDI_LOGGING
238typedef enum efx_log_msg_e {
239 EFX_LOG_INVALID,
240 EFX_LOG_MCDI_REQUEST,
241 EFX_LOG_MCDI_RESPONSE,
242} efx_log_msg_t;
243#endif /* EFSYS_OPT_MCDI_LOGGING */
244
245typedef struct efx_mcdi_transport_s {
246 void *emt_context;
247 efsys_mem_t *emt_dma_mem;
248 void (*emt_execute)(void *, efx_mcdi_req_t *);
249 void (*emt_ev_cpl)(void *);
250 void (*emt_exception)(void *, efx_mcdi_exception_t);
251#if EFSYS_OPT_MCDI_LOGGING
252 void (*emt_logger)(void *, efx_log_msg_t,
253 void *, size_t, void *, size_t);
254#endif /* EFSYS_OPT_MCDI_LOGGING */
255#if EFSYS_OPT_MCDI_PROXY_AUTH
256 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
257#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
f67539c2
TL		 258#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
259 void (*emt_ev_proxy_request)(void *, uint32_t);
260#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
11fdf7f2
TL		 261} efx_mcdi_transport_t;
262
263extern __checkReturn efx_rc_t
264efx_mcdi_init(
265 __in efx_nic_t *enp,
266 __in const efx_mcdi_transport_t *mtp);
267
268extern __checkReturn efx_rc_t
269efx_mcdi_reboot(
270 __in efx_nic_t *enp);
271
272 void
273efx_mcdi_new_epoch(
274 __in efx_nic_t *enp);
275
276extern void
277efx_mcdi_get_timeout(
278 __in efx_nic_t *enp,
279 __in efx_mcdi_req_t *emrp,
280 __out uint32_t *usec_timeoutp);
281
282extern void
283efx_mcdi_request_start(
284 __in efx_nic_t *enp,
285 __in efx_mcdi_req_t *emrp,
286 __in boolean_t ev_cpl);
287
288extern __checkReturn boolean_t
289efx_mcdi_request_poll(
290 __in efx_nic_t *enp);
291
292extern __checkReturn boolean_t
293efx_mcdi_request_abort(
294 __in efx_nic_t *enp);
295
296extern void
297efx_mcdi_fini(
298 __in efx_nic_t *enp);
299
300#endif /* EFSYS_OPT_MCDI */
301
302/* INTR */
303
304#define EFX_NINTR_SIENA 1024
305
306typedef enum efx_intr_type_e {
307 EFX_INTR_INVALID = 0,
308 EFX_INTR_LINE,
309 EFX_INTR_MESSAGE,
310 EFX_INTR_NTYPES
311} efx_intr_type_t;
312
313#define EFX_INTR_SIZE (sizeof (efx_oword_t))
314
315extern __checkReturn efx_rc_t
316efx_intr_init(
317 __in efx_nic_t *enp,
318 __in efx_intr_type_t type,
9f95a23c 319 __in_opt efsys_mem_t *esmp);
11fdf7f2
TL		 320
321extern void
322efx_intr_enable(
323 __in efx_nic_t *enp);
324
325extern void
326efx_intr_disable(
327 __in efx_nic_t *enp);
328
329extern void
330efx_intr_disable_unlocked(
331 __in efx_nic_t *enp);
332
333#define EFX_INTR_NEVQS 32
334
335extern __checkReturn efx_rc_t
336efx_intr_trigger(
337 __in efx_nic_t *enp,
338 __in unsigned int level);
339
340extern void
341efx_intr_status_line(
342 __in efx_nic_t *enp,
343 __out boolean_t *fatalp,
344 __out uint32_t *maskp);
345
346extern void
347efx_intr_status_message(
348 __in efx_nic_t *enp,
349 __in unsigned int message,
350 __out boolean_t *fatalp);
351
352extern void
353efx_intr_fatal(
354 __in efx_nic_t *enp);
355
356extern void
357efx_intr_fini(
358 __in efx_nic_t *enp);
359
360/* MAC */
361
362#if EFSYS_OPT_MAC_STATS
363
364/* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
365typedef enum efx_mac_stat_e {
366 EFX_MAC_RX_OCTETS,
367 EFX_MAC_RX_PKTS,
368 EFX_MAC_RX_UNICST_PKTS,
369 EFX_MAC_RX_MULTICST_PKTS,
370 EFX_MAC_RX_BRDCST_PKTS,
371 EFX_MAC_RX_PAUSE_PKTS,
372 EFX_MAC_RX_LE_64_PKTS,
373 EFX_MAC_RX_65_TO_127_PKTS,
374 EFX_MAC_RX_128_TO_255_PKTS,
375 EFX_MAC_RX_256_TO_511_PKTS,
376 EFX_MAC_RX_512_TO_1023_PKTS,
377 EFX_MAC_RX_1024_TO_15XX_PKTS,
378 EFX_MAC_RX_GE_15XX_PKTS,
379 EFX_MAC_RX_ERRORS,
380 EFX_MAC_RX_FCS_ERRORS,
381 EFX_MAC_RX_DROP_EVENTS,
382 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
383 EFX_MAC_RX_SYMBOL_ERRORS,
384 EFX_MAC_RX_ALIGN_ERRORS,
385 EFX_MAC_RX_INTERNAL_ERRORS,
386 EFX_MAC_RX_JABBER_PKTS,
387 EFX_MAC_RX_LANE0_CHAR_ERR,
388 EFX_MAC_RX_LANE1_CHAR_ERR,
389 EFX_MAC_RX_LANE2_CHAR_ERR,
390 EFX_MAC_RX_LANE3_CHAR_ERR,
391 EFX_MAC_RX_LANE0_DISP_ERR,
392 EFX_MAC_RX_LANE1_DISP_ERR,
393 EFX_MAC_RX_LANE2_DISP_ERR,
394 EFX_MAC_RX_LANE3_DISP_ERR,
395 EFX_MAC_RX_MATCH_FAULT,
396 EFX_MAC_RX_NODESC_DROP_CNT,
397 EFX_MAC_TX_OCTETS,
398 EFX_MAC_TX_PKTS,
399 EFX_MAC_TX_UNICST_PKTS,
400 EFX_MAC_TX_MULTICST_PKTS,
401 EFX_MAC_TX_BRDCST_PKTS,
402 EFX_MAC_TX_PAUSE_PKTS,
403 EFX_MAC_TX_LE_64_PKTS,
404 EFX_MAC_TX_65_TO_127_PKTS,
405 EFX_MAC_TX_128_TO_255_PKTS,
406 EFX_MAC_TX_256_TO_511_PKTS,
407 EFX_MAC_TX_512_TO_1023_PKTS,
408 EFX_MAC_TX_1024_TO_15XX_PKTS,
409 EFX_MAC_TX_GE_15XX_PKTS,
410 EFX_MAC_TX_ERRORS,
411 EFX_MAC_TX_SGL_COL_PKTS,
412 EFX_MAC_TX_MULT_COL_PKTS,
413 EFX_MAC_TX_EX_COL_PKTS,
414 EFX_MAC_TX_LATE_COL_PKTS,
415 EFX_MAC_TX_DEF_PKTS,
416 EFX_MAC_TX_EX_DEF_PKTS,
417 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
418 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
419 EFX_MAC_PM_TRUNC_VFIFO_FULL,
420 EFX_MAC_PM_DISCARD_VFIFO_FULL,
421 EFX_MAC_PM_TRUNC_QBB,
422 EFX_MAC_PM_DISCARD_QBB,
423 EFX_MAC_PM_DISCARD_MAPPING,
424 EFX_MAC_RXDP_Q_DISABLED_PKTS,
425 EFX_MAC_RXDP_DI_DROPPED_PKTS,
426 EFX_MAC_RXDP_STREAMING_PKTS,
427 EFX_MAC_RXDP_HLB_FETCH,
428 EFX_MAC_RXDP_HLB_WAIT,
429 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
430 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
431 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
432 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
433 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
434 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
435 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
436 EFX_MAC_VADAPTER_RX_BAD_BYTES,
437 EFX_MAC_VADAPTER_RX_OVERFLOW,
438 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
439 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
440 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
441 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
442 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
443 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
444 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
445 EFX_MAC_VADAPTER_TX_BAD_BYTES,
446 EFX_MAC_VADAPTER_TX_OVERFLOW,
447 EFX_MAC_FEC_UNCORRECTED_ERRORS,
448 EFX_MAC_FEC_CORRECTED_ERRORS,
449 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
450 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
451 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
452 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
453 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
454 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
455 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
456 EFX_MAC_CTPIO_OVERFLOW_FAIL,
457 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
458 EFX_MAC_CTPIO_TIMEOUT_FAIL,
459 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
460 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
461 EFX_MAC_CTPIO_INVALID_WR_FAIL,
462 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
463 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
464 EFX_MAC_CTPIO_RUNT_FALLBACK,
465 EFX_MAC_CTPIO_SUCCESS,
466 EFX_MAC_CTPIO_FALLBACK,
467 EFX_MAC_CTPIO_POISON,
468 EFX_MAC_CTPIO_ERASE,
469 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
470 EFX_MAC_RXDP_HLB_IDLE,
471 EFX_MAC_RXDP_HLB_TIMEOUT,
472 EFX_MAC_NSTATS
473} efx_mac_stat_t;
474
475/* END MKCONFIG GENERATED EfxHeaderMacBlock */
476
477#endif /* EFSYS_OPT_MAC_STATS */
478
479typedef enum efx_link_mode_e {
480 EFX_LINK_UNKNOWN = 0,
481 EFX_LINK_DOWN,
482 EFX_LINK_10HDX,
483 EFX_LINK_10FDX,
484 EFX_LINK_100HDX,
485 EFX_LINK_100FDX,
486 EFX_LINK_1000HDX,
487 EFX_LINK_1000FDX,
488 EFX_LINK_10000FDX,
489 EFX_LINK_40000FDX,
490 EFX_LINK_25000FDX,
491 EFX_LINK_50000FDX,
492 EFX_LINK_100000FDX,
493 EFX_LINK_NMODES
494} efx_link_mode_t;
495
496#define EFX_MAC_ADDR_LEN 6
497
498#define EFX_VNI_OR_VSID_LEN 3
499
500#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
501
502#define EFX_MAC_MULTICAST_LIST_MAX 256
503
504#define EFX_MAC_SDU_MAX 9202
505
506#define EFX_MAC_PDU_ADJUSTMENT \
507 (/* EtherII */ 14 \
508 + /* VLAN */ 4 \
509 + /* CRC */ 4 \
510 + /* bug16011 */ 16) \
511
512#define EFX_MAC_PDU(_sdu) \
f67539c2 513 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
11fdf7f2
TL		 514
515/*
f67539c2 516 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
11fdf7f2
TL		 517 * the SDU rounded up slightly.
518 */
519#define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
520
521#define EFX_MAC_PDU_MIN 60
522#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
523
524extern __checkReturn efx_rc_t
525efx_mac_pdu_get(
526 __in efx_nic_t *enp,
527 __out size_t *pdu);
528
529extern __checkReturn efx_rc_t
530efx_mac_pdu_set(
531 __in efx_nic_t *enp,
532 __in size_t pdu);
533
534extern __checkReturn efx_rc_t
535efx_mac_addr_set(
536 __in efx_nic_t *enp,
537 __in uint8_t *addr);
538
539extern __checkReturn efx_rc_t
540efx_mac_filter_set(
541 __in efx_nic_t *enp,
542 __in boolean_t all_unicst,
543 __in boolean_t mulcst,
544 __in boolean_t all_mulcst,
545 __in boolean_t brdcst);
546
f67539c2
TL		 547extern void
548efx_mac_filter_get_all_ucast_mcast(
549 __in efx_nic_t *enp,
550 __out boolean_t *all_unicst,
551 __out boolean_t *all_mulcst);
552
11fdf7f2
TL		 553extern __checkReturn efx_rc_t
554efx_mac_multicast_list_set(
555 __in efx_nic_t *enp,
556 __in_ecount(6*count) uint8_t const *addrs,
557 __in int count);
558
559extern __checkReturn efx_rc_t
560efx_mac_filter_default_rxq_set(
561 __in efx_nic_t *enp,
562 __in efx_rxq_t *erp,
563 __in boolean_t using_rss);
564
565extern void
566efx_mac_filter_default_rxq_clear(
567 __in efx_nic_t *enp);
568
569extern __checkReturn efx_rc_t
570efx_mac_drain(
571 __in efx_nic_t *enp,
572 __in boolean_t enabled);
573
574extern __checkReturn efx_rc_t
575efx_mac_up(
576 __in efx_nic_t *enp,
577 __out boolean_t *mac_upp);
578
579#define EFX_FCNTL_RESPOND 0x00000001
580#define EFX_FCNTL_GENERATE 0x00000002
581
582extern __checkReturn efx_rc_t
583efx_mac_fcntl_set(
584 __in efx_nic_t *enp,
585 __in unsigned int fcntl,
586 __in boolean_t autoneg);
587
588extern void
589efx_mac_fcntl_get(
590 __in efx_nic_t *enp,
591 __out unsigned int *fcntl_wantedp,
592 __out unsigned int *fcntl_linkp);
593
594
595#if EFSYS_OPT_MAC_STATS
596
597#if EFSYS_OPT_NAMES
598
599extern __checkReturn const char *
600efx_mac_stat_name(
601 __in efx_nic_t *enp,
602 __in unsigned int id);
603
604#endif /* EFSYS_OPT_NAMES */
605
606#define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
607
f67539c2
TL		 608#define EFX_MAC_STATS_MASK_NPAGES \
609 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
610 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
11fdf7f2
TL		 611 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
612
613/*
614 * Get mask of MAC statistics supported by the hardware.
615 *
616 * If mask_size is insufficient to return the mask, EINVAL error is
617 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
618 * (which is sizeof (uint32_t)) is sufficient.
619 */
620extern __checkReturn efx_rc_t
621efx_mac_stats_get_mask(
622 __in efx_nic_t *enp,
623 __out_bcount(mask_size) uint32_t *maskp,
624 __in size_t mask_size);
625
626#define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
627 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
628 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
629
630
631extern __checkReturn efx_rc_t
632efx_mac_stats_clear(
633 __in efx_nic_t *enp);
634
635/*
636 * Upload mac statistics supported by the hardware into the given buffer.
637 *
638 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
639 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
640 *
641 * The hardware will only DMA statistics that it understands (of course).
642 * Drivers should not make any assumptions about which statistics are
643 * supported, especially when the statistics are generated by firmware.
644 *
645 * Thus, drivers should zero this buffer before use, so that not-understood
646 * statistics read back as zero.
647 */
648extern __checkReturn efx_rc_t
649efx_mac_stats_upload(
650 __in efx_nic_t *enp,
651 __in efsys_mem_t *esmp);
652
653extern __checkReturn efx_rc_t
654efx_mac_stats_periodic(
655 __in efx_nic_t *enp,
656 __in efsys_mem_t *esmp,
657 __in uint16_t period_ms,
658 __in boolean_t events);
659
660extern __checkReturn efx_rc_t
661efx_mac_stats_update(
662 __in efx_nic_t *enp,
663 __in efsys_mem_t *esmp,
664 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
665 __inout_opt uint32_t *generationp);
666
667#endif /* EFSYS_OPT_MAC_STATS */
668
669/* MON */
670
671typedef enum efx_mon_type_e {
672 EFX_MON_INVALID = 0,
673 EFX_MON_SFC90X0,
674 EFX_MON_SFC91X0,
675 EFX_MON_SFC92X0,
676 EFX_MON_NTYPES
677} efx_mon_type_t;
678
679#if EFSYS_OPT_NAMES
680
681extern const char *
682efx_mon_name(
683 __in efx_nic_t *enp);
684
685#endif /* EFSYS_OPT_NAMES */
686
687extern __checkReturn efx_rc_t
688efx_mon_init(
689 __in efx_nic_t *enp);
690
691#if EFSYS_OPT_MON_STATS
692
693#define EFX_MON_STATS_PAGE_SIZE 0x100
694#define EFX_MON_MASK_ELEMENT_SIZE 32
695
9f95a23c 696/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
11fdf7f2 697typedef enum efx_mon_stat_e {
9f95a23c
TL		 698 EFX_MON_STAT_CONTROLLER_TEMP,
699 EFX_MON_STAT_PHY_COMMON_TEMP,
700 EFX_MON_STAT_CONTROLLER_COOLING,
701 EFX_MON_STAT_PHY0_TEMP,
702 EFX_MON_STAT_PHY0_COOLING,
703 EFX_MON_STAT_PHY1_TEMP,
704 EFX_MON_STAT_PHY1_COOLING,
705 EFX_MON_STAT_IN_1V0,
706 EFX_MON_STAT_IN_1V2,
707 EFX_MON_STAT_IN_1V8,
708 EFX_MON_STAT_IN_2V5,
709 EFX_MON_STAT_IN_3V3,
710 EFX_MON_STAT_IN_12V0,
711 EFX_MON_STAT_IN_1V2A,
712 EFX_MON_STAT_IN_VREF,
713 EFX_MON_STAT_OUT_VAOE,
11fdf7f2
TL		 714 EFX_MON_STAT_AOE_TEMP,
715 EFX_MON_STAT_PSU_AOE_TEMP,
716 EFX_MON_STAT_PSU_TEMP,
9f95a23c
TL		 717 EFX_MON_STAT_FAN_0,
718 EFX_MON_STAT_FAN_1,
719 EFX_MON_STAT_FAN_2,
720 EFX_MON_STAT_FAN_3,
721 EFX_MON_STAT_FAN_4,
722 EFX_MON_STAT_IN_VAOE,
723 EFX_MON_STAT_OUT_IAOE,
724 EFX_MON_STAT_IN_IAOE,
11fdf7f2 725 EFX_MON_STAT_NIC_POWER,
9f95a23c
TL		 726 EFX_MON_STAT_IN_0V9,
727 EFX_MON_STAT_IN_I0V9,
728 EFX_MON_STAT_IN_I1V2,
729 EFX_MON_STAT_IN_0V9_ADC,
730 EFX_MON_STAT_CONTROLLER_2_TEMP,
731 EFX_MON_STAT_VREG_INTERNAL_TEMP,
732 EFX_MON_STAT_VREG_0V9_TEMP,
733 EFX_MON_STAT_VREG_1V2_TEMP,
734 EFX_MON_STAT_CONTROLLER_VPTAT,
735 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
736 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
737 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
11fdf7f2
TL		 738 EFX_MON_STAT_AMBIENT_TEMP,
739 EFX_MON_STAT_AIRFLOW,
740 EFX_MON_STAT_VDD08D_VSS08D_CSR,
741 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
742 EFX_MON_STAT_HOTPOINT_TEMP,
9f95a23c
TL		 743 EFX_MON_STAT_PHY_POWER_PORT0,
744 EFX_MON_STAT_PHY_POWER_PORT1,
11fdf7f2 745 EFX_MON_STAT_MUM_VCC,
9f95a23c
TL		 746 EFX_MON_STAT_IN_0V9_A,
747 EFX_MON_STAT_IN_I0V9_A,
748 EFX_MON_STAT_VREG_0V9_A_TEMP,
749 EFX_MON_STAT_IN_0V9_B,
750 EFX_MON_STAT_IN_I0V9_B,
751 EFX_MON_STAT_VREG_0V9_B_TEMP,
11fdf7f2 752 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
9f95a23c 753 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
11fdf7f2 754 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
9f95a23c 755 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
11fdf7f2
TL		 756 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
757 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
9f95a23c
TL		 758 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
759 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
11fdf7f2
TL		 760 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
761 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
9f95a23c
TL		 762 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
763 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
11fdf7f2
TL		 764 EFX_MON_STAT_SODIMM_VOUT,
765 EFX_MON_STAT_SODIMM_0_TEMP,
766 EFX_MON_STAT_SODIMM_1_TEMP,
767 EFX_MON_STAT_PHY0_VCC,
768 EFX_MON_STAT_PHY1_VCC,
769 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
770 EFX_MON_STAT_BOARD_FRONT_TEMP,
771 EFX_MON_STAT_BOARD_BACK_TEMP,
9f95a23c
TL		 772 EFX_MON_STAT_IN_I1V8,
773 EFX_MON_STAT_IN_I2V5,
774 EFX_MON_STAT_IN_I3V3,
775 EFX_MON_STAT_IN_I12V0,
776 EFX_MON_STAT_IN_1V3,
777 EFX_MON_STAT_IN_I1V3,
11fdf7f2
TL		 778 EFX_MON_NSTATS
779} efx_mon_stat_t;
780
781/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
782
783typedef enum efx_mon_stat_state_e {
784 EFX_MON_STAT_STATE_OK = 0,
785 EFX_MON_STAT_STATE_WARNING = 1,
786 EFX_MON_STAT_STATE_FATAL = 2,
787 EFX_MON_STAT_STATE_BROKEN = 3,
788 EFX_MON_STAT_STATE_NO_READING = 4,
789} efx_mon_stat_state_t;
790
9f95a23c
TL		 791typedef enum efx_mon_stat_unit_e {
792 EFX_MON_STAT_UNIT_UNKNOWN = 0,
793 EFX_MON_STAT_UNIT_BOOL,
794 EFX_MON_STAT_UNIT_TEMP_C,
795 EFX_MON_STAT_UNIT_VOLTAGE_MV,
796 EFX_MON_STAT_UNIT_CURRENT_MA,
797 EFX_MON_STAT_UNIT_POWER_W,
798 EFX_MON_STAT_UNIT_RPM,
799 EFX_MON_NUNITS
800} efx_mon_stat_unit_t;
801
11fdf7f2 802typedef struct efx_mon_stat_value_s {
9f95a23c
TL		 803 uint16_t emsv_value;
804 efx_mon_stat_state_t emsv_state;
805 efx_mon_stat_unit_t emsv_unit;
11fdf7f2
TL		 806} efx_mon_stat_value_t;
807
9f95a23c
TL		 808typedef struct efx_mon_limit_value_s {
809 uint16_t emlv_warning_min;
810 uint16_t emlv_warning_max;
811 uint16_t emlv_fatal_min;
812 uint16_t emlv_fatal_max;
813} efx_mon_stat_limits_t;
814
815typedef enum efx_mon_stat_portmask_e {
816 EFX_MON_STAT_PORTMAP_NONE = 0,
817 EFX_MON_STAT_PORTMAP_PORT0 = 1,
818 EFX_MON_STAT_PORTMAP_PORT1 = 2,
819 EFX_MON_STAT_PORTMAP_PORT2 = 3,
820 EFX_MON_STAT_PORTMAP_PORT3 = 4,
821 EFX_MON_STAT_PORTMAP_ALL = (-1),
822 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
823} efx_mon_stat_portmask_t;
824
11fdf7f2
TL		 825#if EFSYS_OPT_NAMES
826
827extern const char *
828efx_mon_stat_name(
829 __in efx_nic_t *enp,
830 __in efx_mon_stat_t id);
831
9f95a23c
TL		 832extern const char *
833efx_mon_stat_description(
834 __in efx_nic_t *enp,
835 __in efx_mon_stat_t id);
836
11fdf7f2
TL		 837#endif /* EFSYS_OPT_NAMES */
838
9f95a23c
TL		 839extern __checkReturn boolean_t
840efx_mon_mcdi_to_efx_stat(
841 __in int mcdi_index,
842 __out efx_mon_stat_t *statp);
843
844extern __checkReturn boolean_t
845efx_mon_get_stat_unit(
846 __in efx_mon_stat_t stat,
847 __out efx_mon_stat_unit_t *unitp);
848
849extern __checkReturn boolean_t
850efx_mon_get_stat_portmap(
851 __in efx_mon_stat_t stat,
852 __out efx_mon_stat_portmask_t *maskp);
853
11fdf7f2
TL		 854extern __checkReturn efx_rc_t
855efx_mon_stats_update(
856 __in efx_nic_t *enp,
857 __in efsys_mem_t *esmp,
858 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
859
9f95a23c
TL		 860extern __checkReturn efx_rc_t
861efx_mon_limits_update(
862 __in efx_nic_t *enp,
863 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
864
11fdf7f2
TL		 865#endif /* EFSYS_OPT_MON_STATS */
866
867extern void
868efx_mon_fini(
869 __in efx_nic_t *enp);
870
871/* PHY */
872
873extern __checkReturn efx_rc_t
874efx_phy_verify(
875 __in efx_nic_t *enp);
876
877#if EFSYS_OPT_PHY_LED_CONTROL
878
879typedef enum efx_phy_led_mode_e {
880 EFX_PHY_LED_DEFAULT = 0,
881 EFX_PHY_LED_OFF,
882 EFX_PHY_LED_ON,
883 EFX_PHY_LED_FLASH,
884 EFX_PHY_LED_NMODES
885} efx_phy_led_mode_t;
886
887extern __checkReturn efx_rc_t
888efx_phy_led_set(
889 __in efx_nic_t *enp,
890 __in efx_phy_led_mode_t mode);
891
892#endif /* EFSYS_OPT_PHY_LED_CONTROL */
893
894extern __checkReturn efx_rc_t
895efx_port_init(
896 __in efx_nic_t *enp);
897
898#if EFSYS_OPT_LOOPBACK
899
900typedef enum efx_loopback_type_e {
901 EFX_LOOPBACK_OFF = 0,
902 EFX_LOOPBACK_DATA = 1,
903 EFX_LOOPBACK_GMAC = 2,
904 EFX_LOOPBACK_XGMII = 3,
905 EFX_LOOPBACK_XGXS = 4,
906 EFX_LOOPBACK_XAUI = 5,
907 EFX_LOOPBACK_GMII = 6,
908 EFX_LOOPBACK_SGMII = 7,
909 EFX_LOOPBACK_XGBR = 8,
910 EFX_LOOPBACK_XFI = 9,
911 EFX_LOOPBACK_XAUI_FAR = 10,
912 EFX_LOOPBACK_GMII_FAR = 11,
913 EFX_LOOPBACK_SGMII_FAR = 12,
914 EFX_LOOPBACK_XFI_FAR = 13,
915 EFX_LOOPBACK_GPHY = 14,
916 EFX_LOOPBACK_PHY_XS = 15,
917 EFX_LOOPBACK_PCS = 16,
918 EFX_LOOPBACK_PMA_PMD = 17,
919 EFX_LOOPBACK_XPORT = 18,
920 EFX_LOOPBACK_XGMII_WS = 19,
921 EFX_LOOPBACK_XAUI_WS = 20,
922 EFX_LOOPBACK_XAUI_WS_FAR = 21,
923 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
924 EFX_LOOPBACK_GMII_WS = 23,
925 EFX_LOOPBACK_XFI_WS = 24,
926 EFX_LOOPBACK_XFI_WS_FAR = 25,
927 EFX_LOOPBACK_PHYXS_WS = 26,
928 EFX_LOOPBACK_PMA_INT = 27,
929 EFX_LOOPBACK_SD_NEAR = 28,
930 EFX_LOOPBACK_SD_FAR = 29,
931 EFX_LOOPBACK_PMA_INT_WS = 30,
932 EFX_LOOPBACK_SD_FEP2_WS = 31,
933 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
934 EFX_LOOPBACK_SD_FEP_WS = 33,
935 EFX_LOOPBACK_SD_FES_WS = 34,
936 EFX_LOOPBACK_AOE_INT_NEAR = 35,
937 EFX_LOOPBACK_DATA_WS = 36,
938 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
939 EFX_LOOPBACK_NTYPES
940} efx_loopback_type_t;
941
942typedef enum efx_loopback_kind_e {
943 EFX_LOOPBACK_KIND_OFF = 0,
944 EFX_LOOPBACK_KIND_ALL,
945 EFX_LOOPBACK_KIND_MAC,
946 EFX_LOOPBACK_KIND_PHY,
947 EFX_LOOPBACK_NKINDS
948} efx_loopback_kind_t;
949
950extern void
951efx_loopback_mask(
952 __in efx_loopback_kind_t loopback_kind,
953 __out efx_qword_t *maskp);
954
955extern __checkReturn efx_rc_t
956efx_port_loopback_set(
957 __in efx_nic_t *enp,
958 __in efx_link_mode_t link_mode,
959 __in efx_loopback_type_t type);
960
961#if EFSYS_OPT_NAMES
962
963extern __checkReturn const char *
964efx_loopback_type_name(
965 __in efx_nic_t *enp,
966 __in efx_loopback_type_t type);
967
968#endif /* EFSYS_OPT_NAMES */
969
970#endif /* EFSYS_OPT_LOOPBACK */
971
972extern __checkReturn efx_rc_t
973efx_port_poll(
974 __in efx_nic_t *enp,
975 __out_opt efx_link_mode_t *link_modep);
976
977extern void
978efx_port_fini(
979 __in efx_nic_t *enp);
980
981typedef enum efx_phy_cap_type_e {
982 EFX_PHY_CAP_INVALID = 0,
983 EFX_PHY_CAP_10HDX,
984 EFX_PHY_CAP_10FDX,
985 EFX_PHY_CAP_100HDX,
986 EFX_PHY_CAP_100FDX,
987 EFX_PHY_CAP_1000HDX,
988 EFX_PHY_CAP_1000FDX,
989 EFX_PHY_CAP_10000FDX,
990 EFX_PHY_CAP_PAUSE,
991 EFX_PHY_CAP_ASYM,
992 EFX_PHY_CAP_AN,
993 EFX_PHY_CAP_40000FDX,
994 EFX_PHY_CAP_DDM,
995 EFX_PHY_CAP_100000FDX,
996 EFX_PHY_CAP_25000FDX,
997 EFX_PHY_CAP_50000FDX,
998 EFX_PHY_CAP_BASER_FEC,
999 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1000 EFX_PHY_CAP_RS_FEC,
1001 EFX_PHY_CAP_RS_FEC_REQUESTED,
1002 EFX_PHY_CAP_25G_BASER_FEC,
1003 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1004 EFX_PHY_CAP_NTYPES
1005} efx_phy_cap_type_t;
1006
1007
1008#define EFX_PHY_CAP_CURRENT 0x00000000
1009#define EFX_PHY_CAP_DEFAULT 0x00000001
1010#define EFX_PHY_CAP_PERM 0x00000002
1011
1012extern void
1013efx_phy_adv_cap_get(
1014 __in efx_nic_t *enp,
1015 __in uint32_t flag,
1016 __out uint32_t *maskp);
1017
1018extern __checkReturn efx_rc_t
1019efx_phy_adv_cap_set(
1020 __in efx_nic_t *enp,
1021 __in uint32_t mask);
1022
1023extern void
1024efx_phy_lp_cap_get(
1025 __in efx_nic_t *enp,
1026 __out uint32_t *maskp);
1027
1028extern __checkReturn efx_rc_t
1029efx_phy_oui_get(
1030 __in efx_nic_t *enp,
1031 __out uint32_t *ouip);
1032
1033typedef enum efx_phy_media_type_e {
1034 EFX_PHY_MEDIA_INVALID = 0,
1035 EFX_PHY_MEDIA_XAUI,
1036 EFX_PHY_MEDIA_CX4,
1037 EFX_PHY_MEDIA_KX4,
1038 EFX_PHY_MEDIA_XFP,
1039 EFX_PHY_MEDIA_SFP_PLUS,
1040 EFX_PHY_MEDIA_BASE_T,
1041 EFX_PHY_MEDIA_QSFP_PLUS,
1042 EFX_PHY_MEDIA_NTYPES
1043} efx_phy_media_type_t;
1044
1045/*
1046 * Get the type of medium currently used. If the board has ports for
1047 * modules, a module is present, and we recognise the media type of
1048 * the module, then this will be the media type of the module.
1049 * Otherwise it will be the media type of the port.
1050 */
1051extern void
1052efx_phy_media_type_get(
1053 __in efx_nic_t *enp,
1054 __out efx_phy_media_type_t *typep);
1055
9f95a23c
TL		 1056/*
1057 * 2-wire device address of the base information in accordance with SFF-8472
1058 * Diagnostic Monitoring Interface for Optical Transceivers section
1059 * 4 Memory Organization.
1060 */
1061#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1062
1063/*
1064 * 2-wire device address of the digital diagnostics monitoring interface
1065 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1066 * Transceivers section 4 Memory Organization.
1067 */
1068#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1069
1070/*
1071 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1072 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1073 * Operation.
1074 */
1075#define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1076
1077/*
1078 * Maximum accessible data offset for PHY module information.
1079 */
1080#define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1081
1082
11fdf7f2
TL		 1083extern __checkReturn efx_rc_t
1084efx_phy_module_get_info(
1085 __in efx_nic_t *enp,
1086 __in uint8_t dev_addr,
9f95a23c
TL		 1087 __in size_t offset,
1088 __in size_t len,
11fdf7f2
TL		 1089 __out_bcount(len) uint8_t *data);
1090
1091#if EFSYS_OPT_PHY_STATS
1092
1093/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1094typedef enum efx_phy_stat_e {
1095 EFX_PHY_STAT_OUI,
1096 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1097 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1098 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1099 EFX_PHY_STAT_PMA_PMD_REV_A,
1100 EFX_PHY_STAT_PMA_PMD_REV_B,
1101 EFX_PHY_STAT_PMA_PMD_REV_C,
1102 EFX_PHY_STAT_PMA_PMD_REV_D,
1103 EFX_PHY_STAT_PCS_LINK_UP,
1104 EFX_PHY_STAT_PCS_RX_FAULT,
1105 EFX_PHY_STAT_PCS_TX_FAULT,
1106 EFX_PHY_STAT_PCS_BER,
1107 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1108 EFX_PHY_STAT_PHY_XS_LINK_UP,
1109 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1110 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1111 EFX_PHY_STAT_PHY_XS_ALIGN,
1112 EFX_PHY_STAT_PHY_XS_SYNC_A,
1113 EFX_PHY_STAT_PHY_XS_SYNC_B,
1114 EFX_PHY_STAT_PHY_XS_SYNC_C,
1115 EFX_PHY_STAT_PHY_XS_SYNC_D,
1116 EFX_PHY_STAT_AN_LINK_UP,
1117 EFX_PHY_STAT_AN_MASTER,
1118 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1119 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1120 EFX_PHY_STAT_CL22EXT_LINK_UP,
1121 EFX_PHY_STAT_SNR_A,
1122 EFX_PHY_STAT_SNR_B,
1123 EFX_PHY_STAT_SNR_C,
1124 EFX_PHY_STAT_SNR_D,
1125 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1126 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1127 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1128 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1129 EFX_PHY_STAT_AN_COMPLETE,
1130 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1131 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1132 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1133 EFX_PHY_STAT_PCS_FW_VERSION_0,
1134 EFX_PHY_STAT_PCS_FW_VERSION_1,
1135 EFX_PHY_STAT_PCS_FW_VERSION_2,
1136 EFX_PHY_STAT_PCS_FW_VERSION_3,
1137 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1138 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1139 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1140 EFX_PHY_STAT_PCS_OP_MODE,
1141 EFX_PHY_NSTATS
1142} efx_phy_stat_t;
1143
1144/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1145
1146#if EFSYS_OPT_NAMES
1147
1148extern const char *
1149efx_phy_stat_name(
1150 __in efx_nic_t *enp,
1151 __in efx_phy_stat_t stat);
1152
1153#endif /* EFSYS_OPT_NAMES */
1154
1155#define EFX_PHY_STATS_SIZE 0x100
1156
1157extern __checkReturn efx_rc_t
1158efx_phy_stats_update(
1159 __in efx_nic_t *enp,
1160 __in efsys_mem_t *esmp,
1161 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1162
1163#endif /* EFSYS_OPT_PHY_STATS */
1164
1165
1166#if EFSYS_OPT_BIST
1167
1168typedef enum efx_bist_type_e {
1169 EFX_BIST_TYPE_UNKNOWN,
1170 EFX_BIST_TYPE_PHY_NORMAL,
1171 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1172 EFX_BIST_TYPE_PHY_CABLE_LONG,
1173 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1174 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1175 EFX_BIST_TYPE_REG, /* Test the register memories */
1176 EFX_BIST_TYPE_NTYPES,
1177} efx_bist_type_t;
1178
1179typedef enum efx_bist_result_e {
1180 EFX_BIST_RESULT_UNKNOWN,
1181 EFX_BIST_RESULT_RUNNING,
1182 EFX_BIST_RESULT_PASSED,
1183 EFX_BIST_RESULT_FAILED,
1184} efx_bist_result_t;
1185
1186typedef enum efx_phy_cable_status_e {
1187 EFX_PHY_CABLE_STATUS_OK,
1188 EFX_PHY_CABLE_STATUS_INVALID,
1189 EFX_PHY_CABLE_STATUS_OPEN,
1190 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1191 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1192 EFX_PHY_CABLE_STATUS_BUSY,
1193} efx_phy_cable_status_t;
1194
1195typedef enum efx_bist_value_e {
1196 EFX_BIST_PHY_CABLE_LENGTH_A,
1197 EFX_BIST_PHY_CABLE_LENGTH_B,
1198 EFX_BIST_PHY_CABLE_LENGTH_C,
1199 EFX_BIST_PHY_CABLE_LENGTH_D,
1200 EFX_BIST_PHY_CABLE_STATUS_A,
1201 EFX_BIST_PHY_CABLE_STATUS_B,
1202 EFX_BIST_PHY_CABLE_STATUS_C,
1203 EFX_BIST_PHY_CABLE_STATUS_D,
1204 EFX_BIST_FAULT_CODE,
1205 /*
1206 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1207 * response.
1208 */
1209 EFX_BIST_MEM_TEST,
1210 EFX_BIST_MEM_ADDR,
1211 EFX_BIST_MEM_BUS,
1212 EFX_BIST_MEM_EXPECT,
1213 EFX_BIST_MEM_ACTUAL,
1214 EFX_BIST_MEM_ECC,
1215 EFX_BIST_MEM_ECC_PARITY,
1216 EFX_BIST_MEM_ECC_FATAL,
1217 EFX_BIST_NVALUES,
1218} efx_bist_value_t;
1219
1220extern __checkReturn efx_rc_t
1221efx_bist_enable_offline(
1222 __in efx_nic_t *enp);
1223
1224extern __checkReturn efx_rc_t
1225efx_bist_start(
1226 __in efx_nic_t *enp,
1227 __in efx_bist_type_t type);
1228
1229extern __checkReturn efx_rc_t
1230efx_bist_poll(
1231 __in efx_nic_t *enp,
1232 __in efx_bist_type_t type,
1233 __out efx_bist_result_t *resultp,
1234 __out_opt uint32_t *value_maskp,
1235 __out_ecount_opt(count) unsigned long *valuesp,
1236 __in size_t count);
1237
1238extern void
1239efx_bist_stop(
1240 __in efx_nic_t *enp,
1241 __in efx_bist_type_t type);
1242
1243#endif /* EFSYS_OPT_BIST */
1244
1245#define EFX_FEATURE_IPV6 0x00000001
1246#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1247#define EFX_FEATURE_LINK_EVENTS 0x00000004
1248#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1249#define EFX_FEATURE_MCDI 0x00000020
1250#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1251#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1252#define EFX_FEATURE_TURBO 0x00000100
1253#define EFX_FEATURE_MCDI_DMA 0x00000200
1254#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1255#define EFX_FEATURE_PIO_BUFFERS 0x00000800
1256#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1257#define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1258#define EFX_FEATURE_PACKED_STREAM 0x00004000
9f95a23c 1259#define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
11fdf7f2
TL		 1260
1261typedef enum efx_tunnel_protocol_e {
1262 EFX_TUNNEL_PROTOCOL_NONE = 0,
1263 EFX_TUNNEL_PROTOCOL_VXLAN,
1264 EFX_TUNNEL_PROTOCOL_GENEVE,
1265 EFX_TUNNEL_PROTOCOL_NVGRE,
1266 EFX_TUNNEL_NPROTOS
1267} efx_tunnel_protocol_t;
1268
1269typedef enum efx_vi_window_shift_e {
1270 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1271 EFX_VI_WINDOW_SHIFT_8K = 13,
1272 EFX_VI_WINDOW_SHIFT_16K = 14,
1273 EFX_VI_WINDOW_SHIFT_64K = 16,
1274} efx_vi_window_shift_t;
1275
1276typedef struct efx_nic_cfg_s {
1277 uint32_t enc_board_type;
1278 uint32_t enc_phy_type;
1279#if EFSYS_OPT_NAMES
1280 char enc_phy_name[21];
1281#endif
1282 char enc_phy_revision[21];
1283 efx_mon_type_t enc_mon_type;
1284#if EFSYS_OPT_MON_STATS
1285 uint32_t enc_mon_stat_dma_buf_size;
1286 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1287#endif
1288 unsigned int enc_features;
1289 efx_vi_window_shift_t enc_vi_window_shift;
1290 uint8_t enc_mac_addr[6];
1291 uint8_t enc_port; /* PHY port number */
1292 uint32_t enc_intr_vec_base;
1293 uint32_t enc_intr_limit;
1294 uint32_t enc_evq_limit;
1295 uint32_t enc_txq_limit;
1296 uint32_t enc_rxq_limit;
9f95a23c
TL		 1297 uint32_t enc_evq_max_nevs;
1298 uint32_t enc_evq_min_nevs;
1299 uint32_t enc_rxq_max_ndescs;
1300 uint32_t enc_rxq_min_ndescs;
11fdf7f2 1301 uint32_t enc_txq_max_ndescs;
9f95a23c 1302 uint32_t enc_txq_min_ndescs;
11fdf7f2
TL		 1303 uint32_t enc_buftbl_limit;
1304 uint32_t enc_piobuf_limit;
1305 uint32_t enc_piobuf_size;
1306 uint32_t enc_piobuf_min_alloc_size;
1307 uint32_t enc_evq_timer_quantum_ns;
1308 uint32_t enc_evq_timer_max_us;
1309 uint32_t enc_clk_mult;
9f95a23c
TL		 1310 uint32_t enc_ev_desc_size;
1311 uint32_t enc_rx_desc_size;
1312 uint32_t enc_tx_desc_size;
11fdf7f2
TL		 1313 uint32_t enc_rx_prefix_size;
1314 uint32_t enc_rx_buf_align_start;
1315 uint32_t enc_rx_buf_align_end;
9f95a23c 1316#if EFSYS_OPT_RX_SCALE
11fdf7f2
TL		 1317 uint32_t enc_rx_scale_max_exclusive_contexts;
1318 /*
1319 * Mask of supported hash algorithms.
1320 * Hash algorithm types are used as the bit indices.
1321 */
1322 uint32_t enc_rx_scale_hash_alg_mask;
1323 /*
1324 * Indicates whether port numbers can be included to the
1325 * input data for hash computation.
1326 */
1327 boolean_t enc_rx_scale_l4_hash_supported;
1328 boolean_t enc_rx_scale_additional_modes_supported;
9f95a23c 1329#endif /* EFSYS_OPT_RX_SCALE */
11fdf7f2
TL		 1330#if EFSYS_OPT_LOOPBACK
1331 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1332#endif /* EFSYS_OPT_LOOPBACK */
1333#if EFSYS_OPT_PHY_FLAGS
1334 uint32_t enc_phy_flags_mask;
1335#endif /* EFSYS_OPT_PHY_FLAGS */
1336#if EFSYS_OPT_PHY_LED_CONTROL
1337 uint32_t enc_led_mask;
1338#endif /* EFSYS_OPT_PHY_LED_CONTROL */
1339#if EFSYS_OPT_PHY_STATS
1340 uint64_t enc_phy_stat_mask;
1341#endif /* EFSYS_OPT_PHY_STATS */
1342#if EFSYS_OPT_MCDI
1343 uint8_t enc_mcdi_mdio_channel;
1344#if EFSYS_OPT_PHY_STATS
1345 uint32_t enc_mcdi_phy_stat_mask;
1346#endif /* EFSYS_OPT_PHY_STATS */
1347#if EFSYS_OPT_MON_STATS
1348 uint32_t *enc_mcdi_sensor_maskp;
1349 uint32_t enc_mcdi_sensor_mask_size;
1350#endif /* EFSYS_OPT_MON_STATS */
1351#endif /* EFSYS_OPT_MCDI */
1352#if EFSYS_OPT_BIST
1353 uint32_t enc_bist_mask;
1354#endif /* EFSYS_OPT_BIST */
9f95a23c 1355#if EFX_OPTS_EF10()
11fdf7f2
TL		 1356 uint32_t enc_pf;
1357 uint32_t enc_vf;
1358 uint32_t enc_privilege_mask;
9f95a23c 1359#endif /* EFX_OPTS_EF10() */
11fdf7f2
TL		 1360 boolean_t enc_bug26807_workaround;
1361 boolean_t enc_bug35388_workaround;
1362 boolean_t enc_bug41750_workaround;
1363 boolean_t enc_bug61265_workaround;
9f95a23c 1364 boolean_t enc_bug61297_workaround;
11fdf7f2
TL		 1365 boolean_t enc_rx_batching_enabled;
1366 /* Maximum number of descriptors completed in an rx event. */
1367 uint32_t enc_rx_batch_max;
1368 /* Number of rx descriptors the hardware requires for a push. */
1369 uint32_t enc_rx_push_align;
1370 /* Maximum amount of data in DMA descriptor */
1371 uint32_t enc_tx_dma_desc_size_max;
1372 /*
1373 * Boundary which DMA descriptor data must not cross or 0 if no
1374 * limitation.
1375 */
1376 uint32_t enc_tx_dma_desc_boundary;
1377 /*
1378 * Maximum number of bytes into the packet the TCP header can start for
1379 * the hardware to apply TSO packet edits.
1380 */
1381 uint32_t enc_tx_tso_tcp_header_offset_limit;
1382 boolean_t enc_fw_assisted_tso_enabled;
1383 boolean_t enc_fw_assisted_tso_v2_enabled;
1384 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1385 /* Number of TSO contexts on the NIC (FATSOv2) */
1386 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1387 boolean_t enc_hw_tx_insert_vlan_enabled;
1388 /* Number of PFs on the NIC */
1389 uint32_t enc_hw_pf_count;
1390 /* Datapath firmware vadapter/vport/vswitch support */
1391 boolean_t enc_datapath_cap_evb;
f67539c2
TL		 1392 /* Datapath firmware vport reconfigure support */
1393 boolean_t enc_vport_reconfigure_supported;
11fdf7f2
TL		 1394 boolean_t enc_rx_disable_scatter_supported;
1395 boolean_t enc_allow_set_mac_with_installed_filters;
1396 boolean_t enc_enhanced_set_mac_supported;
1397 boolean_t enc_init_evq_v2_supported;
9f95a23c
TL		 1398 boolean_t enc_no_cont_ev_mode_supported;
1399 boolean_t enc_init_rxq_with_buffer_size;
11fdf7f2
TL		 1400 boolean_t enc_rx_packed_stream_supported;
1401 boolean_t enc_rx_var_packed_stream_supported;
1402 boolean_t enc_rx_es_super_buffer_supported;
1403 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1404 boolean_t enc_pm_and_rxdp_counters;
1405 boolean_t enc_mac_stats_40g_tx_size_bins;
1406 uint32_t enc_tunnel_encapsulations_supported;
1407 /*
1408 * NIC global maximum for unique UDP tunnel ports shared by all
1409 * functions.
1410 */
1411 uint32_t enc_tunnel_config_udp_entries_max;
1412 /* External port identifier */
1413 uint8_t enc_external_port;
1414 uint32_t enc_mcdi_max_payload_length;
1415 /* VPD may be per-PF or global */
1416 boolean_t enc_vpd_is_global;
1417 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1418 uint32_t enc_required_pcie_bandwidth_mbps;
1419 uint32_t enc_max_pcie_link_gen;
1420 /* Firmware verifies integrity of NVRAM updates */
f67539c2
TL		 1421 boolean_t enc_nvram_update_verify_result_supported;
1422 /* Firmware supports polled NVRAM updates on select partitions */
1423 boolean_t enc_nvram_update_poll_verify_result_supported;
1424 /* Firmware accepts updates via the BUNDLE partition */
1425 boolean_t enc_nvram_bundle_update_supported;
11fdf7f2
TL		 1426 /* Firmware support for extended MAC_STATS buffer */
1427 uint32_t enc_mac_stats_nstats;
1428 boolean_t enc_fec_counters;
1429 boolean_t enc_hlb_counters;
1430 /* Firmware support for "FLAG" and "MARK" filter actions */
1431 boolean_t enc_filter_action_flag_supported;
1432 boolean_t enc_filter_action_mark_supported;
1433 uint32_t enc_filter_action_mark_max;
f67539c2
TL		 1434 /* Port assigned to this PCI function */
1435 uint32_t enc_assigned_port;
11fdf7f2
TL		 1436} efx_nic_cfg_t;
1437
f67539c2
TL		 1438#define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1439 ((configp)->evc_function == 0xffff)
1440
11fdf7f2
TL		 1441#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1442#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1443
1444#define EFX_PCI_FUNCTION(_encp) \
1445 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1446
1447#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1448
1449extern const efx_nic_cfg_t *
1450efx_nic_cfg_get(
9f95a23c 1451 __in const efx_nic_t *enp);
11fdf7f2
TL		 1452
1453/* RxDPCPU firmware id values by which FW variant can be identified */
1454#define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1455#define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1456#define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1457#define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1458#define EFX_RXDP_DPDK_FW_ID 0x6
1459
1460typedef struct efx_nic_fw_info_s {
1461 /* Basic FW version information */
1462 uint16_t enfi_mc_fw_version[4];
1463 /*
1464 * If datapath capabilities can be detected,
1465 * additional FW information is to be shown
1466 */
1467 boolean_t enfi_dpcpu_fw_ids_valid;
1468 /* Rx and Tx datapath CPU FW IDs */
1469 uint16_t enfi_rx_dpcpu_fw_id;
1470 uint16_t enfi_tx_dpcpu_fw_id;
1471} efx_nic_fw_info_t;
1472
1473extern __checkReturn efx_rc_t
1474efx_nic_get_fw_version(
1475 __in efx_nic_t *enp,
1476 __out efx_nic_fw_info_t *enfip);
1477
1478/* Driver resource limits (minimum required/maximum usable). */
1479typedef struct efx_drv_limits_s {
1480 uint32_t edl_min_evq_count;
1481 uint32_t edl_max_evq_count;
1482
1483 uint32_t edl_min_rxq_count;
1484 uint32_t edl_max_rxq_count;
1485
1486 uint32_t edl_min_txq_count;
1487 uint32_t edl_max_txq_count;
1488
1489 /* PIO blocks (sub-allocated from piobuf) */
1490 uint32_t edl_min_pio_alloc_size;
1491 uint32_t edl_max_pio_alloc_count;
1492} efx_drv_limits_t;
1493
1494extern __checkReturn efx_rc_t
1495efx_nic_set_drv_limits(
1496 __inout efx_nic_t *enp,
1497 __in efx_drv_limits_t *edlp);
1498
f67539c2
TL		 1499/*
1500 * Register the OS driver version string for management agents
1501 * (e.g. via NC-SI). The content length is provided (i.e. no
1502 * NUL terminator). Use length 0 to indicate no version string
1503 * should be advertised. It is valid to set the version string
1504 * only before efx_nic_probe() is called.
1505 */
1506extern __checkReturn efx_rc_t
1507efx_nic_set_drv_version(
1508 __inout efx_nic_t *enp,
1509 __in_ecount(length) char const *verp,
1510 __in size_t length);
1511
11fdf7f2
TL		 1512typedef enum efx_nic_region_e {
1513 EFX_REGION_VI, /* Memory BAR UC mapping */
1514 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1515} efx_nic_region_t;
1516
1517extern __checkReturn efx_rc_t
1518efx_nic_get_bar_region(
1519 __in efx_nic_t *enp,
1520 __in efx_nic_region_t region,
1521 __out uint32_t *offsetp,
1522 __out size_t *sizep);
1523
1524extern __checkReturn efx_rc_t
1525efx_nic_get_vi_pool(
1526 __in efx_nic_t *enp,
1527 __out uint32_t *evq_countp,
1528 __out uint32_t *rxq_countp,
1529 __out uint32_t *txq_countp);
1530
1531
1532#if EFSYS_OPT_VPD
1533
1534typedef enum efx_vpd_tag_e {
1535 EFX_VPD_ID = 0x02,
1536 EFX_VPD_END = 0x0f,
1537 EFX_VPD_RO = 0x10,
1538 EFX_VPD_RW = 0x11,
1539} efx_vpd_tag_t;
1540
1541typedef uint16_t efx_vpd_keyword_t;
1542
1543typedef struct efx_vpd_value_s {
1544 efx_vpd_tag_t evv_tag;
1545 efx_vpd_keyword_t evv_keyword;
1546 uint8_t evv_length;
1547 uint8_t evv_value[0x100];
1548} efx_vpd_value_t;
1549
1550
1551#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1552
1553extern __checkReturn efx_rc_t
1554efx_vpd_init(
1555 __in efx_nic_t *enp);
1556
1557extern __checkReturn efx_rc_t
1558efx_vpd_size(
1559 __in efx_nic_t *enp,
1560 __out size_t *sizep);
1561
1562extern __checkReturn efx_rc_t
1563efx_vpd_read(
1564 __in efx_nic_t *enp,
1565 __out_bcount(size) caddr_t data,
1566 __in size_t size);
1567
1568extern __checkReturn efx_rc_t
1569efx_vpd_verify(
1570 __in efx_nic_t *enp,
1571 __in_bcount(size) caddr_t data,
1572 __in size_t size);
1573
1574extern __checkReturn efx_rc_t
1575efx_vpd_reinit(
1576 __in efx_nic_t *enp,
1577 __in_bcount(size) caddr_t data,
1578 __in size_t size);
1579
1580extern __checkReturn efx_rc_t
1581efx_vpd_get(
1582 __in efx_nic_t *enp,
1583 __in_bcount(size) caddr_t data,
1584 __in size_t size,
1585 __inout efx_vpd_value_t *evvp);
1586
1587extern __checkReturn efx_rc_t
1588efx_vpd_set(
1589 __in efx_nic_t *enp,
1590 __inout_bcount(size) caddr_t data,
1591 __in size_t size,
1592 __in efx_vpd_value_t *evvp);
1593
1594extern __checkReturn efx_rc_t
1595efx_vpd_next(
1596 __in efx_nic_t *enp,
1597 __inout_bcount(size) caddr_t data,
1598 __in size_t size,
1599 __out efx_vpd_value_t *evvp,
1600 __inout unsigned int *contp);
1601
1602extern __checkReturn efx_rc_t
1603efx_vpd_write(
1604 __in efx_nic_t *enp,
1605 __in_bcount(size) caddr_t data,
1606 __in size_t size);
1607
1608extern void
1609efx_vpd_fini(
1610 __in efx_nic_t *enp);
1611
1612#endif /* EFSYS_OPT_VPD */
1613
1614/* NVRAM */
1615
1616#if EFSYS_OPT_NVRAM
1617
1618typedef enum efx_nvram_type_e {
1619 EFX_NVRAM_INVALID = 0,
1620 EFX_NVRAM_BOOTROM,
1621 EFX_NVRAM_BOOTROM_CFG,
1622 EFX_NVRAM_MC_FIRMWARE,
1623 EFX_NVRAM_MC_GOLDEN,
1624 EFX_NVRAM_PHY,
1625 EFX_NVRAM_NULLPHY,
1626 EFX_NVRAM_FPGA,
1627 EFX_NVRAM_FCFW,
1628 EFX_NVRAM_CPLD,
1629 EFX_NVRAM_FPGA_BACKUP,
1630 EFX_NVRAM_DYNAMIC_CFG,
1631 EFX_NVRAM_LICENSE,
1632 EFX_NVRAM_UEFIROM,
1633 EFX_NVRAM_MUM_FIRMWARE,
9f95a23c
TL		 1634 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1635 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1636 EFX_NVRAM_BUNDLE,
f67539c2 1637 EFX_NVRAM_BUNDLE_METADATA,
11fdf7f2
TL		 1638 EFX_NVRAM_NTYPES,
1639} efx_nvram_type_t;
1640
f67539c2
TL		 1641typedef struct efx_nvram_info_s {
1642 uint32_t eni_flags;
1643 uint32_t eni_partn_size;
1644 uint32_t eni_address;
1645 uint32_t eni_erase_size;
1646 uint32_t eni_write_size;
1647} efx_nvram_info_t;
1648
1649#define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1650
11fdf7f2
TL		 1651extern __checkReturn efx_rc_t
1652efx_nvram_init(
1653 __in efx_nic_t *enp);
1654
1655#if EFSYS_OPT_DIAG
1656
1657extern __checkReturn efx_rc_t
1658efx_nvram_test(
1659 __in efx_nic_t *enp);
1660
1661#endif /* EFSYS_OPT_DIAG */
1662
1663extern __checkReturn efx_rc_t
1664efx_nvram_size(
1665 __in efx_nic_t *enp,
1666 __in efx_nvram_type_t type,
1667 __out size_t *sizep);
1668
f67539c2
TL		 1669extern __checkReturn efx_rc_t
1670efx_nvram_info(
1671 __in efx_nic_t *enp,
1672 __in efx_nvram_type_t type,
1673 __out efx_nvram_info_t *enip);
1674
11fdf7f2
TL		 1675extern __checkReturn efx_rc_t
1676efx_nvram_rw_start(
1677 __in efx_nic_t *enp,
1678 __in efx_nvram_type_t type,
1679 __out_opt size_t *pref_chunkp);
1680
1681extern __checkReturn efx_rc_t
1682efx_nvram_rw_finish(
1683 __in efx_nic_t *enp,
1684 __in efx_nvram_type_t type,
1685 __out_opt uint32_t *verify_resultp);
1686
1687extern __checkReturn efx_rc_t
1688efx_nvram_get_version(
1689 __in efx_nic_t *enp,
1690 __in efx_nvram_type_t type,
1691 __out uint32_t *subtypep,
1692 __out_ecount(4) uint16_t version[4]);
1693
1694extern __checkReturn efx_rc_t
1695efx_nvram_read_chunk(
1696 __in efx_nic_t *enp,
1697 __in efx_nvram_type_t type,
1698 __in unsigned int offset,
1699 __out_bcount(size) caddr_t data,
1700 __in size_t size);
1701
1702extern __checkReturn efx_rc_t
1703efx_nvram_read_backup(
1704 __in efx_nic_t *enp,
1705 __in efx_nvram_type_t type,
1706 __in unsigned int offset,
1707 __out_bcount(size) caddr_t data,
1708 __in size_t size);
1709
1710extern __checkReturn efx_rc_t
1711efx_nvram_set_version(
1712 __in efx_nic_t *enp,
1713 __in efx_nvram_type_t type,
1714 __in_ecount(4) uint16_t version[4]);
1715
1716extern __checkReturn efx_rc_t
1717efx_nvram_validate(
1718 __in efx_nic_t *enp,
1719 __in efx_nvram_type_t type,
1720 __in_bcount(partn_size) caddr_t partn_data,
1721 __in size_t partn_size);
1722
1723extern __checkReturn efx_rc_t
1724efx_nvram_erase(
1725 __in efx_nic_t *enp,
1726 __in efx_nvram_type_t type);
1727
1728extern __checkReturn efx_rc_t
1729efx_nvram_write_chunk(
1730 __in efx_nic_t *enp,
1731 __in efx_nvram_type_t type,
1732 __in unsigned int offset,
1733 __in_bcount(size) caddr_t data,
1734 __in size_t size);
1735
1736extern void
1737efx_nvram_fini(
1738 __in efx_nic_t *enp);
1739
1740#endif /* EFSYS_OPT_NVRAM */
1741
1742#if EFSYS_OPT_BOOTCFG
1743
1744/* Report size and offset of bootcfg sector in NVRAM partition. */
1745extern __checkReturn efx_rc_t
1746efx_bootcfg_sector_info(
1747 __in efx_nic_t *enp,
1748 __in uint32_t pf,
1749 __out_opt uint32_t *sector_countp,
1750 __out size_t *offsetp,
1751 __out size_t *max_sizep);
1752
1753/*
1754 * Copy bootcfg sector data to a target buffer which may differ in size.
1755 * Optionally corrects format errors in source buffer.
1756 */
1757extern efx_rc_t
1758efx_bootcfg_copy_sector(
1759 __in efx_nic_t *enp,
1760 __inout_bcount(sector_length)
1761 uint8_t *sector,
1762 __in size_t sector_length,
1763 __out_bcount(data_size) uint8_t *data,
1764 __in size_t data_size,
1765 __in boolean_t handle_format_errors);
1766
1767extern efx_rc_t
1768efx_bootcfg_read(
1769 __in efx_nic_t *enp,
1770 __out_bcount(size) uint8_t *data,
1771 __in size_t size);
1772
1773extern efx_rc_t
1774efx_bootcfg_write(
1775 __in efx_nic_t *enp,
1776 __in_bcount(size) uint8_t *data,
1777 __in size_t size);
1778
9f95a23c
TL		 1779
1780/*
1781 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1782 * (see https://tools.ietf.org/html/rfc1533)
1783 *
1784 * Summarising the format: the buffer is a sequence of options. All options
1785 * begin with a tag octet, which uniquely identifies the option. Fixed-
1786 * length options without data consist of only a tag octet. Only options PAD
1787 * (0) and END (255) are fixed length. All other options are variable-length
1788 * with a length octet following the tag octet. The value of the length
1789 * octet does not include the two octets specifying the tag and length. The
1790 * length octet is followed by "length" octets of data.
1791 *
1792 * Option data may be a sequence of sub-options in the same format. The data
1793 * content of the encapsulating option is one or more encapsulated sub-options,
1794 * with no terminating END tag is required.
1795 *
1796 * To be valid, the top-level sequence of options should be terminated by an
1797 * END tag. The buffer should be padded with the PAD byte.
1798 *
1799 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1800 * checksum octet. The full buffer (including after the END tag) contributes
1801 * to the checksum, hence the need to fill the buffer to the end with PAD.
1802 */
1803
1804#define EFX_DHCP_END ((uint8_t)0xff)
1805#define EFX_DHCP_PAD ((uint8_t)0)
1806
1807#define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1808 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1809
1810extern __checkReturn uint8_t
1811efx_dhcp_csum(
1812 __in_bcount(size) uint8_t const *data,
1813 __in size_t size);
1814
1815extern __checkReturn efx_rc_t
1816efx_dhcp_verify(
1817 __in_bcount(size) uint8_t const *data,
1818 __in size_t size,
1819 __out_opt size_t *usedp);
1820
1821extern __checkReturn efx_rc_t
1822efx_dhcp_find_tag(
1823 __in_bcount(buffer_length) uint8_t *bufferp,
1824 __in size_t buffer_length,
1825 __in uint16_t opt,
1826 __deref_out uint8_t **valuepp,
1827 __out size_t *value_lengthp);
1828
1829extern __checkReturn efx_rc_t
1830efx_dhcp_find_end(
1831 __in_bcount(buffer_length) uint8_t *bufferp,
1832 __in size_t buffer_length,
1833 __deref_out uint8_t **endpp);
1834
1835
1836extern __checkReturn efx_rc_t
1837efx_dhcp_delete_tag(
1838 __inout_bcount(buffer_length) uint8_t *bufferp,
1839 __in size_t buffer_length,
1840 __in uint16_t opt);
1841
1842extern __checkReturn efx_rc_t
1843efx_dhcp_add_tag(
1844 __inout_bcount(buffer_length) uint8_t *bufferp,
1845 __in size_t buffer_length,
1846 __in uint16_t opt,
1847 __in_bcount_opt(value_length) uint8_t *valuep,
1848 __in size_t value_length);
1849
1850extern __checkReturn efx_rc_t
1851efx_dhcp_update_tag(
1852 __inout_bcount(buffer_length) uint8_t *bufferp,
1853 __in size_t buffer_length,
1854 __in uint16_t opt,
1855 __in uint8_t *value_locationp,
1856 __in_bcount_opt(value_length) uint8_t *valuep,
1857 __in size_t value_length);
1858
1859
11fdf7f2
TL		 1860#endif /* EFSYS_OPT_BOOTCFG */
1861
1862#if EFSYS_OPT_IMAGE_LAYOUT
1863
1864#include "ef10_signed_image_layout.h"
1865
1866/*
1867 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1868 *
1869 * NOTE:
1870 * The image header format is extensible. However, older drivers require an
1871 * exact match of image header version and header length when validating and
1872 * writing firmware images.
1873 *
1874 * To avoid breaking backward compatibility, we use the upper bits of the
1875 * controller version fields to contain an extra version number used for
1876 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1877 * version). See bug39254 and SF-102785-PS for details.
1878 */
1879typedef struct efx_image_header_s {
1880 uint32_t eih_magic;
1881 uint32_t eih_version;
1882 uint32_t eih_type;
1883 uint32_t eih_subtype;
1884 uint32_t eih_code_size;
1885 uint32_t eih_size;
1886 union {
1887 uint32_t eih_controller_version_min;
1888 struct {
1889 uint16_t eih_controller_version_min_short;
1890 uint8_t eih_extra_version_a;
1891 uint8_t eih_extra_version_b;
1892 };
1893 };
1894 union {
1895 uint32_t eih_controller_version_max;
1896 struct {
1897 uint16_t eih_controller_version_max_short;
1898 uint8_t eih_extra_version_c;
1899 uint8_t eih_extra_version_d;
1900 };
1901 };
1902 uint16_t eih_code_version_a;
1903 uint16_t eih_code_version_b;
1904 uint16_t eih_code_version_c;
1905 uint16_t eih_code_version_d;
1906} efx_image_header_t;
1907
1908#define EFX_IMAGE_HEADER_SIZE (40)
1909#define EFX_IMAGE_HEADER_VERSION (4)
1910#define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1911
1912
1913typedef struct efx_image_trailer_s {
1914 uint32_t eit_crc;
1915} efx_image_trailer_t;
1916
1917#define EFX_IMAGE_TRAILER_SIZE (4)
1918
1919typedef enum efx_image_format_e {
1920 EFX_IMAGE_FORMAT_NO_IMAGE,
1921 EFX_IMAGE_FORMAT_INVALID,
1922 EFX_IMAGE_FORMAT_UNSIGNED,
1923 EFX_IMAGE_FORMAT_SIGNED,
f67539c2 1924 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
11fdf7f2
TL		 1925} efx_image_format_t;
1926
1927typedef struct efx_image_info_s {
1928 efx_image_format_t eii_format;
1929 uint8_t * eii_imagep;
1930 size_t eii_image_size;
1931 efx_image_header_t * eii_headerp;
1932} efx_image_info_t;
1933
1934extern __checkReturn efx_rc_t
1935efx_check_reflash_image(
1936 __in void *bufferp,
1937 __in uint32_t buffer_size,
1938 __out efx_image_info_t *infop);
1939
1940extern __checkReturn efx_rc_t
1941efx_build_signed_image_write_buffer(
9f95a23c
TL		 1942 __out_bcount(buffer_size)
1943 uint8_t *bufferp,
11fdf7f2
TL		 1944 __in uint32_t buffer_size,
1945 __in efx_image_info_t *infop,
1946 __out efx_image_header_t **headerpp);
1947
1948#endif /* EFSYS_OPT_IMAGE_LAYOUT */
1949
1950#if EFSYS_OPT_DIAG
1951
1952typedef enum efx_pattern_type_t {
1953 EFX_PATTERN_BYTE_INCREMENT = 0,
1954 EFX_PATTERN_ALL_THE_SAME,
1955 EFX_PATTERN_BIT_ALTERNATE,
1956 EFX_PATTERN_BYTE_ALTERNATE,
1957 EFX_PATTERN_BYTE_CHANGING,
1958 EFX_PATTERN_BIT_SWEEP,
1959 EFX_PATTERN_NTYPES
1960} efx_pattern_type_t;
1961
1962typedef void
1963(*efx_sram_pattern_fn_t)(
1964 __in size_t row,
1965 __in boolean_t negate,
1966 __out efx_qword_t *eqp);
1967
1968extern __checkReturn efx_rc_t
1969efx_sram_test(
1970 __in efx_nic_t *enp,
1971 __in efx_pattern_type_t type);
1972
1973#endif /* EFSYS_OPT_DIAG */
1974
1975extern __checkReturn efx_rc_t
1976efx_sram_buf_tbl_set(
1977 __in efx_nic_t *enp,
1978 __in uint32_t id,
1979 __in efsys_mem_t *esmp,
1980 __in size_t n);
1981
1982extern void
1983efx_sram_buf_tbl_clear(
1984 __in efx_nic_t *enp,
1985 __in uint32_t id,
1986 __in size_t n);
1987
1988#define EFX_BUF_TBL_SIZE 0x20000
1989
1990#define EFX_BUF_SIZE 4096
1991
1992/* EV */
1993
1994typedef struct efx_evq_s efx_evq_t;
1995
1996#if EFSYS_OPT_QSTATS
1997
9f95a23c 1998/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
11fdf7f2
TL		 1999typedef enum efx_ev_qstat_e {
2000 EV_ALL,
2001 EV_RX,
2002 EV_RX_OK,
2003 EV_RX_FRM_TRUNC,
2004 EV_RX_TOBE_DISC,
2005 EV_RX_PAUSE_FRM_ERR,
2006 EV_RX_BUF_OWNER_ID_ERR,
2007 EV_RX_IPV4_HDR_CHKSUM_ERR,
2008 EV_RX_TCP_UDP_CHKSUM_ERR,
2009 EV_RX_ETH_CRC_ERR,
2010 EV_RX_IP_FRAG_ERR,
2011 EV_RX_MCAST_PKT,
2012 EV_RX_MCAST_HASH_MATCH,
2013 EV_RX_TCP_IPV4,
2014 EV_RX_TCP_IPV6,
2015 EV_RX_UDP_IPV4,
2016 EV_RX_UDP_IPV6,
2017 EV_RX_OTHER_IPV4,
2018 EV_RX_OTHER_IPV6,
2019 EV_RX_NON_IP,
2020 EV_RX_BATCH,
2021 EV_TX,
2022 EV_TX_WQ_FF_FULL,
2023 EV_TX_PKT_ERR,
2024 EV_TX_PKT_TOO_BIG,
2025 EV_TX_UNEXPECTED,
2026 EV_GLOBAL,
2027 EV_GLOBAL_MNT,
2028 EV_DRIVER,
2029 EV_DRIVER_SRM_UPD_DONE,
2030 EV_DRIVER_TX_DESCQ_FLS_DONE,
2031 EV_DRIVER_RX_DESCQ_FLS_DONE,
2032 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2033 EV_DRIVER_RX_DSC_ERROR,
2034 EV_DRIVER_TX_DSC_ERROR,
2035 EV_DRV_GEN,
2036 EV_MCDI_RESPONSE,
9f95a23c 2037 EV_RX_PARSE_INCOMPLETE,
11fdf7f2
TL		 2038 EV_NQSTATS
2039} efx_ev_qstat_t;
2040
2041/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2042
2043#endif /* EFSYS_OPT_QSTATS */
2044
2045extern __checkReturn efx_rc_t
2046efx_ev_init(
2047 __in efx_nic_t *enp);
2048
2049extern void
2050efx_ev_fini(
2051 __in efx_nic_t *enp);
2052
9f95a23c
TL		 2053extern __checkReturn size_t
2054efx_evq_size(
2055 __in const efx_nic_t *enp,
2056 __in unsigned int ndescs);
11fdf7f2 2057
9f95a23c
TL		 2058extern __checkReturn unsigned int
2059efx_evq_nbufs(
2060 __in const efx_nic_t *enp,
2061 __in unsigned int ndescs);
11fdf7f2
TL		 2062
2063#define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2064#define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2065#define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2066#define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2067
2068#define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2069#define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2070#define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2071
9f95a23c
TL		 2072/*
2073 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2074 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2075 * NO_CONT_EV mode".
2076 *
2077 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2078 * which is the case when an event queue is set to THROUGHPUT mode.
2079 */
2080#define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2081
11fdf7f2
TL		 2082extern __checkReturn efx_rc_t
2083efx_ev_qcreate(
2084 __in efx_nic_t *enp,
2085 __in unsigned int index,
2086 __in efsys_mem_t *esmp,
2087 __in size_t ndescs,
2088 __in uint32_t id,
2089 __in uint32_t us,
2090 __in uint32_t flags,
2091 __deref_out efx_evq_t **eepp);
2092
2093extern void
2094efx_ev_qpost(
2095 __in efx_evq_t *eep,
2096 __in uint16_t data);
2097
2098typedef __checkReturn boolean_t
2099(*efx_initialized_ev_t)(
2100 __in_opt void *arg);
2101
2102#define EFX_PKT_UNICAST 0x0004
2103#define EFX_PKT_START 0x0008
2104
2105#define EFX_PKT_VLAN_TAGGED 0x0010
2106#define EFX_CKSUM_TCPUDP 0x0020
2107#define EFX_CKSUM_IPV4 0x0040
2108#define EFX_PKT_CONT 0x0080
2109
2110#define EFX_CHECK_VLAN 0x0100
2111#define EFX_PKT_TCP 0x0200
2112#define EFX_PKT_UDP 0x0400
2113#define EFX_PKT_IPV4 0x0800
2114
2115#define EFX_PKT_IPV6 0x1000
2116#define EFX_PKT_PREFIX_LEN 0x2000
2117#define EFX_ADDR_MISMATCH 0x4000
2118#define EFX_DISCARD 0x8000
2119
2120/*
2121 * The following flags are used only for packed stream
2122 * mode. The values for the flags are reused to fit into 16 bit,
2123 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2124 * packed stream mode
2125 */
2126#define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2127#define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2128
2129
2130#define EFX_EV_RX_NLABELS 32
2131#define EFX_EV_TX_NLABELS 32
2132
2133typedef __checkReturn boolean_t
2134(*efx_rx_ev_t)(
2135 __in_opt void *arg,
2136 __in uint32_t label,
2137 __in uint32_t id,
2138 __in uint32_t size,
2139 __in uint16_t flags);
2140
2141#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2142
2143/*
2144 * Packed stream mode is documented in SF-112241-TC.
2145 * The general idea is that, instead of putting each incoming
2146 * packet into a separate buffer which is specified in a RX
2147 * descriptor, a large buffer is provided to the hardware and
2148 * packets are put there in a continuous stream.
2149 * The main advantage of such an approach is that RX queue refilling
2150 * happens much less frequently.
2151 *
2152 * Equal stride packed stream mode is documented in SF-119419-TC.
2153 * The general idea is to utilize advantages of the packed stream,
2154 * but avoid indirection in packets representation.
2155 * The main advantage of such an approach is that RX queue refilling
2156 * happens much less frequently and packets buffers are independent
2157 * from upper layers point of view.
2158 */
2159
2160typedef __checkReturn boolean_t
2161(*efx_rx_ps_ev_t)(
2162 __in_opt void *arg,
2163 __in uint32_t label,
2164 __in uint32_t id,
2165 __in uint32_t pkt_count,
2166 __in uint16_t flags);
2167
2168#endif
2169
2170typedef __checkReturn boolean_t
2171(*efx_tx_ev_t)(
2172 __in_opt void *arg,
2173 __in uint32_t label,
2174 __in uint32_t id);
2175
2176#define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2177#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2178#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2179#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2180#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2181#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2182#define EFX_EXCEPTION_RX_ERROR 0x00000007
2183#define EFX_EXCEPTION_TX_ERROR 0x00000008
2184#define EFX_EXCEPTION_EV_ERROR 0x00000009
2185
2186typedef __checkReturn boolean_t
2187(*efx_exception_ev_t)(
2188 __in_opt void *arg,
2189 __in uint32_t label,
2190 __in uint32_t data);
2191
2192typedef __checkReturn boolean_t
2193(*efx_rxq_flush_done_ev_t)(
2194 __in_opt void *arg,
2195 __in uint32_t rxq_index);
2196
2197typedef __checkReturn boolean_t
2198(*efx_rxq_flush_failed_ev_t)(
2199 __in_opt void *arg,
2200 __in uint32_t rxq_index);
2201
2202typedef __checkReturn boolean_t
2203(*efx_txq_flush_done_ev_t)(
2204 __in_opt void *arg,
2205 __in uint32_t txq_index);
2206
2207typedef __checkReturn boolean_t
2208(*efx_software_ev_t)(
2209 __in_opt void *arg,
2210 __in uint16_t magic);
2211
2212typedef __checkReturn boolean_t
2213(*efx_sram_ev_t)(
2214 __in_opt void *arg,
2215 __in uint32_t code);
2216
2217#define EFX_SRAM_CLEAR 0
2218#define EFX_SRAM_UPDATE 1
2219#define EFX_SRAM_ILLEGAL_CLEAR 2
2220
2221typedef __checkReturn boolean_t
2222(*efx_wake_up_ev_t)(
2223 __in_opt void *arg,
2224 __in uint32_t label);
2225
2226typedef __checkReturn boolean_t
2227(*efx_timer_ev_t)(
2228 __in_opt void *arg,
2229 __in uint32_t label);
2230
2231typedef __checkReturn boolean_t
2232(*efx_link_change_ev_t)(
2233 __in_opt void *arg,
2234 __in efx_link_mode_t link_mode);
2235
2236#if EFSYS_OPT_MON_STATS
2237
2238typedef __checkReturn boolean_t
2239(*efx_monitor_ev_t)(
2240 __in_opt void *arg,
2241 __in efx_mon_stat_t id,
2242 __in efx_mon_stat_value_t value);
2243
2244#endif /* EFSYS_OPT_MON_STATS */
2245
2246#if EFSYS_OPT_MAC_STATS
2247
2248typedef __checkReturn boolean_t
2249(*efx_mac_stats_ev_t)(
2250 __in_opt void *arg,
2251 __in uint32_t generation);
2252
2253#endif /* EFSYS_OPT_MAC_STATS */
2254
2255typedef struct efx_ev_callbacks_s {
2256 efx_initialized_ev_t eec_initialized;
2257 efx_rx_ev_t eec_rx;
2258#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2259 efx_rx_ps_ev_t eec_rx_ps;
2260#endif
2261 efx_tx_ev_t eec_tx;
2262 efx_exception_ev_t eec_exception;
2263 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2264 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2265 efx_txq_flush_done_ev_t eec_txq_flush_done;
2266 efx_software_ev_t eec_software;
2267 efx_sram_ev_t eec_sram;
2268 efx_wake_up_ev_t eec_wake_up;
2269 efx_timer_ev_t eec_timer;
2270 efx_link_change_ev_t eec_link_change;
2271#if EFSYS_OPT_MON_STATS
2272 efx_monitor_ev_t eec_monitor;
2273#endif /* EFSYS_OPT_MON_STATS */
2274#if EFSYS_OPT_MAC_STATS
2275 efx_mac_stats_ev_t eec_mac_stats;
2276#endif /* EFSYS_OPT_MAC_STATS */
2277} efx_ev_callbacks_t;
2278
2279extern __checkReturn boolean_t
2280efx_ev_qpending(
2281 __in efx_evq_t *eep,
2282 __in unsigned int count);
2283
2284#if EFSYS_OPT_EV_PREFETCH
2285
2286extern void
2287efx_ev_qprefetch(
2288 __in efx_evq_t *eep,
2289 __in unsigned int count);
2290
2291#endif /* EFSYS_OPT_EV_PREFETCH */
2292
2293extern void
2294efx_ev_qpoll(
2295 __in efx_evq_t *eep,
2296 __inout unsigned int *countp,
2297 __in const efx_ev_callbacks_t *eecp,
2298 __in_opt void *arg);
2299
2300extern __checkReturn efx_rc_t
2301efx_ev_usecs_to_ticks(
2302 __in efx_nic_t *enp,
2303 __in unsigned int usecs,
2304 __out unsigned int *ticksp);
2305
2306extern __checkReturn efx_rc_t
2307efx_ev_qmoderate(
2308 __in efx_evq_t *eep,
2309 __in unsigned int us);
2310
2311extern __checkReturn efx_rc_t
2312efx_ev_qprime(
2313 __in efx_evq_t *eep,
2314 __in unsigned int count);
2315
2316#if EFSYS_OPT_QSTATS
2317
2318#if EFSYS_OPT_NAMES
2319
2320extern const char *
2321efx_ev_qstat_name(
2322 __in efx_nic_t *enp,
2323 __in unsigned int id);
2324
2325#endif /* EFSYS_OPT_NAMES */
2326
2327extern void
2328efx_ev_qstats_update(
2329 __in efx_evq_t *eep,
2330 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2331
2332#endif /* EFSYS_OPT_QSTATS */
2333
2334extern void
2335efx_ev_qdestroy(
2336 __in efx_evq_t *eep);
2337
2338/* RX */
2339
2340extern __checkReturn efx_rc_t
2341efx_rx_init(
2342 __inout efx_nic_t *enp);
2343
2344extern void
2345efx_rx_fini(
2346 __in efx_nic_t *enp);
2347
2348#if EFSYS_OPT_RX_SCATTER
2349 __checkReturn efx_rc_t
2350efx_rx_scatter_enable(
2351 __in efx_nic_t *enp,
2352 __in unsigned int buf_size);
2353#endif /* EFSYS_OPT_RX_SCATTER */
2354
2355/* Handle to represent use of the default RSS context. */
2356#define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2357
2358#if EFSYS_OPT_RX_SCALE
2359
2360typedef enum efx_rx_hash_alg_e {
2361 EFX_RX_HASHALG_LFSR = 0,
2362 EFX_RX_HASHALG_TOEPLITZ,
2363 EFX_RX_HASHALG_PACKED_STREAM,
2364 EFX_RX_NHASHALGS
2365} efx_rx_hash_alg_t;
2366
2367/*
2368 * Legacy hash type flags.
2369 *
2370 * They represent standard tuples for distinct traffic classes.
2371 */
2372#define EFX_RX_HASH_IPV4 (1U << 0)
2373#define EFX_RX_HASH_TCPIPV4 (1U << 1)
2374#define EFX_RX_HASH_IPV6 (1U << 2)
2375#define EFX_RX_HASH_TCPIPV6 (1U << 3)
2376
2377#define EFX_RX_HASH_LEGACY_MASK \
2378 (EFX_RX_HASH_IPV4 | \
2379 EFX_RX_HASH_TCPIPV4 | \
2380 EFX_RX_HASH_IPV6 | \
2381 EFX_RX_HASH_TCPIPV6)
2382
2383/*
2384 * The type of the argument used by efx_rx_scale_mode_set() to
2385 * provide a means for the client drivers to configure hashing.
2386 *
2387 * A properly constructed value can either be:
2388 * - a combination of legacy flags
2389 * - a combination of EFX_RX_HASH() flags
2390 */
9f95a23c 2391typedef uint32_t efx_rx_hash_type_t;
11fdf7f2
TL		 2392
2393typedef enum efx_rx_hash_support_e {
2394 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2395 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2396} efx_rx_hash_support_t;
2397
2398#define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2399#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2400#define EFX_MAXRSS 64 /* RX indirection entry range */
2401#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2402
2403typedef enum efx_rx_scale_context_type_e {
2404 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2405 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2406 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2407} efx_rx_scale_context_type_t;
2408
2409/*
2410 * Traffic classes eligible for hash computation.
2411 *
2412 * Select packet headers used in computing the receive hash.
2413 * This uses the same encoding as the RSS_MODES field of
2414 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2415 */
2416#define EFX_RX_CLASS_IPV4_TCP_LBN 8
2417#define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2418#define EFX_RX_CLASS_IPV4_UDP_LBN 12
2419#define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2420#define EFX_RX_CLASS_IPV4_LBN 16
2421#define EFX_RX_CLASS_IPV4_WIDTH 4
2422#define EFX_RX_CLASS_IPV6_TCP_LBN 20
2423#define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2424#define EFX_RX_CLASS_IPV6_UDP_LBN 24
2425#define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2426#define EFX_RX_CLASS_IPV6_LBN 28
2427#define EFX_RX_CLASS_IPV6_WIDTH 4
2428
2429#define EFX_RX_NCLASSES 6
2430
2431/*
2432 * Ancillary flags used to construct generic hash tuples.
2433 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2434 */
2435#define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2436#define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2437#define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2438#define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2439
2440/*
2441 * Generic hash tuples.
2442 *
2443 * They express combinations of packet fields
2444 * which can contribute to the hash value for
2445 * a particular traffic class.
2446 */
2447#define EFX_RX_CLASS_HASH_DISABLE 0
2448
2449#define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2450#define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2451
2452#define EFX_RX_CLASS_HASH_2TUPLE \
2453 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2454 EFX_RX_CLASS_HASH_DST_ADDR)
2455
2456#define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2457 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2458 EFX_RX_CLASS_HASH_SRC_PORT)
2459
2460#define EFX_RX_CLASS_HASH_2TUPLE_DST \
2461 (EFX_RX_CLASS_HASH_DST_ADDR | \
2462 EFX_RX_CLASS_HASH_DST_PORT)
2463
2464#define EFX_RX_CLASS_HASH_4TUPLE \
2465 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2466 EFX_RX_CLASS_HASH_DST_ADDR | \
2467 EFX_RX_CLASS_HASH_SRC_PORT | \
2468 EFX_RX_CLASS_HASH_DST_PORT)
2469
2470#define EFX_RX_CLASS_HASH_NTUPLES 7
2471
2472/*
2473 * Hash flag constructor.
2474 *
2475 * Resulting flags encode hash tuples for specific traffic classes.
2476 * The client drivers are encouraged to use these flags to form
2477 * a hash type value.
2478 */
2479#define EFX_RX_HASH(_class, _tuple) \
2480 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2481 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2482
2483/*
2484 * The maximum number of EFX_RX_HASH() flags.
2485 */
2486#define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2487
2488extern __checkReturn efx_rc_t
2489efx_rx_scale_hash_flags_get(
2490 __in efx_nic_t *enp,
2491 __in efx_rx_hash_alg_t hash_alg,
9f95a23c
TL		 2492 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2493 __in unsigned int max_nflags,
11fdf7f2
TL		 2494 __out unsigned int *nflagsp);
2495
2496extern __checkReturn efx_rc_t
2497efx_rx_hash_default_support_get(
2498 __in efx_nic_t *enp,
2499 __out efx_rx_hash_support_t *supportp);
2500
2501
2502extern __checkReturn efx_rc_t
2503efx_rx_scale_default_support_get(
2504 __in efx_nic_t *enp,
2505 __out efx_rx_scale_context_type_t *typep);
2506
2507extern __checkReturn efx_rc_t
2508efx_rx_scale_context_alloc(
2509 __in efx_nic_t *enp,
2510 __in efx_rx_scale_context_type_t type,
2511 __in uint32_t num_queues,
2512 __out uint32_t *rss_contextp);
2513
2514extern __checkReturn efx_rc_t
2515efx_rx_scale_context_free(
2516 __in efx_nic_t *enp,
2517 __in uint32_t rss_context);
2518
2519extern __checkReturn efx_rc_t
2520efx_rx_scale_mode_set(
2521 __in efx_nic_t *enp,
2522 __in uint32_t rss_context,
2523 __in efx_rx_hash_alg_t alg,
2524 __in efx_rx_hash_type_t type,
2525 __in boolean_t insert);
2526
2527extern __checkReturn efx_rc_t
2528efx_rx_scale_tbl_set(
2529 __in efx_nic_t *enp,
2530 __in uint32_t rss_context,
2531 __in_ecount(n) unsigned int *table,
2532 __in size_t n);
2533
2534extern __checkReturn efx_rc_t
2535efx_rx_scale_key_set(
2536 __in efx_nic_t *enp,
2537 __in uint32_t rss_context,
2538 __in_ecount(n) uint8_t *key,
2539 __in size_t n);
2540
2541extern __checkReturn uint32_t
2542efx_pseudo_hdr_hash_get(
2543 __in efx_rxq_t *erp,
2544 __in efx_rx_hash_alg_t func,
2545 __in uint8_t *buffer);
2546
2547#endif /* EFSYS_OPT_RX_SCALE */
2548
2549extern __checkReturn efx_rc_t
2550efx_pseudo_hdr_pkt_length_get(
2551 __in efx_rxq_t *erp,
2552 __in uint8_t *buffer,
2553 __out uint16_t *pkt_lengthp);
2554
9f95a23c
TL		 2555extern __checkReturn size_t
2556efx_rxq_size(
2557 __in const efx_nic_t *enp,
2558 __in unsigned int ndescs);
2559
2560extern __checkReturn unsigned int
2561efx_rxq_nbufs(
2562 __in const efx_nic_t *enp,
2563 __in unsigned int ndescs);
11fdf7f2 2564
11fdf7f2 2565#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
11fdf7f2
TL		 2566
2567typedef enum efx_rxq_type_e {
2568 EFX_RXQ_TYPE_DEFAULT,
2569 EFX_RXQ_TYPE_PACKED_STREAM,
2570 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2571 EFX_RXQ_NTYPES
2572} efx_rxq_type_t;
2573
2574/*
2575 * Dummy flag to be used instead of 0 to make it clear that the argument
2576 * is receive queue flags.
2577 */
2578#define EFX_RXQ_FLAG_NONE 0x0
2579#define EFX_RXQ_FLAG_SCATTER 0x1
2580/*
2581 * If tunnels are supported and Rx event can provide information about
2582 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2583 * full-feature firmware variant running), outer classes are requested by
2584 * default. However, if the driver supports tunnels, the flag allows to
2585 * request inner classes which are required to be able to interpret inner
2586 * Rx checksum offload results.
2587 */
2588#define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2589
2590extern __checkReturn efx_rc_t
2591efx_rx_qcreate(
2592 __in efx_nic_t *enp,
2593 __in unsigned int index,
2594 __in unsigned int label,
2595 __in efx_rxq_type_t type,
9f95a23c 2596 __in size_t buf_size,
11fdf7f2
TL		 2597 __in efsys_mem_t *esmp,
2598 __in size_t ndescs,
2599 __in uint32_t id,
2600 __in unsigned int flags,
2601 __in efx_evq_t *eep,
2602 __deref_out efx_rxq_t **erpp);
2603
2604#if EFSYS_OPT_RX_PACKED_STREAM
2605
2606#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2607#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2608#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2609#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2610#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2611
2612extern __checkReturn efx_rc_t
2613efx_rx_qcreate_packed_stream(
2614 __in efx_nic_t *enp,
2615 __in unsigned int index,
2616 __in unsigned int label,
2617 __in uint32_t ps_buf_size,
2618 __in efsys_mem_t *esmp,
2619 __in size_t ndescs,
2620 __in efx_evq_t *eep,
2621 __deref_out efx_rxq_t **erpp);
2622
2623#endif
2624
2625#if EFSYS_OPT_RX_ES_SUPER_BUFFER
2626
2627/* Maximum head-of-line block timeout in nanoseconds */
2628#define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2629
2630extern __checkReturn efx_rc_t
2631efx_rx_qcreate_es_super_buffer(
2632 __in efx_nic_t *enp,
2633 __in unsigned int index,
2634 __in unsigned int label,
2635 __in uint32_t n_bufs_per_desc,
2636 __in uint32_t max_dma_len,
2637 __in uint32_t buf_stride,
2638 __in uint32_t hol_block_timeout,
2639 __in efsys_mem_t *esmp,
2640 __in size_t ndescs,
2641 __in unsigned int flags,
2642 __in efx_evq_t *eep,
2643 __deref_out efx_rxq_t **erpp);
2644
2645#endif
2646
2647typedef struct efx_buffer_s {
2648 efsys_dma_addr_t eb_addr;
2649 size_t eb_size;
2650 boolean_t eb_eop;
2651} efx_buffer_t;
2652
2653typedef struct efx_desc_s {
2654 efx_qword_t ed_eq;
2655} efx_desc_t;
2656
2657extern void
2658efx_rx_qpost(
2659 __in efx_rxq_t *erp,
2660 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2661 __in size_t size,
2662 __in unsigned int ndescs,
2663 __in unsigned int completed,
2664 __in unsigned int added);
2665
2666extern void
2667efx_rx_qpush(
2668 __in efx_rxq_t *erp,
2669 __in unsigned int added,
2670 __inout unsigned int *pushedp);
2671
2672#if EFSYS_OPT_RX_PACKED_STREAM
2673
2674extern void
2675efx_rx_qpush_ps_credits(
2676 __in efx_rxq_t *erp);
2677
2678extern __checkReturn uint8_t *
2679efx_rx_qps_packet_info(
2680 __in efx_rxq_t *erp,
2681 __in uint8_t *buffer,
2682 __in uint32_t buffer_length,
2683 __in uint32_t current_offset,
2684 __out uint16_t *lengthp,
2685 __out uint32_t *next_offsetp,
2686 __out uint32_t *timestamp);
2687#endif
2688
2689extern __checkReturn efx_rc_t
2690efx_rx_qflush(
2691 __in efx_rxq_t *erp);
2692
2693extern void
2694efx_rx_qenable(
2695 __in efx_rxq_t *erp);
2696
2697extern void
2698efx_rx_qdestroy(
2699 __in efx_rxq_t *erp);
2700
2701/* TX */
2702
2703typedef struct efx_txq_s efx_txq_t;
2704
2705#if EFSYS_OPT_QSTATS
2706
2707/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2708typedef enum efx_tx_qstat_e {
2709 TX_POST,
2710 TX_POST_PIO,
2711 TX_NQSTATS
2712} efx_tx_qstat_t;
2713
2714/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2715
2716#endif /* EFSYS_OPT_QSTATS */
2717
2718extern __checkReturn efx_rc_t
2719efx_tx_init(
2720 __in efx_nic_t *enp);
2721
2722extern void
2723efx_tx_fini(
2724 __in efx_nic_t *enp);
2725
9f95a23c
TL		 2726extern __checkReturn size_t
2727efx_txq_size(
2728 __in const efx_nic_t *enp,
2729 __in unsigned int ndescs);
11fdf7f2 2730
9f95a23c
TL		 2731extern __checkReturn unsigned int
2732efx_txq_nbufs(
2733 __in const efx_nic_t *enp,
2734 __in unsigned int ndescs);
11fdf7f2 2735
9f95a23c 2736#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
11fdf7f2
TL		 2737
2738#define EFX_TXQ_CKSUM_IPV4 0x0001
2739#define EFX_TXQ_CKSUM_TCPUDP 0x0002
2740#define EFX_TXQ_FATSOV2 0x0004
2741#define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2742#define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2743
2744extern __checkReturn efx_rc_t
2745efx_tx_qcreate(
2746 __in efx_nic_t *enp,
2747 __in unsigned int index,
2748 __in unsigned int label,
2749 __in efsys_mem_t *esmp,
2750 __in size_t n,
2751 __in uint32_t id,
2752 __in uint16_t flags,
2753 __in efx_evq_t *eep,
2754 __deref_out efx_txq_t **etpp,
2755 __out unsigned int *addedp);
2756
2757extern __checkReturn efx_rc_t
2758efx_tx_qpost(
2759 __in efx_txq_t *etp,
2760 __in_ecount(ndescs) efx_buffer_t *eb,
2761 __in unsigned int ndescs,
2762 __in unsigned int completed,
2763 __inout unsigned int *addedp);
2764
2765extern __checkReturn efx_rc_t
2766efx_tx_qpace(
2767 __in efx_txq_t *etp,
2768 __in unsigned int ns);
2769
2770extern void
2771efx_tx_qpush(
2772 __in efx_txq_t *etp,
2773 __in unsigned int added,
2774 __in unsigned int pushed);
2775
2776extern __checkReturn efx_rc_t
2777efx_tx_qflush(
2778 __in efx_txq_t *etp);
2779
2780extern void
2781efx_tx_qenable(
2782 __in efx_txq_t *etp);
2783
2784extern __checkReturn efx_rc_t
2785efx_tx_qpio_enable(
2786 __in efx_txq_t *etp);
2787
2788extern void
2789efx_tx_qpio_disable(
2790 __in efx_txq_t *etp);
2791
2792extern __checkReturn efx_rc_t
2793efx_tx_qpio_write(
2794 __in efx_txq_t *etp,
2795 __in_ecount(buf_length) uint8_t *buffer,
2796 __in size_t buf_length,
2797 __in size_t pio_buf_offset);
2798
2799extern __checkReturn efx_rc_t
2800efx_tx_qpio_post(
2801 __in efx_txq_t *etp,
2802 __in size_t pkt_length,
2803 __in unsigned int completed,
2804 __inout unsigned int *addedp);
2805
2806extern __checkReturn efx_rc_t
2807efx_tx_qdesc_post(
2808 __in efx_txq_t *etp,
2809 __in_ecount(n) efx_desc_t *ed,
2810 __in unsigned int n,
2811 __in unsigned int completed,
2812 __inout unsigned int *addedp);
2813
2814extern void
2815efx_tx_qdesc_dma_create(
2816 __in efx_txq_t *etp,
2817 __in efsys_dma_addr_t addr,
2818 __in size_t size,
2819 __in boolean_t eop,
2820 __out efx_desc_t *edp);
2821
2822extern void
2823efx_tx_qdesc_tso_create(
2824 __in efx_txq_t *etp,
2825 __in uint16_t ipv4_id,
2826 __in uint32_t tcp_seq,
2827 __in uint8_t tcp_flags,
2828 __out efx_desc_t *edp);
2829
2830/* Number of FATSOv2 option descriptors */
2831#define EFX_TX_FATSOV2_OPT_NDESCS 2
2832
2833/* Maximum number of DMA segments per TSO packet (not superframe) */
2834#define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2835
2836extern void
2837efx_tx_qdesc_tso2_create(
2838 __in efx_txq_t *etp,
2839 __in uint16_t ipv4_id,
2840 __in uint16_t outer_ipv4_id,
2841 __in uint32_t tcp_seq,
2842 __in uint16_t tcp_mss,
2843 __out_ecount(count) efx_desc_t *edp,
2844 __in int count);
2845
2846extern void
2847efx_tx_qdesc_vlantci_create(
2848 __in efx_txq_t *etp,
2849 __in uint16_t tci,
2850 __out efx_desc_t *edp);
2851
2852extern void
2853efx_tx_qdesc_checksum_create(
2854 __in efx_txq_t *etp,
2855 __in uint16_t flags,
2856 __out efx_desc_t *edp);
2857
2858#if EFSYS_OPT_QSTATS
2859
2860#if EFSYS_OPT_NAMES
2861
2862extern const char *
2863efx_tx_qstat_name(
2864 __in efx_nic_t *etp,
2865 __in unsigned int id);
2866
2867#endif /* EFSYS_OPT_NAMES */
2868
2869extern void
2870efx_tx_qstats_update(
2871 __in efx_txq_t *etp,
2872 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2873
2874#endif /* EFSYS_OPT_QSTATS */
2875
2876extern void
2877efx_tx_qdestroy(
2878 __in efx_txq_t *etp);
2879
2880
2881/* FILTER */
2882
2883#if EFSYS_OPT_FILTER
2884
2885#define EFX_ETHER_TYPE_IPV4 0x0800
2886#define EFX_ETHER_TYPE_IPV6 0x86DD
2887
2888#define EFX_IPPROTO_TCP 6
2889#define EFX_IPPROTO_UDP 17
2890#define EFX_IPPROTO_GRE 47
2891
2892/* Use RSS to spread across multiple queues */
2893#define EFX_FILTER_FLAG_RX_RSS 0x01
2894/* Enable RX scatter */
2895#define EFX_FILTER_FLAG_RX_SCATTER 0x02
2896/*
2897 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2898 * May only be set by the filter implementation for each type.
2899 * A removal request will restore the automatic filter in its place.
2900 */
2901#define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2902/* Filter is for RX */
2903#define EFX_FILTER_FLAG_RX 0x08
2904/* Filter is for TX */
2905#define EFX_FILTER_FLAG_TX 0x10
2906/* Set match flag on the received packet */
2907#define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2908/* Set match mark on the received packet */
2909#define EFX_FILTER_FLAG_ACTION_MARK 0x40
2910
2911typedef uint8_t efx_filter_flags_t;
2912
2913/*
2914 * Flags which specify the fields to match on. The values are the same as in the
2915 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2916 */
2917
2918/* Match by remote IP host address */
2919#define EFX_FILTER_MATCH_REM_HOST 0x00000001
2920/* Match by local IP host address */
2921#define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2922/* Match by remote MAC address */
2923#define EFX_FILTER_MATCH_REM_MAC 0x00000004
2924/* Match by remote TCP/UDP port */
2925#define EFX_FILTER_MATCH_REM_PORT 0x00000008
2926/* Match by remote TCP/UDP port */
2927#define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2928/* Match by local TCP/UDP port */
2929#define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2930/* Match by Ether-type */
2931#define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2932/* Match by inner VLAN ID */
2933#define EFX_FILTER_MATCH_INNER_VID 0x00000080
2934/* Match by outer VLAN ID */
2935#define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2936/* Match by IP transport protocol */
2937#define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2938/* Match by VNI or VSID */
2939#define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2940/* For encapsulated packets, match by inner frame local MAC address */
2941#define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2942/* For encapsulated packets, match all multicast inner frames */
2943#define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2944/* For encapsulated packets, match all unicast inner frames */
2945#define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2946/*
2947 * Match by encap type, this flag does not correspond to
2948 * the MCDI match flags and any unoccupied value may be used
2949 */
2950#define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2951/* Match otherwise-unmatched multicast and broadcast packets */
2952#define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2953/* Match otherwise-unmatched unicast packets */
2954#define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2955
2956typedef uint32_t efx_filter_match_flags_t;
2957
f67539c2 2958/* Filter priority from lowest to highest */
11fdf7f2 2959typedef enum efx_filter_priority_s {
f67539c2 2960 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
11fdf7f2
TL		 2961 * address list or hardware
2962 * requirements. This may only be used
2963 * by the filter implementation for
2964 * each NIC type. */
2965 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
f67539c2 2966 EFX_FILTER_NPRI,
11fdf7f2
TL		 2967} efx_filter_priority_t;
2968
2969/*
2970 * FIXME: All these fields are assumed to be in little-endian byte order.
2971 * It may be better for some to be big-endian. See bug42804.
2972 */
2973
2974typedef struct efx_filter_spec_s {
2975 efx_filter_match_flags_t efs_match_flags;
2976 uint8_t efs_priority;
2977 efx_filter_flags_t efs_flags;
2978 uint16_t efs_dmaq_id;
2979 uint32_t efs_rss_context;
9f95a23c 2980 uint32_t efs_mark;
f67539c2
TL		 2981 /*
2982 * Saved lower-priority filter. If it is set, it is restored on
2983 * filter delete operation.
2984 */
2985 struct efx_filter_spec_s *efs_overridden_spec;
9f95a23c 2986 /* Fields below here are hashed for software filter lookup */
11fdf7f2
TL		 2987 uint16_t efs_outer_vid;
2988 uint16_t efs_inner_vid;
2989 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2990 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2991 uint16_t efs_ether_type;
2992 uint8_t efs_ip_proto;
2993 efx_tunnel_protocol_t efs_encap_type;
2994 uint16_t efs_loc_port;
2995 uint16_t efs_rem_port;
2996 efx_oword_t efs_rem_host;
2997 efx_oword_t efs_loc_host;
2998 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2999 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
11fdf7f2
TL		 3000} efx_filter_spec_t;
3001
3002
3003/* Default values for use in filter specifications */
3004#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3005#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3006
3007extern __checkReturn efx_rc_t
3008efx_filter_init(
3009 __in efx_nic_t *enp);
3010
3011extern void
3012efx_filter_fini(
3013 __in efx_nic_t *enp);
3014
3015extern __checkReturn efx_rc_t
3016efx_filter_insert(
3017 __in efx_nic_t *enp,
3018 __inout efx_filter_spec_t *spec);
3019
3020extern __checkReturn efx_rc_t
3021efx_filter_remove(
3022 __in efx_nic_t *enp,
3023 __inout efx_filter_spec_t *spec);
3024
3025extern __checkReturn efx_rc_t
3026efx_filter_restore(
3027 __in efx_nic_t *enp);
3028
3029extern __checkReturn efx_rc_t
3030efx_filter_supported_filters(
3031 __in efx_nic_t *enp,
3032 __out_ecount(buffer_length) uint32_t *buffer,
3033 __in size_t buffer_length,
3034 __out size_t *list_lengthp);
3035
3036extern void
3037efx_filter_spec_init_rx(
3038 __out efx_filter_spec_t *spec,
3039 __in efx_filter_priority_t priority,
3040 __in efx_filter_flags_t flags,
3041 __in efx_rxq_t *erp);
3042
3043extern void
3044efx_filter_spec_init_tx(
3045 __out efx_filter_spec_t *spec,
3046 __in efx_txq_t *etp);
3047
3048extern __checkReturn efx_rc_t
3049efx_filter_spec_set_ipv4_local(
3050 __inout efx_filter_spec_t *spec,
3051 __in uint8_t proto,
3052 __in uint32_t host,
3053 __in uint16_t port);
3054
3055extern __checkReturn efx_rc_t
3056efx_filter_spec_set_ipv4_full(
3057 __inout efx_filter_spec_t *spec,
3058 __in uint8_t proto,
3059 __in uint32_t lhost,
3060 __in uint16_t lport,
3061 __in uint32_t rhost,
3062 __in uint16_t rport);
3063
3064extern __checkReturn efx_rc_t
3065efx_filter_spec_set_eth_local(
3066 __inout efx_filter_spec_t *spec,
3067 __in uint16_t vid,
3068 __in const uint8_t *addr);
3069
3070extern void
3071efx_filter_spec_set_ether_type(
3072 __inout efx_filter_spec_t *spec,
3073 __in uint16_t ether_type);
3074
3075extern __checkReturn efx_rc_t
3076efx_filter_spec_set_uc_def(
3077 __inout efx_filter_spec_t *spec);
3078
3079extern __checkReturn efx_rc_t
3080efx_filter_spec_set_mc_def(
3081 __inout efx_filter_spec_t *spec);
3082
3083typedef enum efx_filter_inner_frame_match_e {
3084 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3085 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3086 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3087} efx_filter_inner_frame_match_t;
3088
3089extern __checkReturn efx_rc_t
3090efx_filter_spec_set_encap_type(
3091 __inout efx_filter_spec_t *spec,
3092 __in efx_tunnel_protocol_t encap_type,
3093 __in efx_filter_inner_frame_match_t inner_frame_match);
3094
3095extern __checkReturn efx_rc_t
9f95a23c
TL		 3096efx_filter_spec_set_vxlan(
3097 __inout efx_filter_spec_t *spec,
3098 __in const uint8_t *vni,
3099 __in const uint8_t *inner_addr,
3100 __in const uint8_t *outer_addr);
3101
3102extern __checkReturn efx_rc_t
3103efx_filter_spec_set_geneve(
11fdf7f2 3104 __inout efx_filter_spec_t *spec,
9f95a23c
TL		 3105 __in const uint8_t *vni,
3106 __in const uint8_t *inner_addr,
3107 __in const uint8_t *outer_addr);
3108
3109extern __checkReturn efx_rc_t
3110efx_filter_spec_set_nvgre(
3111 __inout efx_filter_spec_t *spec,
3112 __in const uint8_t *vsid,
11fdf7f2
TL		 3113 __in const uint8_t *inner_addr,
3114 __in const uint8_t *outer_addr);
3115
3116#if EFSYS_OPT_RX_SCALE
3117extern __checkReturn efx_rc_t
3118efx_filter_spec_set_rss_context(
3119 __inout efx_filter_spec_t *spec,
3120 __in uint32_t rss_context);
3121#endif
3122#endif /* EFSYS_OPT_FILTER */
3123
3124/* HASH */
3125
3126extern __checkReturn uint32_t
3127efx_hash_dwords(
3128 __in_ecount(count) uint32_t const *input,
3129 __in size_t count,
3130 __in uint32_t init);
3131
3132extern __checkReturn uint32_t
3133efx_hash_bytes(
3134 __in_ecount(length) uint8_t const *input,
3135 __in size_t length,
3136 __in uint32_t init);
3137
3138#if EFSYS_OPT_LICENSING
3139
3140/* LICENSING */
3141
3142typedef struct efx_key_stats_s {
3143 uint32_t eks_valid;
3144 uint32_t eks_invalid;
3145 uint32_t eks_blacklisted;
3146 uint32_t eks_unverifiable;
3147 uint32_t eks_wrong_node;
3148 uint32_t eks_licensed_apps_lo;
3149 uint32_t eks_licensed_apps_hi;
3150 uint32_t eks_licensed_features_lo;
3151 uint32_t eks_licensed_features_hi;
3152} efx_key_stats_t;
3153
3154extern __checkReturn efx_rc_t
3155efx_lic_init(
3156 __in efx_nic_t *enp);
3157
3158extern void
3159efx_lic_fini(
3160 __in efx_nic_t *enp);
3161
3162extern __checkReturn boolean_t
3163efx_lic_check_support(
3164 __in efx_nic_t *enp);
3165
3166extern __checkReturn efx_rc_t
3167efx_lic_update_licenses(
3168 __in efx_nic_t *enp);
3169
3170extern __checkReturn efx_rc_t
3171efx_lic_get_key_stats(
3172 __in efx_nic_t *enp,
3173 __out efx_key_stats_t *ksp);
3174
3175extern __checkReturn efx_rc_t
3176efx_lic_app_state(
3177 __in efx_nic_t *enp,
3178 __in uint64_t app_id,
3179 __out boolean_t *licensedp);
3180
3181extern __checkReturn efx_rc_t
3182efx_lic_get_id(
3183 __in efx_nic_t *enp,
3184 __in size_t buffer_size,
3185 __out uint32_t *typep,
3186 __out size_t *lengthp,
3187 __out_opt uint8_t *bufferp);
3188
3189
3190extern __checkReturn efx_rc_t
3191efx_lic_find_start(
3192 __in efx_nic_t *enp,
3193 __in_bcount(buffer_size)
3194 caddr_t bufferp,
3195 __in size_t buffer_size,
3196 __out uint32_t *startp);
3197
3198extern __checkReturn efx_rc_t
3199efx_lic_find_end(
3200 __in efx_nic_t *enp,
3201 __in_bcount(buffer_size)
3202 caddr_t bufferp,
3203 __in size_t buffer_size,
3204 __in uint32_t offset,
3205 __out uint32_t *endp);
3206
3207extern __checkReturn __success(return != B_FALSE) boolean_t
3208efx_lic_find_key(
3209 __in efx_nic_t *enp,
3210 __in_bcount(buffer_size)
3211 caddr_t bufferp,
3212 __in size_t buffer_size,
3213 __in uint32_t offset,
3214 __out uint32_t *startp,
3215 __out uint32_t *lengthp);
3216
3217extern __checkReturn __success(return != B_FALSE) boolean_t
3218efx_lic_validate_key(
3219 __in efx_nic_t *enp,
3220 __in_bcount(length) caddr_t keyp,
3221 __in uint32_t length);
3222
3223extern __checkReturn efx_rc_t
3224efx_lic_read_key(
3225 __in efx_nic_t *enp,
3226 __in_bcount(buffer_size)
3227 caddr_t bufferp,
3228 __in size_t buffer_size,
3229 __in uint32_t offset,
3230 __in uint32_t length,
3231 __out_bcount_part(key_max_size, *lengthp)
3232 caddr_t keyp,
3233 __in size_t key_max_size,
3234 __out uint32_t *lengthp);
3235
3236extern __checkReturn efx_rc_t
3237efx_lic_write_key(
3238 __in efx_nic_t *enp,
3239 __in_bcount(buffer_size)
3240 caddr_t bufferp,
3241 __in size_t buffer_size,
3242 __in uint32_t offset,
3243 __in_bcount(length) caddr_t keyp,
3244 __in uint32_t length,
3245 __out uint32_t *lengthp);
3246
3247 __checkReturn efx_rc_t
3248efx_lic_delete_key(
3249 __in efx_nic_t *enp,
3250 __in_bcount(buffer_size)
3251 caddr_t bufferp,
3252 __in size_t buffer_size,
3253 __in uint32_t offset,
3254 __in uint32_t length,
3255 __in uint32_t end,
3256 __out uint32_t *deltap);
3257
3258extern __checkReturn efx_rc_t
3259efx_lic_create_partition(
3260 __in efx_nic_t *enp,
3261 __in_bcount(buffer_size)
3262 caddr_t bufferp,
3263 __in size_t buffer_size);
3264
3265extern __checkReturn efx_rc_t
3266efx_lic_finish_partition(
3267 __in efx_nic_t *enp,
3268 __in_bcount(buffer_size)
3269 caddr_t bufferp,
3270 __in size_t buffer_size);
3271
3272#endif /* EFSYS_OPT_LICENSING */
3273
3274/* TUNNEL */
3275
3276#if EFSYS_OPT_TUNNEL
3277
3278extern __checkReturn efx_rc_t
3279efx_tunnel_init(
3280 __in efx_nic_t *enp);
3281
3282extern void
3283efx_tunnel_fini(
3284 __in efx_nic_t *enp);
3285
3286/*
3287 * For overlay network encapsulation using UDP, the firmware needs to know
3288 * the configured UDP port for the overlay so it can decode encapsulated
3289 * frames correctly.
3290 * The UDP port/protocol list is global.
3291 */
3292
3293extern __checkReturn efx_rc_t
3294efx_tunnel_config_udp_add(
3295 __in efx_nic_t *enp,
3296 __in uint16_t port /* host/cpu-endian */,
3297 __in efx_tunnel_protocol_t protocol);
3298
3299extern __checkReturn efx_rc_t
3300efx_tunnel_config_udp_remove(
3301 __in efx_nic_t *enp,
3302 __in uint16_t port /* host/cpu-endian */,
3303 __in efx_tunnel_protocol_t protocol);
3304
3305extern void
3306efx_tunnel_config_clear(
3307 __in efx_nic_t *enp);
3308
3309/**
3310 * Apply tunnel UDP ports configuration to hardware.
3311 *
3312 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3313 * reboot).
3314 */
3315extern __checkReturn efx_rc_t
3316efx_tunnel_reconfigure(
3317 __in efx_nic_t *enp);
3318
3319#endif /* EFSYS_OPT_TUNNEL */
3320
3321#if EFSYS_OPT_FW_SUBVARIANT_AWARE
3322
3323/**
3324 * Firmware subvariant choice options.
3325 *
3326 * It may be switched to no Tx checksum if attached drivers are either
3327 * preboot or firmware subvariant aware and no VIS are allocated.
3328 * If may be always switched to default explicitly using set request or
3329 * implicitly if unaware driver is attaching. If switching is done when
3330 * a driver is attached, it gets MC_REBOOT event and should recreate its
3331 * datapath.
3332 *
3333 * See SF-119419-TC DPDK Firmware Driver Interface and
3334 * SF-109306-TC EF10 for Driver Writers for details.
3335 */
3336typedef enum efx_nic_fw_subvariant_e {
3337 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3338 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3339 EFX_NIC_FW_SUBVARIANT_NTYPES
3340} efx_nic_fw_subvariant_t;
3341
3342extern __checkReturn efx_rc_t
3343efx_nic_get_fw_subvariant(
3344 __in efx_nic_t *enp,
3345 __out efx_nic_fw_subvariant_t *subvariantp);
3346
3347extern __checkReturn efx_rc_t
3348efx_nic_set_fw_subvariant(
3349 __in efx_nic_t *enp,
3350 __in efx_nic_fw_subvariant_t subvariant);
3351
3352#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3353
9f95a23c
TL		 3354typedef enum efx_phy_fec_type_e {
3355 EFX_PHY_FEC_NONE = 0,
3356 EFX_PHY_FEC_BASER,
3357 EFX_PHY_FEC_RS
3358} efx_phy_fec_type_t;
3359
3360extern __checkReturn efx_rc_t
3361efx_phy_fec_type_get(
3362 __in efx_nic_t *enp,
3363 __out efx_phy_fec_type_t *typep);
3364
3365typedef struct efx_phy_link_state_s {
3366 uint32_t epls_adv_cap_mask;
3367 uint32_t epls_lp_cap_mask;
3368 uint32_t epls_ld_cap_mask;
3369 unsigned int epls_fcntl;
3370 efx_phy_fec_type_t epls_fec;
3371 efx_link_mode_t epls_link_mode;
3372} efx_phy_link_state_t;
3373
3374extern __checkReturn efx_rc_t
3375efx_phy_link_state_get(
3376 __in efx_nic_t *enp,
3377 __out efx_phy_link_state_t *eplsp);
3378
3379
f67539c2
TL		 3380#if EFSYS_OPT_EVB
3381
3382typedef uint32_t efx_vswitch_id_t;
3383typedef uint32_t efx_vport_id_t;
3384
3385typedef enum efx_vswitch_type_e {
3386 EFX_VSWITCH_TYPE_VLAN = 1,
3387 EFX_VSWITCH_TYPE_VEB,
3388 /* VSWITCH_TYPE_VEPA: obsolete */
3389 EFX_VSWITCH_TYPE_MUX = 4,
3390} efx_vswitch_type_t;
3391
3392typedef enum efx_vport_type_e {
3393 EFX_VPORT_TYPE_NORMAL = 4,
3394 EFX_VPORT_TYPE_EXPANSION,
3395 EFX_VPORT_TYPE_TEST,
3396} efx_vport_type_t;
3397
3398/* Unspecified VLAN ID to support disabling of VLAN filtering */
3399#define EFX_FILTER_VID_UNSPEC 0xffff
3400#define EFX_DEFAULT_VSWITCH_ID 1
3401
3402/* Default VF VLAN ID on creation */
3403#define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3404#define EFX_VPORT_ID_INVALID 0
3405
3406typedef struct efx_vport_config_s {
3407 /* Either VF index or 0xffff for PF */
3408 uint16_t evc_function;
3409 /* VLAN ID of the associated function */
3410 uint16_t evc_vid;
3411 /* vport id shared with client driver */
3412 efx_vport_id_t evc_vport_id;
3413 /* MAC address of the associated function */
3414 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3415 /*
3416 * vports created with this flag set may only transfer traffic on the
3417 * VLANs permitted by the vport. Also, an attempt to install filter with
3418 * VLAN will be refused unless requesting function has VLAN privilege.
3419 */
3420 boolean_t evc_vlan_restrict;
3421 /* Whether this function is assigned or not */
3422 boolean_t evc_vport_assigned;
3423} efx_vport_config_t;
3424
3425typedef struct efx_vswitch_s efx_vswitch_t;
3426
3427extern __checkReturn efx_rc_t
3428efx_evb_init(
3429 __in efx_nic_t *enp);
3430
3431extern void
3432efx_evb_fini(
3433 __in efx_nic_t *enp);
3434
3435extern __checkReturn efx_rc_t
3436efx_evb_vswitch_create(
3437 __in efx_nic_t *enp,
3438 __in uint32_t num_vports,
3439 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3440 __deref_out efx_vswitch_t **evpp);
3441
3442extern __checkReturn efx_rc_t
3443efx_evb_vswitch_destroy(
3444 __in efx_nic_t *enp,
3445 __in efx_vswitch_t *evp);
3446
3447extern __checkReturn efx_rc_t
3448efx_evb_vport_mac_set(
3449 __in efx_nic_t *enp,
3450 __in efx_vswitch_t *evp,
3451 __in efx_vport_id_t vport_id,
3452 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3453
3454extern __checkReturn efx_rc_t
3455efx_evb_vport_vlan_set(
3456 __in efx_nic_t *enp,
3457 __in efx_vswitch_t *evp,
3458 __in efx_vport_id_t vport_id,
3459 __in uint16_t vid);
3460
3461extern __checkReturn efx_rc_t
3462efx_evb_vport_reset(
3463 __in efx_nic_t *enp,
3464 __in efx_vswitch_t *evp,
3465 __in efx_vport_id_t vport_id,
3466 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3467 __in uint16_t vid,
3468 __out boolean_t *is_fn_resetp);
3469
3470extern __checkReturn efx_rc_t
3471efx_evb_vport_stats(
3472 __in efx_nic_t *enp,
3473 __in efx_vswitch_t *evp,
3474 __in efx_vport_id_t vport_id,
3475 __out efsys_mem_t *stats_bufferp);
3476
3477#endif /* EFSYS_OPT_EVB */
3478
3479#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3480
3481typedef struct efx_proxy_auth_config_s {
3482 efsys_mem_t *request_bufferp;
3483 efsys_mem_t *response_bufferp;
3484 efsys_mem_t *status_bufferp;
3485 uint32_t block_cnt;
3486 uint32_t *op_listp;
3487 size_t op_count;
3488 uint32_t handled_privileges;
3489} efx_proxy_auth_config_t;
3490
3491typedef struct efx_proxy_cmd_params_s {
3492 uint32_t pf_index;
3493 uint32_t vf_index;
3494 uint8_t *request_bufferp;
3495 size_t request_size;
3496 uint8_t *response_bufferp;
3497 size_t response_size;
3498 size_t *response_size_actualp;
3499} efx_proxy_cmd_params_t;
3500
3501extern __checkReturn efx_rc_t
3502efx_proxy_auth_init(
3503 __in efx_nic_t *enp);
3504
3505extern void
3506efx_proxy_auth_fini(
3507 __in efx_nic_t *enp);
3508
3509extern __checkReturn efx_rc_t
3510efx_proxy_auth_configure(
3511 __in efx_nic_t *enp,
3512 __in efx_proxy_auth_config_t *configp);
3513
3514 __checkReturn efx_rc_t
3515efx_proxy_auth_destroy(
3516 __in efx_nic_t *enp,
3517 __in uint32_t handled_privileges);
3518
3519 __checkReturn efx_rc_t
3520efx_proxy_auth_complete_request(
3521 __in efx_nic_t *enp,
3522 __in uint32_t fn_index,
3523 __in uint32_t proxy_result,
3524 __in uint32_t handle);
3525
3526 __checkReturn efx_rc_t
3527efx_proxy_auth_exec_cmd(
3528 __in efx_nic_t *enp,
3529 __inout efx_proxy_cmd_params_t *paramsp);
3530
3531 __checkReturn efx_rc_t
3532efx_proxy_auth_set_privilege_mask(
3533 __in efx_nic_t *enp,
3534 __in uint32_t vf_index,
3535 __in uint32_t mask,
3536 __in uint32_t value);
3537
3538 __checkReturn efx_rc_t
3539efx_proxy_auth_privilege_mask_get(
3540 __in efx_nic_t *enp,
3541 __in uint32_t pf_index,
3542 __in uint32_t vf_index,
3543 __out uint32_t *maskp);
3544
3545 __checkReturn efx_rc_t
3546efx_proxy_auth_privilege_modify(
3547 __in efx_nic_t *enp,
3548 __in uint32_t pf_index,
3549 __in uint32_t vf_index,
3550 __in uint32_t add_privileges_mask,
3551 __in uint32_t remove_privileges_mask);
3552
3553#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3554
11fdf7f2
TL		 3555#ifdef __cplusplus
3556}
3557#endif
3558
3559#endif /* _SYS_EFX_H */
Ceph