[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / efx_phy_ids.h

/* SPDX-License-Identifier: BSD-3-Clause
 *
 * Copyright(c) 2019-2020 Xilinx, Inc.
 * Copyright(c) 2013-2019 Solarflare Communications Inc.
 */

#ifndef	_SYS_EFX_PHY_IDS_H
#define	_SYS_EFX_PHY_IDS_H

#define	EFX_PHY_NULL	0

typedef enum efx_phy_type_e {			/* GENERATED BY scripts/genfwdef */
	EFX_PHY_TXC43128 = 1,
	EFX_PHY_SFX7101 = 3,
	EFX_PHY_QT2022C2 = 4,
	EFX_PHY_PM8358 = 6,
	EFX_PHY_SFT9001A = 8,
	EFX_PHY_QT2025C = 9,
	EFX_PHY_SFT9001B = 10,
	EFX_PHY_QLX111V = 12,
	EFX_PHY_QT2025_KR = 17,
	EFX_PHY_AEL3020 = 18,
	EFX_PHY_XFI_FARMI = 19,
} efx_phy_type_t;


#endif	/* _SYS_EFX_PHY_IDS_H */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
11fdf7f2 TL	2	*
f67539c2 TL	3	* Copyright(c) 2019-2020 Xilinx, Inc.
f67539c2 TL	4	* Copyright(c) 2013-2019 Solarflare Communications Inc.
11fdf7f2 TL	5	*/
	6
	7	#ifndef _SYS_EFX_PHY_IDS_H
	8	#define _SYS_EFX_PHY_IDS_H
	9
	10	#define EFX_PHY_NULL 0
	11
	12	typedef enum efx_phy_type_e { /* GENERATED BY scripts/genfwdef */
	13	EFX_PHY_TXC43128 = 1,
	14	EFX_PHY_SFX7101 = 3,
	15	EFX_PHY_QT2022C2 = 4,
	16	EFX_PHY_PM8358 = 6,
	17	EFX_PHY_SFT9001A = 8,
	18	EFX_PHY_QT2025C = 9,
	19	EFX_PHY_SFT9001B = 10,
	20	EFX_PHY_QLX111V = 12,
	21	EFX_PHY_QT2025_KR = 17,
	22	EFX_PHY_AEL3020 = 18,
	23	EFX_PHY_XFI_FARMI = 19,
	24	} efx_phy_type_t;
	25
	26
	27	#endif /* _SYS_EFX_PHY_IDS_H */