[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / medford_nic.c

/* SPDX-License-Identifier: BSD-3-Clause
 *
 * Copyright (c) 2015-2018 Solarflare Communications Inc.
 * All rights reserved.
 */

#include "efx.h"
#include "efx_impl.h"


#if EFSYS_OPT_MEDFORD

static	__checkReturn	efx_rc_t
medford_nic_get_required_pcie_bandwidth(
	__in		efx_nic_t *enp,
	__out		uint32_t *bandwidth_mbpsp)
{
	uint32_t bandwidth;
	efx_rc_t rc;

	if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
						    &bandwidth)) != 0)
		goto fail1;

	*bandwidth_mbpsp = bandwidth;

	return (0);

fail1:
	EFSYS_PROBE1(fail1, efx_rc_t, rc);

	return (rc);
}

	__checkReturn	efx_rc_t
medford_board_cfg(
	__in		efx_nic_t *enp)
{
	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
	uint32_t sysclk, dpcpu_clk;
	uint32_t end_padding;
	uint32_t bandwidth;
	efx_rc_t rc;

	/*
	 * Enable firmware workarounds for hardware errata.
	 * Expected responses are:
	 *  - 0 (zero):
	 *	Success: workaround enabled or disabled as requested.
	 *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
	 *	Firmware does not support the MC_CMD_WORKAROUND request.
	 *	(assume that the workaround is not supported).
	 *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
	 *	Firmware does not support the requested workaround.
	 *  - MC_CMD_ERR_EPERM  (reported as EACCES):
	 *	Unprivileged function cannot enable/disable workarounds.
	 *
	 * See efx_mcdi_request_errcode() for MCDI error translations.
	 */


	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
		/*
		 * Interrupt testing does not work for VFs. See bug50084 and
		 * bug71432 comment 21.
		 */
		encp->enc_bug41750_workaround = B_TRUE;
	}

	/* Chained multicast is always enabled on Medford */
	encp->enc_bug26807_workaround = B_TRUE;

	/*
	 * If the bug61265 workaround is enabled, then interrupt holdoff timers
	 * cannot be controlled by timer table writes, so MCDI must be used
	 * (timer table writes can still be used for wakeup timers).
	 */
	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
	    NULL);
	if ((rc == 0) || (rc == EACCES))
		encp->enc_bug61265_workaround = B_TRUE;
	else if ((rc == ENOTSUP) || (rc == ENOENT))
		encp->enc_bug61265_workaround = B_FALSE;
	else
		goto fail1;

	/* Checksums for TSO sends can be incorrect on Medford. */
	encp->enc_bug61297_workaround = B_TRUE;

	/* Get clock frequencies (in MHz). */
	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
		goto fail2;

	/*
	 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
	 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
	 */
	encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;

	encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
	encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
	encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;

	/* Alignment for receive packet DMA buffers */
	encp->enc_rx_buf_align_start = 1;

	/* Get the RX DMA end padding alignment configuration */
	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
		if (rc != EACCES)
			goto fail3;

		/* Assume largest tail padding size supported by hardware */
		end_padding = 256;
	}
	encp->enc_rx_buf_align_end = end_padding;

	encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
	encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;

	encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
	encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;

	/*
	 * The maximum supported transmit queue size is 2048. TXQs with 4096
	 * descriptors are not supported as the top bit is used for vfifo
	 * stuffing.
	 */
	encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS;
	encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;

	EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
	encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
	encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;

	/*
	 * Medford stores a single global copy of VPD, not per-PF as on
	 * Huntington.
	 */
	encp->enc_vpd_is_global = B_TRUE;

	rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
	if (rc != 0)
		goto fail4;
	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;

	return (0);

fail4:
	EFSYS_PROBE(fail4);
fail3:
	EFSYS_PROBE(fail3);
fail2:
	EFSYS_PROBE(fail2);
fail1:
	EFSYS_PROBE1(fail1, efx_rc_t, rc);

	return (rc);
}

#endif	/* EFSYS_OPT_MEDFORD */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	*
	3	* Copyright (c) 2015-2018 Solarflare Communications Inc.
	4	* All rights reserved.
	5	*/
	6
	7	#include "efx.h"
	8	#include "efx_impl.h"
	9
	10
	11	#if EFSYS_OPT_MEDFORD
	12
	13	static __checkReturn efx_rc_t
	14	medford_nic_get_required_pcie_bandwidth(
	15	__in efx_nic_t *enp,
	16	__out uint32_t *bandwidth_mbpsp)
	17	{
11fdf7f2 TL	18	uint32_t bandwidth;
	19	efx_rc_t rc;
	20
9f95a23c	21	if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
11fdf7f2 TL	22	&bandwidth)) != 0)
	23	goto fail1;
	24
11fdf7f2 TL	25	*bandwidth_mbpsp = bandwidth;
	26
	27	return (0);
	28
	29	fail1:
	30	EFSYS_PROBE1(fail1, efx_rc_t, rc);
	31
	32	return (rc);
	33	}
	34
	35	__checkReturn efx_rc_t
	36	medford_board_cfg(
	37	__in efx_nic_t *enp)
	38	{
	39	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
	40	uint32_t sysclk, dpcpu_clk;
	41	uint32_t end_padding;
	42	uint32_t bandwidth;
	43	efx_rc_t rc;
	44
	45	/*
	46	* Enable firmware workarounds for hardware errata.
	47	* Expected responses are:
	48	* - 0 (zero):
	49	* Success: workaround enabled or disabled as requested.
	50	* - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
	51	* Firmware does not support the MC_CMD_WORKAROUND request.
	52	* (assume that the workaround is not supported).
	53	* - MC_CMD_ERR_ENOENT (reported as ENOENT):
	54	* Firmware does not support the requested workaround.
	55	* - MC_CMD_ERR_EPERM (reported as EACCES):
	56	* Unprivileged function cannot enable/disable workarounds.
	57	*
	58	* See efx_mcdi_request_errcode() for MCDI error translations.
	59	*/
	60
	61
	62	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
	63	/*
	64	* Interrupt testing does not work for VFs. See bug50084 and
	65	* bug71432 comment 21.
	66	*/
	67	encp->enc_bug41750_workaround = B_TRUE;
	68	}
	69
	70	/* Chained multicast is always enabled on Medford */
	71	encp->enc_bug26807_workaround = B_TRUE;
	72
	73	/*
	74	* If the bug61265 workaround is enabled, then interrupt holdoff timers
	75	* cannot be controlled by timer table writes, so MCDI must be used
	76	* (timer table writes can still be used for wakeup timers).
	77	*/
	78	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
	79	NULL);
	80	if ((rc == 0) \|\| (rc == EACCES))
	81	encp->enc_bug61265_workaround = B_TRUE;
	82	else if ((rc == ENOTSUP) \|\| (rc == ENOENT))
	83	encp->enc_bug61265_workaround = B_FALSE;
	84	else
	85	goto fail1;
	86
9f95a23c TL	87	/* Checksums for TSO sends can be incorrect on Medford. */
	88	encp->enc_bug61297_workaround = B_TRUE;
	89
11fdf7f2 TL	90	/* Get clock frequencies (in MHz). */
	91	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
	92	goto fail2;
	93
	94	/*
	95	* The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
	96	* the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
	97	*/
	98	encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
	99	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
	100	FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
	101
9f95a23c TL	102	encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
	103	encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
	104	encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
	105
11fdf7f2 TL	106	/* Alignment for receive packet DMA buffers */
	107	encp->enc_rx_buf_align_start = 1;
	108
	109	/* Get the RX DMA end padding alignment configuration */
	110	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
	111	if (rc != EACCES)
	112	goto fail3;
	113
	114	/* Assume largest tail padding size supported by hardware */
	115	end_padding = 256;
	116	}
	117	encp->enc_rx_buf_align_end = end_padding;
	118
9f95a23c TL	119	encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
	120	encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
	121
	122	encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
	123	encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
	124
11fdf7f2 TL	125	/*
	126	* The maximum supported transmit queue size is 2048. TXQs with 4096
	127	* descriptors are not supported as the top bit is used for vfifo
	128	* stuffing.
	129	*/
9f95a23c TL	130	encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS;
9f95a23c TL	131	encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
11fdf7f2 TL	132
	133	EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
	134	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
	135	encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
	136	encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
	137
	138	/*
	139	* Medford stores a single global copy of VPD, not per-PF as on
	140	* Huntington.
	141	*/
	142	encp->enc_vpd_is_global = B_TRUE;
	143
	144	rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
	145	if (rc != 0)
	146	goto fail4;
	147	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
	148	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
	149
	150	return (0);
	151
	152	fail4:
	153	EFSYS_PROBE(fail4);
	154	fail3:
	155	EFSYS_PROBE(fail3);
	156	fail2:
	157	EFSYS_PROBE(fail2);
	158	fail1:
	159	EFSYS_PROBE1(fail1, efx_rc_t, rc);
	160
	161	return (rc);
	162	}
	163
	164	#endif /* EFSYS_OPT_MEDFORD */