[ceph.git] / ceph / src / spdk / dpdk / drivers / raw / dpaa2_qdma / dpaa2_qdma.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright 2018 NXP
 */

#ifndef __DPAA2_QDMA_H__
#define __DPAA2_QDMA_H__

struct qdma_sdd;
struct qdma_io_meta;

#define DPAA2_QDMA_MAX_FLE 3
#define DPAA2_QDMA_MAX_SDD 2

#define DPAA2_DPDMAI_MAX_QUEUES	8

/** FLE pool size: 3 Frame list + 2 source/destination descriptor */
#define QDMA_FLE_POOL_SIZE (sizeof(struct qdma_io_meta) + \
		sizeof(struct qbman_fle) * DPAA2_QDMA_MAX_FLE + \
		sizeof(struct qdma_sdd) * DPAA2_QDMA_MAX_SDD)
/** FLE pool cache size */
#define QDMA_FLE_CACHE_SIZE(_num) (_num/(RTE_MAX_LCORE * 2))

/** Notification by FQD_CTX[fqid] */
#define QDMA_SER_CTX (1 << 8)
#define DPAA2_RBP_MEM_RW            0x0
/**
 * Source descriptor command read transaction type for RBP=0:
 * coherent copy of cacheable memory
 */
#define DPAA2_COHERENT_NO_ALLOCATE_CACHE	0xb
#define DPAA2_LX2_COHERENT_NO_ALLOCATE_CACHE	0x7
/**
 * Destination descriptor command write transaction type for RBP=0:
 * coherent copy of cacheable memory
 */
#define DPAA2_COHERENT_ALLOCATE_CACHE		0x6
#define DPAA2_LX2_COHERENT_ALLOCATE_CACHE	0xb

/** Maximum possible H/W Queues on each core */
#define MAX_HW_QUEUE_PER_CORE		64

#define QDMA_RBP_UPPER_ADDRESS_MASK (0xfff0000000000)
/**
 * Represents a QDMA device.
 * A single QDMA device exists which is combination of multiple DPDMAI rawdev's.
 */
struct qdma_device {
	/** total number of hw queues. */
	uint16_t num_hw_queues;
	/**
	 * Maximum number of hw queues to be alocated per core.
	 * This is limited by MAX_HW_QUEUE_PER_CORE
	 */
	uint16_t max_hw_queues_per_core;
	/** Maximum number of VQ's */
	uint16_t max_vqs;
	/** mode of operation - physical(h/w) or virtual */
	uint8_t mode;
	/** Device state - started or stopped */
	uint8_t state;
	/** FLE pool for the device */
	struct rte_mempool *fle_pool;
	/** FLE pool size */
	int fle_pool_count;
	/** A lock to QDMA device whenever required */
	rte_spinlock_t lock;
};

/** Represents a QDMA H/W queue */
struct qdma_hw_queue {
	/** Pointer to Next instance */
	TAILQ_ENTRY(qdma_hw_queue) next;
	/** DPDMAI device to communicate with HW */
	struct dpaa2_dpdmai_dev *dpdmai_dev;
	/** queue ID to communicate with HW */
	uint16_t queue_id;
	/** Associated lcore id */
	uint32_t lcore_id;
	/** Number of users of this hw queue */
	uint32_t num_users;
};

/** Represents a QDMA virtual queue */
struct qdma_virt_queue {
	/** Status ring of the virtual queue */
	struct rte_ring *status_ring;
	/** Associated hw queue */
	struct qdma_hw_queue *hw_queue;
	/** Route by port */
	struct rte_qdma_rbp rbp;
	/** Associated lcore id */
	uint32_t lcore_id;
	/** States if this vq is in use or not */
	uint8_t in_use;
	/** States if this vq has exclusively associated hw queue */
	uint8_t exclusive_hw_queue;
	/* Total number of enqueues on this VQ */
	uint64_t num_enqueues;
	/* Total number of dequeues from this VQ */
	uint64_t num_dequeues;
};

/** Represents a QDMA per core hw queues allocation in virtual mode */
struct qdma_per_core_info {
	/** list for allocated hw queues */
	struct qdma_hw_queue *hw_queues[MAX_HW_QUEUE_PER_CORE];
	/* Number of hw queues allocated for this core */
	uint16_t num_hw_queues;
};

/** Metadata which is stored with each operation */
struct qdma_io_meta {
	/**
	 * Context which is stored in the FLE pool (just before the FLE).
	 * QDMA job is stored as a this context as a part of metadata.
	 */
	uint64_t cnxt;
	/** VQ ID is stored as a part of metadata of the enqueue command */
	uint64_t id;
};

/** Source/Destination Descriptor */
struct qdma_sdd {
	uint32_t rsv;
	/** Stride configuration */
	uint32_t stride;
	/** Route-by-port command */
	union {
		uint32_t rbpcmd;
		struct rbpcmd_st {
			uint32_t vfid:6;
			uint32_t rsv4:2;
			uint32_t pfid:1;
			uint32_t rsv3:7;
			uint32_t attr:3;
			uint32_t rsv2:1;
			uint32_t at:2;
			uint32_t vfa:1;
			uint32_t ca:1;
			uint32_t tc:3;
			uint32_t rsv1:5;
		} rbpcmd_simple;
	};
	union {
		uint32_t cmd;
		struct rcmd_simple {
			uint32_t portid:4;
			uint32_t rsv1:14;
			uint32_t rbp:1;
			uint32_t ssen:1;
			uint32_t rthrotl:4;
			uint32_t sqos:3;
			uint32_t ns:1;
			uint32_t rdtype:4;
		} read_cmd;
		struct wcmd_simple {
			uint32_t portid:4;
			uint32_t rsv3:10;
			uint32_t rsv2:2;
			uint32_t lwc:2;
			uint32_t rbp:1;
			uint32_t dsen:1;
			uint32_t rsv1:4;
			uint32_t dqos:3;
			uint32_t ns:1;
			uint32_t wrttype:4;
		} write_cmd;
	};
} __attribute__ ((__packed__));

/** Represents a DPDMAI raw device */
struct dpaa2_dpdmai_dev {
	/** Pointer to Next device instance */
	TAILQ_ENTRY(dpaa2_qdma_device) next;
	/** handle to DPDMAI object */
	struct fsl_mc_io dpdmai;
	/** HW ID for DPDMAI object */
	uint32_t dpdmai_id;
	/** Tocken of this device */
	uint16_t token;
	/** Number of queue in this DPDMAI device */
	uint8_t num_queues;
	/** RX queues */
	struct dpaa2_queue rx_queue[DPAA2_DPDMAI_MAX_QUEUES];
	/** TX queues */
	struct dpaa2_queue tx_queue[DPAA2_DPDMAI_MAX_QUEUES];
};

#endif /* __DPAA2_QDMA_H__ */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	* Copyright 2018 NXP
	3	*/
	4
	5	#ifndef __DPAA2_QDMA_H__
	6	#define __DPAA2_QDMA_H__
	7
	8	struct qdma_sdd;
	9	struct qdma_io_meta;
	10
	11	#define DPAA2_QDMA_MAX_FLE 3
	12	#define DPAA2_QDMA_MAX_SDD 2
	13
9f95a23c TL	14	#define DPAA2_DPDMAI_MAX_QUEUES 8
9f95a23c TL	15
11fdf7f2 TL	16	/** FLE pool size: 3 Frame list + 2 source/destination descriptor */
	17	#define QDMA_FLE_POOL_SIZE (sizeof(struct qdma_io_meta) + \
	18	sizeof(struct qbman_fle) * DPAA2_QDMA_MAX_FLE + \
	19	sizeof(struct qdma_sdd) * DPAA2_QDMA_MAX_SDD)
	20	/** FLE pool cache size */
	21	#define QDMA_FLE_CACHE_SIZE(_num) (_num/(RTE_MAX_LCORE * 2))
	22
	23	/** Notification by FQD_CTX[fqid] */
	24	#define QDMA_SER_CTX (1 << 8)
9f95a23c	25	#define DPAA2_RBP_MEM_RW 0x0
11fdf7f2 TL	26	/**
	27	* Source descriptor command read transaction type for RBP=0:
	28	* coherent copy of cacheable memory
	29	*/
9f95a23c TL	30	#define DPAA2_COHERENT_NO_ALLOCATE_CACHE 0xb
9f95a23c TL	31	#define DPAA2_LX2_COHERENT_NO_ALLOCATE_CACHE 0x7
11fdf7f2 TL	32	/**
	33	* Destination descriptor command write transaction type for RBP=0:
	34	* coherent copy of cacheable memory
	35	*/
9f95a23c TL	36	#define DPAA2_COHERENT_ALLOCATE_CACHE 0x6
9f95a23c TL	37	#define DPAA2_LX2_COHERENT_ALLOCATE_CACHE 0xb
11fdf7f2 TL	38
	39	/** Maximum possible H/W Queues on each core */
	40	#define MAX_HW_QUEUE_PER_CORE 64
	41
9f95a23c	42	#define QDMA_RBP_UPPER_ADDRESS_MASK (0xfff0000000000)
11fdf7f2 TL	43	/**
	44	* Represents a QDMA device.
	45	* A single QDMA device exists which is combination of multiple DPDMAI rawdev's.
	46	*/
	47	struct qdma_device {
	48	/** total number of hw queues. */
	49	uint16_t num_hw_queues;
	50	/**
	51	* Maximum number of hw queues to be alocated per core.
	52	* This is limited by MAX_HW_QUEUE_PER_CORE
	53	*/
	54	uint16_t max_hw_queues_per_core;
	55	/** Maximum number of VQ's */
	56	uint16_t max_vqs;
	57	/** mode of operation - physical(h/w) or virtual */
	58	uint8_t mode;
	59	/** Device state - started or stopped */
	60	uint8_t state;
	61	/** FLE pool for the device */
	62	struct rte_mempool *fle_pool;
	63	/** FLE pool size */
	64	int fle_pool_count;
	65	/** A lock to QDMA device whenever required */
	66	rte_spinlock_t lock;
	67	};
	68
	69	/** Represents a QDMA H/W queue */
	70	struct qdma_hw_queue {
	71	/** Pointer to Next instance */
	72	TAILQ_ENTRY(qdma_hw_queue) next;
	73	/** DPDMAI device to communicate with HW */
	74	struct dpaa2_dpdmai_dev *dpdmai_dev;
	75	/** queue ID to communicate with HW */
	76	uint16_t queue_id;
	77	/** Associated lcore id */
	78	uint32_t lcore_id;
	79	/** Number of users of this hw queue */
	80	uint32_t num_users;
	81	};
	82
	83	/** Represents a QDMA virtual queue */
	84	struct qdma_virt_queue {
	85	/** Status ring of the virtual queue */
	86	struct rte_ring *status_ring;
	87	/** Associated hw queue */
	88	struct qdma_hw_queue *hw_queue;
9f95a23c TL	89	/** Route by port */
9f95a23c TL	90	struct rte_qdma_rbp rbp;
11fdf7f2 TL	91	/** Associated lcore id */
	92	uint32_t lcore_id;
	93	/** States if this vq is in use or not */
	94	uint8_t in_use;
	95	/** States if this vq has exclusively associated hw queue */
	96	uint8_t exclusive_hw_queue;
	97	/* Total number of enqueues on this VQ */
	98	uint64_t num_enqueues;
	99	/* Total number of dequeues from this VQ */
	100	uint64_t num_dequeues;
	101	};
	102
	103	/** Represents a QDMA per core hw queues allocation in virtual mode */
	104	struct qdma_per_core_info {
	105	/** list for allocated hw queues */
	106	struct qdma_hw_queue *hw_queues[MAX_HW_QUEUE_PER_CORE];
	107	/* Number of hw queues allocated for this core */
	108	uint16_t num_hw_queues;
	109	};
	110
	111	/** Metadata which is stored with each operation */
	112	struct qdma_io_meta {
	113	/**
	114	* Context which is stored in the FLE pool (just before the FLE).
	115	* QDMA job is stored as a this context as a part of metadata.
	116	*/
	117	uint64_t cnxt;
	118	/** VQ ID is stored as a part of metadata of the enqueue command */
9f95a23c	119	uint64_t id;
11fdf7f2 TL	120	};
	121
	122	/** Source/Destination Descriptor */
	123	struct qdma_sdd {
	124	uint32_t rsv;
	125	/** Stride configuration */
	126	uint32_t stride;
	127	/** Route-by-port command */
9f95a23c TL	128	union {
	129	uint32_t rbpcmd;
	130	struct rbpcmd_st {
	131	uint32_t vfid:6;
	132	uint32_t rsv4:2;
	133	uint32_t pfid:1;
	134	uint32_t rsv3:7;
	135	uint32_t attr:3;
	136	uint32_t rsv2:1;
	137	uint32_t at:2;
	138	uint32_t vfa:1;
	139	uint32_t ca:1;
	140	uint32_t tc:3;
	141	uint32_t rsv1:5;
	142	} rbpcmd_simple;
	143	};
	144	union {
	145	uint32_t cmd;
	146	struct rcmd_simple {
	147	uint32_t portid:4;
	148	uint32_t rsv1:14;
	149	uint32_t rbp:1;
	150	uint32_t ssen:1;
	151	uint32_t rthrotl:4;
	152	uint32_t sqos:3;
	153	uint32_t ns:1;
	154	uint32_t rdtype:4;
	155	} read_cmd;
	156	struct wcmd_simple {
	157	uint32_t portid:4;
	158	uint32_t rsv3:10;
	159	uint32_t rsv2:2;
	160	uint32_t lwc:2;
	161	uint32_t rbp:1;
	162	uint32_t dsen:1;
	163	uint32_t rsv1:4;
	164	uint32_t dqos:3;
	165	uint32_t ns:1;
	166	uint32_t wrttype:4;
	167	} write_cmd;
	168	};
	169	} __attribute__ ((__packed__));
11fdf7f2 TL	170
	171	/** Represents a DPDMAI raw device */
	172	struct dpaa2_dpdmai_dev {
	173	/** Pointer to Next device instance */
	174	TAILQ_ENTRY(dpaa2_qdma_device) next;
	175	/** handle to DPDMAI object */
	176	struct fsl_mc_io dpdmai;
	177	/** HW ID for DPDMAI object */
	178	uint32_t dpdmai_id;
	179	/** Tocken of this device */
	180	uint16_t token;
	181	/** Number of queue in this DPDMAI device */
	182	uint8_t num_queues;
	183	/** RX queues */
9f95a23c	184	struct dpaa2_queue rx_queue[DPAA2_DPDMAI_MAX_QUEUES];
11fdf7f2	185	/** TX queues */
9f95a23c	186	struct dpaa2_queue tx_queue[DPAA2_DPDMAI_MAX_QUEUES];
11fdf7f2 TL	187	};
	188
	189	#endif /* __DPAA2_QDMA_H__ */