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[ceph.git] / ceph / src / spdk / dpdk / drivers / raw / ifpga_rawdev / base / ifpga_fme.c
CommitLineData
11fdf7f2
TL		 1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
3 */
4
5#include "ifpga_feature_dev.h"
9f95a23c
TL		 6#include "opae_spi.h"
7#include "opae_intel_max10.h"
8#include "opae_i2c.h"
9#include "opae_at24_eeprom.h"
11fdf7f2
TL		 10
11#define PWR_THRESHOLD_MAX 0x7F
12
13int fme_get_prop(struct ifpga_fme_hw *fme, struct feature_prop *prop)
14{
9f95a23c 15 struct ifpga_feature *feature;
11fdf7f2
TL		 16
17 if (!fme)
18 return -ENOENT;
19
20 feature = get_fme_feature_by_id(fme, prop->feature_id);
21
22 if (feature && feature->ops && feature->ops->get_prop)
23 return feature->ops->get_prop(feature, prop);
24
25 return -ENOENT;
26}
27
28int fme_set_prop(struct ifpga_fme_hw *fme, struct feature_prop *prop)
29{
9f95a23c 30 struct ifpga_feature *feature;
11fdf7f2
TL		 31
32 if (!fme)
33 return -ENOENT;
34
35 feature = get_fme_feature_by_id(fme, prop->feature_id);
36
37 if (feature && feature->ops && feature->ops->set_prop)
38 return feature->ops->set_prop(feature, prop);
39
40 return -ENOENT;
41}
42
43int fme_set_irq(struct ifpga_fme_hw *fme, u32 feature_id, void *irq_set)
44{
9f95a23c 45 struct ifpga_feature *feature;
11fdf7f2
TL		 46
47 if (!fme)
48 return -ENOENT;
49
50 feature = get_fme_feature_by_id(fme, feature_id);
51
52 if (feature && feature->ops && feature->ops->set_irq)
53 return feature->ops->set_irq(feature, irq_set);
54
55 return -ENOENT;
56}
57
58/* fme private feature head */
9f95a23c 59static int fme_hdr_init(struct ifpga_feature *feature)
11fdf7f2
TL		 60{
61 struct feature_fme_header *fme_hdr;
62
63 fme_hdr = (struct feature_fme_header *)feature->addr;
64
65 dev_info(NULL, "FME HDR Init.\n");
66 dev_info(NULL, "FME cap %llx.\n",
67 (unsigned long long)fme_hdr->capability.csr);
68
69 return 0;
70}
71
9f95a23c 72static void fme_hdr_uinit(struct ifpga_feature *feature)
11fdf7f2
TL		 73{
74 UNUSED(feature);
75
76 dev_info(NULL, "FME HDR UInit.\n");
77}
78
79static int fme_hdr_get_revision(struct ifpga_fme_hw *fme, u64 *revision)
80{
81 struct feature_fme_header *fme_hdr
82 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
83 struct feature_header header;
84
85 header.csr = readq(&fme_hdr->header);
86 *revision = header.revision;
87
88 return 0;
89}
90
91static int fme_hdr_get_ports_num(struct ifpga_fme_hw *fme, u64 *ports_num)
92{
93 struct feature_fme_header *fme_hdr
94 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
95 struct feature_fme_capability fme_capability;
96
97 fme_capability.csr = readq(&fme_hdr->capability);
98 *ports_num = fme_capability.num_ports;
99
100 return 0;
101}
102
103static int fme_hdr_get_cache_size(struct ifpga_fme_hw *fme, u64 *cache_size)
104{
105 struct feature_fme_header *fme_hdr
106 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
107 struct feature_fme_capability fme_capability;
108
109 fme_capability.csr = readq(&fme_hdr->capability);
110 *cache_size = fme_capability.cache_size;
111
112 return 0;
113}
114
115static int fme_hdr_get_version(struct ifpga_fme_hw *fme, u64 *version)
116{
117 struct feature_fme_header *fme_hdr
118 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
119 struct feature_fme_capability fme_capability;
120
121 fme_capability.csr = readq(&fme_hdr->capability);
122 *version = fme_capability.fabric_verid;
123
124 return 0;
125}
126
127static int fme_hdr_get_socket_id(struct ifpga_fme_hw *fme, u64 *socket_id)
128{
129 struct feature_fme_header *fme_hdr
130 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
131 struct feature_fme_capability fme_capability;
132
133 fme_capability.csr = readq(&fme_hdr->capability);
134 *socket_id = fme_capability.socket_id;
135
136 return 0;
137}
138
139static int fme_hdr_get_bitstream_id(struct ifpga_fme_hw *fme,
140 u64 *bitstream_id)
141{
142 struct feature_fme_header *fme_hdr
143 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
144
145 *bitstream_id = readq(&fme_hdr->bitstream_id);
146
147 return 0;
148}
149
150static int fme_hdr_get_bitstream_metadata(struct ifpga_fme_hw *fme,
151 u64 *bitstream_metadata)
152{
153 struct feature_fme_header *fme_hdr
154 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
155
156 *bitstream_metadata = readq(&fme_hdr->bitstream_md);
157
158 return 0;
159}
160
161static int
9f95a23c 162fme_hdr_get_prop(struct ifpga_feature *feature, struct feature_prop *prop)
11fdf7f2
TL		 163{
164 struct ifpga_fme_hw *fme = feature->parent;
165
166 switch (prop->prop_id) {
167 case FME_HDR_PROP_REVISION:
168 return fme_hdr_get_revision(fme, &prop->data);
169 case FME_HDR_PROP_PORTS_NUM:
170 return fme_hdr_get_ports_num(fme, &prop->data);
171 case FME_HDR_PROP_CACHE_SIZE:
172 return fme_hdr_get_cache_size(fme, &prop->data);
173 case FME_HDR_PROP_VERSION:
174 return fme_hdr_get_version(fme, &prop->data);
175 case FME_HDR_PROP_SOCKET_ID:
176 return fme_hdr_get_socket_id(fme, &prop->data);
177 case FME_HDR_PROP_BITSTREAM_ID:
178 return fme_hdr_get_bitstream_id(fme, &prop->data);
179 case FME_HDR_PROP_BITSTREAM_METADATA:
180 return fme_hdr_get_bitstream_metadata(fme, &prop->data);
181 }
182
183 return -ENOENT;
184}
185
9f95a23c 186struct ifpga_feature_ops fme_hdr_ops = {
11fdf7f2
TL		 187 .init = fme_hdr_init,
188 .uinit = fme_hdr_uinit,
189 .get_prop = fme_hdr_get_prop,
190};
191
192/* thermal management */
193static int fme_thermal_get_threshold1(struct ifpga_fme_hw *fme, u64 *thres1)
194{
195 struct feature_fme_thermal *thermal;
196 struct feature_fme_tmp_threshold temp_threshold;
197
198 thermal = get_fme_feature_ioaddr_by_index(fme,
199 FME_FEATURE_ID_THERMAL_MGMT);
200
201 temp_threshold.csr = readq(&thermal->threshold);
202 *thres1 = temp_threshold.tmp_thshold1;
203
204 return 0;
205}
206
207static int fme_thermal_set_threshold1(struct ifpga_fme_hw *fme, u64 thres1)
208{
209 struct feature_fme_thermal *thermal;
210 struct feature_fme_header *fme_hdr;
211 struct feature_fme_tmp_threshold tmp_threshold;
212 struct feature_fme_capability fme_capability;
213
214 thermal = get_fme_feature_ioaddr_by_index(fme,
215 FME_FEATURE_ID_THERMAL_MGMT);
216 fme_hdr = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
217
218 spinlock_lock(&fme->lock);
219 tmp_threshold.csr = readq(&thermal->threshold);
220 fme_capability.csr = readq(&fme_hdr->capability);
221
222 if (fme_capability.lock_bit == 1) {
223 spinlock_unlock(&fme->lock);
224 return -EBUSY;
225 } else if (thres1 > 100) {
226 spinlock_unlock(&fme->lock);
227 return -EINVAL;
228 } else if (thres1 == 0) {
229 tmp_threshold.tmp_thshold1_enable = 0;
230 tmp_threshold.tmp_thshold1 = thres1;
231 } else {
232 tmp_threshold.tmp_thshold1_enable = 1;
233 tmp_threshold.tmp_thshold1 = thres1;
234 }
235
236 writeq(tmp_threshold.csr, &thermal->threshold);
237 spinlock_unlock(&fme->lock);
238
239 return 0;
240}
241
242static int fme_thermal_get_threshold2(struct ifpga_fme_hw *fme, u64 *thres2)
243{
244 struct feature_fme_thermal *thermal;
245 struct feature_fme_tmp_threshold temp_threshold;
246
247 thermal = get_fme_feature_ioaddr_by_index(fme,
248 FME_FEATURE_ID_THERMAL_MGMT);
249
250 temp_threshold.csr = readq(&thermal->threshold);
251 *thres2 = temp_threshold.tmp_thshold2;
252
253 return 0;
254}
255
256static int fme_thermal_set_threshold2(struct ifpga_fme_hw *fme, u64 thres2)
257{
258 struct feature_fme_thermal *thermal;
259 struct feature_fme_header *fme_hdr;
260 struct feature_fme_tmp_threshold tmp_threshold;
261 struct feature_fme_capability fme_capability;
262
263 thermal = get_fme_feature_ioaddr_by_index(fme,
264 FME_FEATURE_ID_THERMAL_MGMT);
265 fme_hdr = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
266
267 spinlock_lock(&fme->lock);
268 tmp_threshold.csr = readq(&thermal->threshold);
269 fme_capability.csr = readq(&fme_hdr->capability);
270
271 if (fme_capability.lock_bit == 1) {
272 spinlock_unlock(&fme->lock);
273 return -EBUSY;
274 } else if (thres2 > 100) {
275 spinlock_unlock(&fme->lock);
276 return -EINVAL;
277 } else if (thres2 == 0) {
278 tmp_threshold.tmp_thshold2_enable = 0;
279 tmp_threshold.tmp_thshold2 = thres2;
280 } else {
281 tmp_threshold.tmp_thshold2_enable = 1;
282 tmp_threshold.tmp_thshold2 = thres2;
283 }
284
285 writeq(tmp_threshold.csr, &thermal->threshold);
286 spinlock_unlock(&fme->lock);
287
288 return 0;
289}
290
291static int fme_thermal_get_threshold_trip(struct ifpga_fme_hw *fme,
292 u64 *thres_trip)
293{
294 struct feature_fme_thermal *thermal;
295 struct feature_fme_tmp_threshold temp_threshold;
296
297 thermal = get_fme_feature_ioaddr_by_index(fme,
298 FME_FEATURE_ID_THERMAL_MGMT);
299
300 temp_threshold.csr = readq(&thermal->threshold);
301 *thres_trip = temp_threshold.therm_trip_thshold;
302
303 return 0;
304}
305
306static int fme_thermal_get_threshold1_reached(struct ifpga_fme_hw *fme,
307 u64 *thres1_reached)
308{
309 struct feature_fme_thermal *thermal;
310 struct feature_fme_tmp_threshold temp_threshold;
311
312 thermal = get_fme_feature_ioaddr_by_index(fme,
313 FME_FEATURE_ID_THERMAL_MGMT);
314
315 temp_threshold.csr = readq(&thermal->threshold);
316 *thres1_reached = temp_threshold.thshold1_status;
317
318 return 0;
319}
320
321static int fme_thermal_get_threshold2_reached(struct ifpga_fme_hw *fme,
322 u64 *thres1_reached)
323{
324 struct feature_fme_thermal *thermal;
325 struct feature_fme_tmp_threshold temp_threshold;
326
327 thermal = get_fme_feature_ioaddr_by_index(fme,
328 FME_FEATURE_ID_THERMAL_MGMT);
329
330 temp_threshold.csr = readq(&thermal->threshold);
331 *thres1_reached = temp_threshold.thshold2_status;
332
333 return 0;
334}
335
336static int fme_thermal_get_threshold1_policy(struct ifpga_fme_hw *fme,
337 u64 *thres1_policy)
338{
339 struct feature_fme_thermal *thermal;
340 struct feature_fme_tmp_threshold temp_threshold;
341
342 thermal = get_fme_feature_ioaddr_by_index(fme,
343 FME_FEATURE_ID_THERMAL_MGMT);
344
345 temp_threshold.csr = readq(&thermal->threshold);
346 *thres1_policy = temp_threshold.thshold_policy;
347
348 return 0;
349}
350
351static int fme_thermal_set_threshold1_policy(struct ifpga_fme_hw *fme,
352 u64 thres1_policy)
353{
354 struct feature_fme_thermal *thermal;
355 struct feature_fme_tmp_threshold tmp_threshold;
356
357 thermal = get_fme_feature_ioaddr_by_index(fme,
358 FME_FEATURE_ID_THERMAL_MGMT);
359
360 spinlock_lock(&fme->lock);
361 tmp_threshold.csr = readq(&thermal->threshold);
362
363 if (thres1_policy == 0) {
364 tmp_threshold.thshold_policy = 0;
365 } else if (thres1_policy == 1) {
366 tmp_threshold.thshold_policy = 1;
367 } else {
368 spinlock_unlock(&fme->lock);
369 return -EINVAL;
370 }
371
372 writeq(tmp_threshold.csr, &thermal->threshold);
373 spinlock_unlock(&fme->lock);
374
375 return 0;
376}
377
378static int fme_thermal_get_temperature(struct ifpga_fme_hw *fme, u64 *temp)
379{
380 struct feature_fme_thermal *thermal;
381 struct feature_fme_temp_rdsensor_fmt1 temp_rdsensor_fmt1;
382
383 thermal = get_fme_feature_ioaddr_by_index(fme,
384 FME_FEATURE_ID_THERMAL_MGMT);
385
386 temp_rdsensor_fmt1.csr = readq(&thermal->rdsensor_fm1);
387 *temp = temp_rdsensor_fmt1.fpga_temp;
388
389 return 0;
390}
391
392static int fme_thermal_get_revision(struct ifpga_fme_hw *fme, u64 *revision)
393{
394 struct feature_fme_thermal *fme_thermal
395 = get_fme_feature_ioaddr_by_index(fme,
396 FME_FEATURE_ID_THERMAL_MGMT);
397 struct feature_header header;
398
399 header.csr = readq(&fme_thermal->header);
400 *revision = header.revision;
401
402 return 0;
403}
404
405#define FME_THERMAL_CAP_NO_TMP_THRESHOLD 0x1
406
9f95a23c 407static int fme_thermal_mgmt_init(struct ifpga_feature *feature)
11fdf7f2
TL		 408{
409 struct feature_fme_thermal *fme_thermal;
410 struct feature_fme_tmp_threshold_cap thermal_cap;
411
412 UNUSED(feature);
413
414 dev_info(NULL, "FME thermal mgmt Init.\n");
415
416 fme_thermal = (struct feature_fme_thermal *)feature->addr;
417 thermal_cap.csr = readq(&fme_thermal->threshold_cap);
418
419 dev_info(NULL, "FME thermal cap %llx.\n",
420 (unsigned long long)fme_thermal->threshold_cap.csr);
421
422 if (thermal_cap.tmp_thshold_disabled)
423 feature->cap |= FME_THERMAL_CAP_NO_TMP_THRESHOLD;
424
425 return 0;
426}
427
9f95a23c 428static void fme_thermal_mgmt_uinit(struct ifpga_feature *feature)
11fdf7f2
TL		 429{
430 UNUSED(feature);
431
432 dev_info(NULL, "FME thermal mgmt UInit.\n");
433}
434
435static int
9f95a23c 436fme_thermal_set_prop(struct ifpga_feature *feature, struct feature_prop *prop)
11fdf7f2
TL		 437{
438 struct ifpga_fme_hw *fme = feature->parent;
439
440 if (feature->cap & FME_THERMAL_CAP_NO_TMP_THRESHOLD)
441 return -ENOENT;
442
443 switch (prop->prop_id) {
444 case FME_THERMAL_PROP_THRESHOLD1:
445 return fme_thermal_set_threshold1(fme, prop->data);
446 case FME_THERMAL_PROP_THRESHOLD2:
447 return fme_thermal_set_threshold2(fme, prop->data);
448 case FME_THERMAL_PROP_THRESHOLD1_POLICY:
449 return fme_thermal_set_threshold1_policy(fme, prop->data);
450 }
451
452 return -ENOENT;
453}
454
455static int
9f95a23c 456fme_thermal_get_prop(struct ifpga_feature *feature, struct feature_prop *prop)
11fdf7f2
TL		 457{
458 struct ifpga_fme_hw *fme = feature->parent;
459
460 if (feature->cap & FME_THERMAL_CAP_NO_TMP_THRESHOLD &&
461 prop->prop_id != FME_THERMAL_PROP_TEMPERATURE &&
462 prop->prop_id != FME_THERMAL_PROP_REVISION)
463 return -ENOENT;
464
465 switch (prop->prop_id) {
466 case FME_THERMAL_PROP_THRESHOLD1:
467 return fme_thermal_get_threshold1(fme, &prop->data);
468 case FME_THERMAL_PROP_THRESHOLD2:
469 return fme_thermal_get_threshold2(fme, &prop->data);
470 case FME_THERMAL_PROP_THRESHOLD_TRIP:
471 return fme_thermal_get_threshold_trip(fme, &prop->data);
472 case FME_THERMAL_PROP_THRESHOLD1_REACHED:
473 return fme_thermal_get_threshold1_reached(fme, &prop->data);
474 case FME_THERMAL_PROP_THRESHOLD2_REACHED:
475 return fme_thermal_get_threshold2_reached(fme, &prop->data);
476 case FME_THERMAL_PROP_THRESHOLD1_POLICY:
477 return fme_thermal_get_threshold1_policy(fme, &prop->data);
478 case FME_THERMAL_PROP_TEMPERATURE:
479 return fme_thermal_get_temperature(fme, &prop->data);
480 case FME_THERMAL_PROP_REVISION:
481 return fme_thermal_get_revision(fme, &prop->data);
482 }
483
484 return -ENOENT;
485}
486
9f95a23c 487struct ifpga_feature_ops fme_thermal_mgmt_ops = {
11fdf7f2
TL		 488 .init = fme_thermal_mgmt_init,
489 .uinit = fme_thermal_mgmt_uinit,
490 .get_prop = fme_thermal_get_prop,
491 .set_prop = fme_thermal_set_prop,
492};
493
494static int fme_pwr_get_consumed(struct ifpga_fme_hw *fme, u64 *consumed)
495{
496 struct feature_fme_power *fme_power
497 = get_fme_feature_ioaddr_by_index(fme,
498 FME_FEATURE_ID_POWER_MGMT);
499 struct feature_fme_pm_status pm_status;
500
501 pm_status.csr = readq(&fme_power->status);
502
503 *consumed = pm_status.pwr_consumed;
504
505 return 0;
506}
507
508static int fme_pwr_get_threshold1(struct ifpga_fme_hw *fme, u64 *threshold)
509{
510 struct feature_fme_power *fme_power
511 = get_fme_feature_ioaddr_by_index(fme,
512 FME_FEATURE_ID_POWER_MGMT);
513 struct feature_fme_pm_ap_threshold pm_ap_threshold;
514
515 pm_ap_threshold.csr = readq(&fme_power->threshold);
516
517 *threshold = pm_ap_threshold.threshold1;
518
519 return 0;
520}
521
522static int fme_pwr_set_threshold1(struct ifpga_fme_hw *fme, u64 threshold)
523{
524 struct feature_fme_power *fme_power
525 = get_fme_feature_ioaddr_by_index(fme,
526 FME_FEATURE_ID_POWER_MGMT);
527 struct feature_fme_pm_ap_threshold pm_ap_threshold;
528
529 spinlock_lock(&fme->lock);
530 pm_ap_threshold.csr = readq(&fme_power->threshold);
531
532 if (threshold <= PWR_THRESHOLD_MAX) {
533 pm_ap_threshold.threshold1 = threshold;
534 } else {
535 spinlock_unlock(&fme->lock);
536 return -EINVAL;
537 }
538
539 writeq(pm_ap_threshold.csr, &fme_power->threshold);
540 spinlock_unlock(&fme->lock);
541
542 return 0;
543}
544
545static int fme_pwr_get_threshold2(struct ifpga_fme_hw *fme, u64 *threshold)
546{
547 struct feature_fme_power *fme_power
548 = get_fme_feature_ioaddr_by_index(fme,
549 FME_FEATURE_ID_POWER_MGMT);
550 struct feature_fme_pm_ap_threshold pm_ap_threshold;
551
552 pm_ap_threshold.csr = readq(&fme_power->threshold);
553
554 *threshold = pm_ap_threshold.threshold2;
555
556 return 0;
557}
558
559static int fme_pwr_set_threshold2(struct ifpga_fme_hw *fme, u64 threshold)
560{
561 struct feature_fme_power *fme_power
562 = get_fme_feature_ioaddr_by_index(fme,
563 FME_FEATURE_ID_POWER_MGMT);
564 struct feature_fme_pm_ap_threshold pm_ap_threshold;
565
566 spinlock_lock(&fme->lock);
567 pm_ap_threshold.csr = readq(&fme_power->threshold);
568
569 if (threshold <= PWR_THRESHOLD_MAX) {
570 pm_ap_threshold.threshold2 = threshold;
571 } else {
572 spinlock_unlock(&fme->lock);
573 return -EINVAL;
574 }
575
576 writeq(pm_ap_threshold.csr, &fme_power->threshold);
577 spinlock_unlock(&fme->lock);
578
579 return 0;
580}
581
582static int fme_pwr_get_threshold1_status(struct ifpga_fme_hw *fme,
583 u64 *threshold_status)
584{
585 struct feature_fme_power *fme_power
586 = get_fme_feature_ioaddr_by_index(fme,
587 FME_FEATURE_ID_POWER_MGMT);
588 struct feature_fme_pm_ap_threshold pm_ap_threshold;
589
590 pm_ap_threshold.csr = readq(&fme_power->threshold);
591
592 *threshold_status = pm_ap_threshold.threshold1_status;
593
594 return 0;
595}
596
597static int fme_pwr_get_threshold2_status(struct ifpga_fme_hw *fme,
598 u64 *threshold_status)
599{
600 struct feature_fme_power *fme_power
601 = get_fme_feature_ioaddr_by_index(fme,
602 FME_FEATURE_ID_POWER_MGMT);
603 struct feature_fme_pm_ap_threshold pm_ap_threshold;
604
605 pm_ap_threshold.csr = readq(&fme_power->threshold);
606
607 *threshold_status = pm_ap_threshold.threshold2_status;
608
609 return 0;
610}
611
612static int fme_pwr_get_rtl(struct ifpga_fme_hw *fme, u64 *rtl)
613{
614 struct feature_fme_power *fme_power
615 = get_fme_feature_ioaddr_by_index(fme,
616 FME_FEATURE_ID_POWER_MGMT);
617 struct feature_fme_pm_status pm_status;
618
619 pm_status.csr = readq(&fme_power->status);
620
621 *rtl = pm_status.fpga_latency_report;
622
623 return 0;
624}
625
626static int fme_pwr_get_xeon_limit(struct ifpga_fme_hw *fme, u64 *limit)
627{
628 struct feature_fme_power *fme_power
629 = get_fme_feature_ioaddr_by_index(fme,
630 FME_FEATURE_ID_POWER_MGMT);
631 struct feature_fme_pm_xeon_limit xeon_limit;
632
633 xeon_limit.csr = readq(&fme_power->xeon_limit);
634
635 if (!xeon_limit.enable)
636 xeon_limit.pwr_limit = 0;
637
638 *limit = xeon_limit.pwr_limit;
639
640 return 0;
641}
642
643static int fme_pwr_get_fpga_limit(struct ifpga_fme_hw *fme, u64 *limit)
644{
645 struct feature_fme_power *fme_power
646 = get_fme_feature_ioaddr_by_index(fme,
647 FME_FEATURE_ID_POWER_MGMT);
648 struct feature_fme_pm_fpga_limit fpga_limit;
649
650 fpga_limit.csr = readq(&fme_power->fpga_limit);
651
652 if (!fpga_limit.enable)
653 fpga_limit.pwr_limit = 0;
654
655 *limit = fpga_limit.pwr_limit;
656
657 return 0;
658}
659
660static int fme_pwr_get_revision(struct ifpga_fme_hw *fme, u64 *revision)
661{
662 struct feature_fme_power *fme_power
663 = get_fme_feature_ioaddr_by_index(fme,
664 FME_FEATURE_ID_POWER_MGMT);
665 struct feature_header header;
666
667 header.csr = readq(&fme_power->header);
668 *revision = header.revision;
669
670 return 0;
671}
672
9f95a23c 673static int fme_power_mgmt_init(struct ifpga_feature *feature)
11fdf7f2
TL		 674{
675 UNUSED(feature);
676
677 dev_info(NULL, "FME power mgmt Init.\n");
678
679 return 0;
680}
681
9f95a23c 682static void fme_power_mgmt_uinit(struct ifpga_feature *feature)
11fdf7f2
TL		 683{
684 UNUSED(feature);
685
686 dev_info(NULL, "FME power mgmt UInit.\n");
687}
688
9f95a23c 689static int fme_power_mgmt_get_prop(struct ifpga_feature *feature,
11fdf7f2
TL		 690 struct feature_prop *prop)
691{
692 struct ifpga_fme_hw *fme = feature->parent;
693
694 switch (prop->prop_id) {
695 case FME_PWR_PROP_CONSUMED:
696 return fme_pwr_get_consumed(fme, &prop->data);
697 case FME_PWR_PROP_THRESHOLD1:
698 return fme_pwr_get_threshold1(fme, &prop->data);
699 case FME_PWR_PROP_THRESHOLD2:
700 return fme_pwr_get_threshold2(fme, &prop->data);
701 case FME_PWR_PROP_THRESHOLD1_STATUS:
702 return fme_pwr_get_threshold1_status(fme, &prop->data);
703 case FME_PWR_PROP_THRESHOLD2_STATUS:
704 return fme_pwr_get_threshold2_status(fme, &prop->data);
705 case FME_PWR_PROP_RTL:
706 return fme_pwr_get_rtl(fme, &prop->data);
707 case FME_PWR_PROP_XEON_LIMIT:
708 return fme_pwr_get_xeon_limit(fme, &prop->data);
709 case FME_PWR_PROP_FPGA_LIMIT:
710 return fme_pwr_get_fpga_limit(fme, &prop->data);
711 case FME_PWR_PROP_REVISION:
712 return fme_pwr_get_revision(fme, &prop->data);
713 }
714
715 return -ENOENT;
716}
717
9f95a23c 718static int fme_power_mgmt_set_prop(struct ifpga_feature *feature,
11fdf7f2
TL		 719 struct feature_prop *prop)
720{
721 struct ifpga_fme_hw *fme = feature->parent;
722
723 switch (prop->prop_id) {
724 case FME_PWR_PROP_THRESHOLD1:
725 return fme_pwr_set_threshold1(fme, prop->data);
726 case FME_PWR_PROP_THRESHOLD2:
727 return fme_pwr_set_threshold2(fme, prop->data);
728 }
729
730 return -ENOENT;
731}
732
9f95a23c 733struct ifpga_feature_ops fme_power_mgmt_ops = {
11fdf7f2
TL		 734 .init = fme_power_mgmt_init,
735 .uinit = fme_power_mgmt_uinit,
736 .get_prop = fme_power_mgmt_get_prop,
737 .set_prop = fme_power_mgmt_set_prop,
738};
9f95a23c
TL		 739
740static int fme_hssi_eth_init(struct ifpga_feature *feature)
741{
742 UNUSED(feature);
743 return 0;
744}
745
746static void fme_hssi_eth_uinit(struct ifpga_feature *feature)
747{
748 UNUSED(feature);
749}
750
751struct ifpga_feature_ops fme_hssi_eth_ops = {
752 .init = fme_hssi_eth_init,
753 .uinit = fme_hssi_eth_uinit,
754};
755
756static int fme_emif_init(struct ifpga_feature *feature)
757{
758 UNUSED(feature);
759 return 0;
760}
761
762static void fme_emif_uinit(struct ifpga_feature *feature)
763{
764 UNUSED(feature);
765}
766
767struct ifpga_feature_ops fme_emif_ops = {
768 .init = fme_emif_init,
769 .uinit = fme_emif_uinit,
770};
771
772static const char *board_type_to_string(u32 type)
773{
774 switch (type) {
775 case VC_8_10G:
776 return "VC_8x10G";
777 case VC_4_25G:
778 return "VC_4x25G";
779 case VC_2_1_25:
780 return "VC_2x1x25G";
781 case VC_4_25G_2_25G:
782 return "VC_4x25G+2x25G";
783 case VC_2_2_25G:
784 return "VC_2x2x25G";
785 }
786
787 return "unknown";
788}
789
790static int board_type_to_info(u32 type,
791 struct ifpga_fme_board_info *info)
792{
793 switch (type) {
794 case VC_8_10G:
795 info->nums_of_retimer = 2;
796 info->ports_per_retimer = 4;
797 info->nums_of_fvl = 2;
798 info->ports_per_fvl = 4;
799 break;
800 case VC_4_25G:
801 info->nums_of_retimer = 1;
802 info->ports_per_retimer = 4;
803 info->nums_of_fvl = 2;
804 info->ports_per_fvl = 2;
805 break;
806 case VC_2_1_25:
807 info->nums_of_retimer = 2;
808 info->ports_per_retimer = 1;
809 info->nums_of_fvl = 1;
810 info->ports_per_fvl = 2;
811 break;
812 case VC_2_2_25G:
813 info->nums_of_retimer = 2;
814 info->ports_per_retimer = 2;
815 info->nums_of_fvl = 2;
816 info->ports_per_fvl = 2;
817 break;
818 default:
819 return -EINVAL;
820 }
821
822 return 0;
823}
824
825static int fme_get_board_interface(struct ifpga_fme_hw *fme)
826{
827 struct fme_bitstream_id id;
828
829 if (fme_hdr_get_bitstream_id(fme, &id.id))
830 return -EINVAL;
831
832 fme->board_info.type = id.interface;
833 fme->board_info.build_hash = id.hash;
834 fme->board_info.debug_version = id.debug;
835 fme->board_info.major_version = id.major;
836 fme->board_info.minor_version = id.minor;
837
838 dev_info(fme, "board type: %s major_version:%u minor_version:%u build_hash:%u\n",
839 board_type_to_string(fme->board_info.type),
840 fme->board_info.major_version,
841 fme->board_info.minor_version,
842 fme->board_info.build_hash);
843
844 if (board_type_to_info(fme->board_info.type, &fme->board_info))
845 return -EINVAL;
846
847 dev_info(fme, "get board info: nums_retimers %d ports_per_retimer %d nums_fvl %d ports_per_fvl %d\n",
848 fme->board_info.nums_of_retimer,
849 fme->board_info.ports_per_retimer,
850 fme->board_info.nums_of_fvl,
851 fme->board_info.ports_per_fvl);
852
853 return 0;
854}
855
856static int spi_self_checking(void)
857{
858 u32 val;
859 int ret;
860
861 ret = max10_reg_read(0x30043c, &val);
862 if (ret)
863 return -EIO;
864
865 if (val != 0x87654321) {
866 dev_err(NULL, "Read MAX10 test register fail: 0x%x\n", val);
867 return -EIO;
868 }
869
870 dev_info(NULL, "Read MAX10 test register success, SPI self-test done\n");
871
872 return 0;
873}
874
875static int fme_spi_init(struct ifpga_feature *feature)
876{
877 struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
878 struct altera_spi_device *spi_master;
879 struct intel_max10_device *max10;
880 int ret = 0;
881
882 dev_info(fme, "FME SPI Master (Max10) Init.\n");
883 dev_debug(fme, "FME SPI base addr %p.\n",
884 feature->addr);
885 dev_debug(fme, "spi param=0x%llx\n",
886 (unsigned long long)opae_readq(feature->addr + 0x8));
887
888 spi_master = altera_spi_alloc(feature->addr, TYPE_SPI);
889 if (!spi_master)
890 return -ENODEV;
891
892 altera_spi_init(spi_master);
893
894 max10 = intel_max10_device_probe(spi_master, 0);
895 if (!max10) {
896 ret = -ENODEV;
897 dev_err(fme, "max10 init fail\n");
898 goto spi_fail;
899 }
900
901 fme->max10_dev = max10;
902
903 /* SPI self test */
904 if (spi_self_checking()) {
905 ret = -EIO;
906 goto max10_fail;
907 }
908
909 return ret;
910
911max10_fail:
912 intel_max10_device_remove(fme->max10_dev);
913spi_fail:
914 altera_spi_release(spi_master);
915 return ret;
916}
917
918static void fme_spi_uinit(struct ifpga_feature *feature)
919{
920 struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
921
922 if (fme->max10_dev)
923 intel_max10_device_remove(fme->max10_dev);
924}
925
926struct ifpga_feature_ops fme_spi_master_ops = {
927 .init = fme_spi_init,
928 .uinit = fme_spi_uinit,
929};
930
931static int nios_spi_wait_init_done(struct altera_spi_device *dev)
932{
933 u32 val = 0;
934 unsigned long timeout = msecs_to_timer_cycles(10000);
935 unsigned long ticks;
936
937 do {
938 if (spi_reg_read(dev, NIOS_SPI_INIT_DONE, &val))
939 return -EIO;
940 if (val)
941 break;
942
943 ticks = rte_get_timer_cycles();
944 if (time_after(ticks, timeout))
945 return -ETIMEDOUT;
946 msleep(100);
947 } while (!val);
948
949 return 0;
950}
951
952static int nios_spi_check_error(struct altera_spi_device *dev)
953{
954 u32 value = 0;
955
956 if (spi_reg_read(dev, NIOS_SPI_INIT_STS0, &value))
957 return -EIO;
958
959 dev_debug(dev, "SPI init status0 0x%x\n", value);
960
961 /* Error code: 0xFFF0 to 0xFFFC */
962 if (value >= 0xFFF0 && value <= 0xFFFC)
963 return -EINVAL;
964
965 value = 0;
966 if (spi_reg_read(dev, NIOS_SPI_INIT_STS1, &value))
967 return -EIO;
968
969 dev_debug(dev, "SPI init status1 0x%x\n", value);
970
971 /* Error code: 0xFFF0 to 0xFFFC */
972 if (value >= 0xFFF0 && value <= 0xFFFC)
973 return -EINVAL;
974
975 return 0;
976}
977
978static int fme_nios_spi_init(struct ifpga_feature *feature)
979{
980 struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
981 struct altera_spi_device *spi_master;
982 struct intel_max10_device *max10;
983 int ret = 0;
984
985 dev_info(fme, "FME SPI Master (NIOS) Init.\n");
986 dev_debug(fme, "FME SPI base addr %p.\n",
987 feature->addr);
988 dev_debug(fme, "spi param=0x%llx\n",
989 (unsigned long long)opae_readq(feature->addr + 0x8));
990
991 spi_master = altera_spi_alloc(feature->addr, TYPE_NIOS_SPI);
992 if (!spi_master)
993 return -ENODEV;
994
995 /**
996 * 1. wait A10 NIOS initial finished and
997 * release the SPI master to Host
998 */
999 ret = nios_spi_wait_init_done(spi_master);
1000 if (ret != 0) {
1001 dev_err(fme, "FME NIOS_SPI init fail\n");
1002 goto release_dev;
1003 }
1004
1005 dev_info(fme, "FME NIOS_SPI initial done\n");
1006
1007 /* 2. check if error occur? */
1008 if (nios_spi_check_error(spi_master))
1009 dev_info(fme, "NIOS_SPI INIT done, but found some error\n");
1010
1011 /* 3. init the spi master*/
1012 altera_spi_init(spi_master);
1013
1014 /* init the max10 device */
1015 max10 = intel_max10_device_probe(spi_master, 0);
1016 if (!max10) {
1017 ret = -ENODEV;
1018 dev_err(fme, "max10 init fail\n");
1019 goto release_dev;
1020 }
1021
1022 fme_get_board_interface(fme);
1023
1024 fme->max10_dev = max10;
1025
1026 /* SPI self test */
1027 if (spi_self_checking())
1028 goto spi_fail;
1029
1030 return ret;
1031
1032spi_fail:
1033 intel_max10_device_remove(fme->max10_dev);
1034release_dev:
1035 altera_spi_release(spi_master);
1036 return -ENODEV;
1037}
1038
1039static void fme_nios_spi_uinit(struct ifpga_feature *feature)
1040{
1041 struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
1042
1043 if (fme->max10_dev)
1044 intel_max10_device_remove(fme->max10_dev);
1045}
1046
1047struct ifpga_feature_ops fme_nios_spi_master_ops = {
1048 .init = fme_nios_spi_init,
1049 .uinit = fme_nios_spi_uinit,
1050};
1051
1052static int i2c_mac_rom_test(struct altera_i2c_dev *dev)
1053{
1054 char buf[20];
1055 int ret;
1056 char read_buf[20] = {0,};
1057 const char *string = "1a2b3c4d5e";
1058
1059 opae_memcpy(buf, string, strlen(string));
1060
1061 ret = at24_eeprom_write(dev, AT24512_SLAVE_ADDR, 0,
1062 (u8 *)buf, strlen(string));
1063 if (ret < 0) {
1064 dev_err(NULL, "write i2c error:%d\n", ret);
1065 return ret;
1066 }
1067
1068 ret = at24_eeprom_read(dev, AT24512_SLAVE_ADDR, 0,
1069 (u8 *)read_buf, strlen(string));
1070 if (ret < 0) {
1071 dev_err(NULL, "read i2c error:%d\n", ret);
1072 return ret;
1073 }
1074
1075 if (memcmp(buf, read_buf, strlen(string))) {
1076 dev_err(NULL, "%s test fail!\n", __func__);
1077 return -EFAULT;
1078 }
1079
1080 dev_info(NULL, "%s test successful\n", __func__);
1081
1082 return 0;
1083}
1084
1085static int fme_i2c_init(struct ifpga_feature *feature)
1086{
1087 struct feature_fme_i2c *i2c;
1088 struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
1089
1090 i2c = (struct feature_fme_i2c *)feature->addr;
1091
1092 dev_info(NULL, "FME I2C Master Init.\n");
1093
1094 fme->i2c_master = altera_i2c_probe(i2c);
1095 if (!fme->i2c_master)
1096 return -ENODEV;
1097
1098 /* MAC ROM self test */
1099 i2c_mac_rom_test(fme->i2c_master);
1100
1101 return 0;
1102}
1103
1104static void fme_i2c_uninit(struct ifpga_feature *feature)
1105{
1106 struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
1107
1108 altera_i2c_remove(fme->i2c_master);
1109}
1110
1111struct ifpga_feature_ops fme_i2c_master_ops = {
1112 .init = fme_i2c_init,
1113 .uinit = fme_i2c_uninit,
1114};
1115
1116static int fme_eth_group_init(struct ifpga_feature *feature)
1117{
1118 struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
1119 struct eth_group_device *dev;
1120
1121 dev = (struct eth_group_device *)eth_group_probe(feature->addr);
1122 if (!dev)
1123 return -ENODEV;
1124
1125 fme->eth_dev[dev->group_id] = dev;
1126
1127 fme->eth_group_region[dev->group_id].addr =
1128 feature->addr;
1129 fme->eth_group_region[dev->group_id].phys_addr =
1130 feature->phys_addr;
1131 fme->eth_group_region[dev->group_id].len =
1132 feature->size;
1133
1134 fme->nums_eth_dev++;
1135
1136 dev_info(NULL, "FME PHY Group %d Init.\n", dev->group_id);
1137 dev_info(NULL, "found %d eth group, addr %p phys_addr 0x%llx len %u\n",
1138 dev->group_id, feature->addr,
1139 (unsigned long long)feature->phys_addr,
1140 feature->size);
1141
1142 return 0;
1143}
1144
1145static void fme_eth_group_uinit(struct ifpga_feature *feature)
1146{
1147 UNUSED(feature);
1148}
1149
1150struct ifpga_feature_ops fme_eth_group_ops = {
1151 .init = fme_eth_group_init,
1152 .uinit = fme_eth_group_uinit,
1153};
1154
1155int fme_mgr_read_mac_rom(struct ifpga_fme_hw *fme, int offset,
1156 void *buf, int size)
1157{
1158 struct altera_i2c_dev *dev;
1159
1160 dev = fme->i2c_master;
1161 if (!dev)
1162 return -ENODEV;
1163
1164 return at24_eeprom_read(dev, AT24512_SLAVE_ADDR, offset, buf, size);
1165}
1166
1167int fme_mgr_write_mac_rom(struct ifpga_fme_hw *fme, int offset,
1168 void *buf, int size)
1169{
1170 struct altera_i2c_dev *dev;
1171
1172 dev = fme->i2c_master;
1173 if (!dev)
1174 return -ENODEV;
1175
1176 return at24_eeprom_write(dev, AT24512_SLAVE_ADDR, offset, buf, size);
1177}
1178
1179static struct eth_group_device *get_eth_group_dev(struct ifpga_fme_hw *fme,
1180 u8 group_id)
1181{
1182 struct eth_group_device *dev;
1183
1184 if (group_id > (MAX_ETH_GROUP_DEVICES - 1))
1185 return NULL;
1186
1187 dev = (struct eth_group_device *)fme->eth_dev[group_id];
1188 if (!dev)
1189 return NULL;
1190
1191 if (dev->status != ETH_GROUP_DEV_ATTACHED)
1192 return NULL;
1193
1194 return dev;
1195}
1196
1197int fme_mgr_get_eth_group_nums(struct ifpga_fme_hw *fme)
1198{
1199 return fme->nums_eth_dev;
1200}
1201
1202int fme_mgr_get_eth_group_info(struct ifpga_fme_hw *fme,
1203 u8 group_id, struct opae_eth_group_info *info)
1204{
1205 struct eth_group_device *dev;
1206
1207 dev = get_eth_group_dev(fme, group_id);
1208 if (!dev)
1209 return -ENODEV;
1210
1211 info->group_id = group_id;
1212 info->speed = dev->speed;
1213 info->nums_of_mac = dev->mac_num;
1214 info->nums_of_phy = dev->phy_num;
1215
1216 return 0;
1217}
1218
1219int fme_mgr_eth_group_read_reg(struct ifpga_fme_hw *fme, u8 group_id,
1220 u8 type, u8 index, u16 addr, u32 *data)
1221{
1222 struct eth_group_device *dev;
1223
1224 dev = get_eth_group_dev(fme, group_id);
1225 if (!dev)
1226 return -ENODEV;
1227
1228 return eth_group_read_reg(dev, type, index, addr, data);
1229}
1230
1231int fme_mgr_eth_group_write_reg(struct ifpga_fme_hw *fme, u8 group_id,
1232 u8 type, u8 index, u16 addr, u32 data)
1233{
1234 struct eth_group_device *dev;
1235
1236 dev = get_eth_group_dev(fme, group_id);
1237 if (!dev)
1238 return -ENODEV;
1239
1240 return eth_group_write_reg(dev, type, index, addr, data);
1241}
1242
1243static int fme_get_eth_group_speed(struct ifpga_fme_hw *fme,
1244 u8 group_id)
1245{
1246 struct eth_group_device *dev;
1247
1248 dev = get_eth_group_dev(fme, group_id);
1249 if (!dev)
1250 return -ENODEV;
1251
1252 return dev->speed;
1253}
1254
1255int fme_mgr_get_retimer_info(struct ifpga_fme_hw *fme,
1256 struct opae_retimer_info *info)
1257{
1258 struct intel_max10_device *dev;
1259
1260 dev = (struct intel_max10_device *)fme->max10_dev;
1261 if (!dev)
1262 return -ENODEV;
1263
1264 info->nums_retimer = fme->board_info.nums_of_retimer;
1265 info->ports_per_retimer = fme->board_info.ports_per_retimer;
1266 info->nums_fvl = fme->board_info.nums_of_fvl;
1267 info->ports_per_fvl = fme->board_info.ports_per_fvl;
1268
1269 /* The speed of PKVL is identical the eth group's speed */
1270 info->support_speed = fme_get_eth_group_speed(fme,
1271 LINE_SIDE_GROUP_ID);
1272
1273 return 0;
1274}
1275
1276int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,
1277 struct opae_retimer_status *status)
1278{
1279 struct intel_max10_device *dev;
1280 unsigned int val;
1281
1282 dev = (struct intel_max10_device *)fme->max10_dev;
1283 if (!dev)
1284 return -ENODEV;
1285
1286 if (max10_reg_read(PKVL_LINK_STATUS, &val)) {
1287 dev_err(dev, "%s: read pkvl status fail\n", __func__);
1288 return -EINVAL;
1289 }
1290
1291 /* The speed of PKVL is identical the eth group's speed */
1292 status->speed = fme_get_eth_group_speed(fme,
1293 LINE_SIDE_GROUP_ID);
1294
1295 status->line_link_bitmap = val;
1296
1297 dev_debug(dev, "get retimer status: speed:%d. line_link_bitmap:0x%x\n",
1298 status->speed,
1299 status->line_link_bitmap);
1300
1301 return 0;
1302}
Ceph