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11fdf7f2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
7c673cae FG |
2 | /******************************************************************************* |
3 | ||
4 | Intel(R) Gigabit Ethernet Linux driver | |
5 | Copyright(c) 2007-2013 Intel Corporation. | |
6 | ||
7c673cae FG |
7 | Contact Information: |
8 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
9 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
10 | ||
11 | *******************************************************************************/ | |
12 | ||
13 | #include "e1000_api.h" | |
14 | ||
15 | static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); | |
16 | static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); | |
17 | static void e1000_config_collision_dist_generic(struct e1000_hw *hw); | |
18 | static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); | |
19 | ||
20 | /** | |
21 | * e1000_init_mac_ops_generic - Initialize MAC function pointers | |
22 | * @hw: pointer to the HW structure | |
23 | * | |
24 | * Setups up the function pointers to no-op functions | |
25 | **/ | |
26 | void e1000_init_mac_ops_generic(struct e1000_hw *hw) | |
27 | { | |
28 | struct e1000_mac_info *mac = &hw->mac; | |
29 | DEBUGFUNC("e1000_init_mac_ops_generic"); | |
30 | ||
31 | /* General Setup */ | |
32 | mac->ops.init_params = e1000_null_ops_generic; | |
33 | mac->ops.init_hw = e1000_null_ops_generic; | |
34 | mac->ops.reset_hw = e1000_null_ops_generic; | |
35 | mac->ops.setup_physical_interface = e1000_null_ops_generic; | |
36 | mac->ops.get_bus_info = e1000_null_ops_generic; | |
37 | mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; | |
38 | mac->ops.read_mac_addr = e1000_read_mac_addr_generic; | |
39 | mac->ops.config_collision_dist = e1000_config_collision_dist_generic; | |
40 | mac->ops.clear_hw_cntrs = e1000_null_mac_generic; | |
41 | /* LED */ | |
42 | mac->ops.cleanup_led = e1000_null_ops_generic; | |
43 | mac->ops.setup_led = e1000_null_ops_generic; | |
44 | mac->ops.blink_led = e1000_null_ops_generic; | |
45 | mac->ops.led_on = e1000_null_ops_generic; | |
46 | mac->ops.led_off = e1000_null_ops_generic; | |
47 | /* LINK */ | |
48 | mac->ops.setup_link = e1000_null_ops_generic; | |
49 | mac->ops.get_link_up_info = e1000_null_link_info; | |
50 | mac->ops.check_for_link = e1000_null_ops_generic; | |
51 | /* Management */ | |
52 | mac->ops.check_mng_mode = e1000_null_mng_mode; | |
53 | /* VLAN, MC, etc. */ | |
54 | mac->ops.update_mc_addr_list = e1000_null_update_mc; | |
55 | mac->ops.clear_vfta = e1000_null_mac_generic; | |
56 | mac->ops.write_vfta = e1000_null_write_vfta; | |
57 | mac->ops.rar_set = e1000_rar_set_generic; | |
58 | mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; | |
59 | } | |
60 | ||
61 | /** | |
62 | * e1000_null_ops_generic - No-op function, returns 0 | |
63 | * @hw: pointer to the HW structure | |
64 | **/ | |
65 | s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) | |
66 | { | |
67 | DEBUGFUNC("e1000_null_ops_generic"); | |
68 | return E1000_SUCCESS; | |
69 | } | |
70 | ||
71 | /** | |
72 | * e1000_null_mac_generic - No-op function, return void | |
73 | * @hw: pointer to the HW structure | |
74 | **/ | |
75 | void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) | |
76 | { | |
77 | DEBUGFUNC("e1000_null_mac_generic"); | |
78 | return; | |
79 | } | |
80 | ||
81 | /** | |
82 | * e1000_null_link_info - No-op function, return 0 | |
83 | * @hw: pointer to the HW structure | |
84 | **/ | |
85 | s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, | |
86 | u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) | |
87 | { | |
88 | DEBUGFUNC("e1000_null_link_info"); | |
89 | return E1000_SUCCESS; | |
90 | } | |
91 | ||
92 | /** | |
93 | * e1000_null_mng_mode - No-op function, return false | |
94 | * @hw: pointer to the HW structure | |
95 | **/ | |
96 | bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) | |
97 | { | |
98 | DEBUGFUNC("e1000_null_mng_mode"); | |
99 | return false; | |
100 | } | |
101 | ||
102 | /** | |
103 | * e1000_null_update_mc - No-op function, return void | |
104 | * @hw: pointer to the HW structure | |
105 | **/ | |
106 | void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, | |
107 | u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) | |
108 | { | |
109 | DEBUGFUNC("e1000_null_update_mc"); | |
110 | return; | |
111 | } | |
112 | ||
113 | /** | |
114 | * e1000_null_write_vfta - No-op function, return void | |
115 | * @hw: pointer to the HW structure | |
116 | **/ | |
117 | void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, | |
118 | u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) | |
119 | { | |
120 | DEBUGFUNC("e1000_null_write_vfta"); | |
121 | return; | |
122 | } | |
123 | ||
124 | /** | |
125 | * e1000_null_rar_set - No-op function, return void | |
126 | * @hw: pointer to the HW structure | |
127 | **/ | |
128 | void e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, | |
129 | u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) | |
130 | { | |
131 | DEBUGFUNC("e1000_null_rar_set"); | |
132 | return; | |
133 | } | |
134 | ||
135 | /** | |
136 | * e1000_get_bus_info_pcie_generic - Get PCIe bus information | |
137 | * @hw: pointer to the HW structure | |
138 | * | |
139 | * Determines and stores the system bus information for a particular | |
140 | * network interface. The following bus information is determined and stored: | |
141 | * bus speed, bus width, type (PCIe), and PCIe function. | |
142 | **/ | |
143 | s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) | |
144 | { | |
145 | struct e1000_mac_info *mac = &hw->mac; | |
146 | struct e1000_bus_info *bus = &hw->bus; | |
147 | s32 ret_val; | |
148 | u16 pcie_link_status; | |
149 | ||
150 | DEBUGFUNC("e1000_get_bus_info_pcie_generic"); | |
151 | ||
152 | bus->type = e1000_bus_type_pci_express; | |
153 | ||
154 | ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, | |
155 | &pcie_link_status); | |
156 | if (ret_val) { | |
157 | bus->width = e1000_bus_width_unknown; | |
158 | bus->speed = e1000_bus_speed_unknown; | |
159 | } else { | |
160 | switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { | |
161 | case PCIE_LINK_SPEED_2500: | |
162 | bus->speed = e1000_bus_speed_2500; | |
163 | break; | |
164 | case PCIE_LINK_SPEED_5000: | |
165 | bus->speed = e1000_bus_speed_5000; | |
166 | break; | |
167 | default: | |
168 | bus->speed = e1000_bus_speed_unknown; | |
169 | break; | |
170 | } | |
171 | ||
172 | bus->width = (enum e1000_bus_width)((pcie_link_status & | |
173 | PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); | |
174 | } | |
175 | ||
176 | mac->ops.set_lan_id(hw); | |
177 | ||
178 | return E1000_SUCCESS; | |
179 | } | |
180 | ||
181 | /** | |
182 | * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices | |
183 | * | |
184 | * @hw: pointer to the HW structure | |
185 | * | |
186 | * Determines the LAN function id by reading memory-mapped registers | |
187 | * and swaps the port value if requested. | |
188 | **/ | |
189 | static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) | |
190 | { | |
191 | struct e1000_bus_info *bus = &hw->bus; | |
192 | u32 reg; | |
193 | ||
194 | /* The status register reports the correct function number | |
195 | * for the device regardless of function swap state. | |
196 | */ | |
197 | reg = E1000_READ_REG(hw, E1000_STATUS); | |
198 | bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; | |
199 | } | |
200 | ||
201 | /** | |
202 | * e1000_set_lan_id_single_port - Set LAN id for a single port device | |
203 | * @hw: pointer to the HW structure | |
204 | * | |
205 | * Sets the LAN function id to zero for a single port device. | |
206 | **/ | |
207 | void e1000_set_lan_id_single_port(struct e1000_hw *hw) | |
208 | { | |
209 | struct e1000_bus_info *bus = &hw->bus; | |
210 | ||
211 | bus->func = 0; | |
212 | } | |
213 | ||
214 | /** | |
215 | * e1000_clear_vfta_generic - Clear VLAN filter table | |
216 | * @hw: pointer to the HW structure | |
217 | * | |
218 | * Clears the register array which contains the VLAN filter table by | |
219 | * setting all the values to 0. | |
220 | **/ | |
221 | void e1000_clear_vfta_generic(struct e1000_hw *hw) | |
222 | { | |
223 | u32 offset; | |
224 | ||
225 | DEBUGFUNC("e1000_clear_vfta_generic"); | |
226 | ||
227 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
228 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); | |
229 | E1000_WRITE_FLUSH(hw); | |
230 | } | |
231 | } | |
232 | ||
233 | /** | |
234 | * e1000_write_vfta_generic - Write value to VLAN filter table | |
235 | * @hw: pointer to the HW structure | |
236 | * @offset: register offset in VLAN filter table | |
237 | * @value: register value written to VLAN filter table | |
238 | * | |
239 | * Writes value at the given offset in the register array which stores | |
240 | * the VLAN filter table. | |
241 | **/ | |
242 | void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) | |
243 | { | |
244 | DEBUGFUNC("e1000_write_vfta_generic"); | |
245 | ||
246 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); | |
247 | E1000_WRITE_FLUSH(hw); | |
248 | } | |
249 | ||
250 | /** | |
251 | * e1000_init_rx_addrs_generic - Initialize receive address's | |
252 | * @hw: pointer to the HW structure | |
253 | * @rar_count: receive address registers | |
254 | * | |
255 | * Setup the receive address registers by setting the base receive address | |
256 | * register to the devices MAC address and clearing all the other receive | |
257 | * address registers to 0. | |
258 | **/ | |
259 | void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) | |
260 | { | |
261 | u32 i; | |
262 | u8 mac_addr[ETH_ADDR_LEN] = {0}; | |
263 | ||
264 | DEBUGFUNC("e1000_init_rx_addrs_generic"); | |
265 | ||
266 | /* Setup the receive address */ | |
267 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | |
268 | ||
269 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); | |
270 | ||
271 | /* Zero out the other (rar_entry_count - 1) receive addresses */ | |
272 | DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); | |
273 | for (i = 1; i < rar_count; i++) | |
274 | hw->mac.ops.rar_set(hw, mac_addr, i); | |
275 | } | |
276 | ||
277 | /** | |
278 | * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr | |
279 | * @hw: pointer to the HW structure | |
280 | * | |
281 | * Checks the nvm for an alternate MAC address. An alternate MAC address | |
282 | * can be setup by pre-boot software and must be treated like a permanent | |
283 | * address and must override the actual permanent MAC address. If an | |
284 | * alternate MAC address is found it is programmed into RAR0, replacing | |
285 | * the permanent address that was installed into RAR0 by the Si on reset. | |
286 | * This function will return SUCCESS unless it encounters an error while | |
287 | * reading the EEPROM. | |
288 | **/ | |
289 | s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) | |
290 | { | |
291 | u32 i; | |
292 | s32 ret_val; | |
293 | u16 offset, nvm_alt_mac_addr_offset, nvm_data; | |
294 | u8 alt_mac_addr[ETH_ADDR_LEN]; | |
295 | ||
296 | DEBUGFUNC("e1000_check_alt_mac_addr_generic"); | |
297 | ||
298 | ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); | |
299 | if (ret_val) | |
300 | return ret_val; | |
301 | ||
302 | ||
303 | /* Alternate MAC address is handled by the option ROM for 82580 | |
304 | * and newer. SW support not required. | |
305 | */ | |
306 | if (hw->mac.type >= e1000_82580) | |
307 | return E1000_SUCCESS; | |
308 | ||
309 | ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, | |
310 | &nvm_alt_mac_addr_offset); | |
311 | if (ret_val) { | |
312 | DEBUGOUT("NVM Read Error\n"); | |
313 | return ret_val; | |
314 | } | |
315 | ||
316 | if ((nvm_alt_mac_addr_offset == 0xFFFF) || | |
317 | (nvm_alt_mac_addr_offset == 0x0000)) | |
318 | /* There is no Alternate MAC Address */ | |
319 | return E1000_SUCCESS; | |
320 | ||
321 | if (hw->bus.func == E1000_FUNC_1) | |
322 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; | |
323 | if (hw->bus.func == E1000_FUNC_2) | |
324 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; | |
325 | ||
326 | if (hw->bus.func == E1000_FUNC_3) | |
327 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; | |
328 | for (i = 0; i < ETH_ADDR_LEN; i += 2) { | |
329 | offset = nvm_alt_mac_addr_offset + (i >> 1); | |
330 | ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); | |
331 | if (ret_val) { | |
332 | DEBUGOUT("NVM Read Error\n"); | |
333 | return ret_val; | |
334 | } | |
335 | ||
336 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); | |
337 | alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); | |
338 | } | |
339 | ||
340 | /* if multicast bit is set, the alternate address will not be used */ | |
341 | if (alt_mac_addr[0] & 0x01) { | |
342 | DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); | |
343 | return E1000_SUCCESS; | |
344 | } | |
345 | ||
346 | /* We have a valid alternate MAC address, and we want to treat it the | |
347 | * same as the normal permanent MAC address stored by the HW into the | |
348 | * RAR. Do this by mapping this address into RAR0. | |
349 | */ | |
350 | hw->mac.ops.rar_set(hw, alt_mac_addr, 0); | |
351 | ||
352 | return E1000_SUCCESS; | |
353 | } | |
354 | ||
355 | /** | |
356 | * e1000_rar_set_generic - Set receive address register | |
357 | * @hw: pointer to the HW structure | |
358 | * @addr: pointer to the receive address | |
359 | * @index: receive address array register | |
360 | * | |
361 | * Sets the receive address array register at index to the address passed | |
362 | * in by addr. | |
363 | **/ | |
364 | static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) | |
365 | { | |
366 | u32 rar_low, rar_high; | |
367 | ||
368 | DEBUGFUNC("e1000_rar_set_generic"); | |
369 | ||
370 | /* HW expects these in little endian so we reverse the byte order | |
371 | * from network order (big endian) to little endian | |
372 | */ | |
373 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
374 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
375 | ||
376 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
377 | ||
378 | /* If MAC address zero, no need to set the AV bit */ | |
379 | if (rar_low || rar_high) | |
380 | rar_high |= E1000_RAH_AV; | |
381 | ||
382 | /* Some bridges will combine consecutive 32-bit writes into | |
383 | * a single burst write, which will malfunction on some parts. | |
384 | * The flushes avoid this. | |
385 | */ | |
386 | E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); | |
387 | E1000_WRITE_FLUSH(hw); | |
388 | E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); | |
389 | E1000_WRITE_FLUSH(hw); | |
390 | } | |
391 | ||
392 | /** | |
393 | * e1000_hash_mc_addr_generic - Generate a multicast hash value | |
394 | * @hw: pointer to the HW structure | |
395 | * @mc_addr: pointer to a multicast address | |
396 | * | |
397 | * Generates a multicast address hash value which is used to determine | |
398 | * the multicast filter table array address and new table value. | |
399 | **/ | |
400 | u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) | |
401 | { | |
402 | u32 hash_value, hash_mask; | |
403 | u8 bit_shift = 0; | |
404 | ||
405 | DEBUGFUNC("e1000_hash_mc_addr_generic"); | |
406 | ||
407 | /* Register count multiplied by bits per register */ | |
408 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; | |
409 | ||
410 | /* For a mc_filter_type of 0, bit_shift is the number of left-shifts | |
411 | * where 0xFF would still fall within the hash mask. | |
412 | */ | |
413 | while (hash_mask >> bit_shift != 0xFF) | |
414 | bit_shift++; | |
415 | ||
416 | /* The portion of the address that is used for the hash table | |
417 | * is determined by the mc_filter_type setting. | |
418 | * The algorithm is such that there is a total of 8 bits of shifting. | |
419 | * The bit_shift for a mc_filter_type of 0 represents the number of | |
420 | * left-shifts where the MSB of mc_addr[5] would still fall within | |
421 | * the hash_mask. Case 0 does this exactly. Since there are a total | |
422 | * of 8 bits of shifting, then mc_addr[4] will shift right the | |
423 | * remaining number of bits. Thus 8 - bit_shift. The rest of the | |
424 | * cases are a variation of this algorithm...essentially raising the | |
425 | * number of bits to shift mc_addr[5] left, while still keeping the | |
426 | * 8-bit shifting total. | |
427 | * | |
428 | * For example, given the following Destination MAC Address and an | |
429 | * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), | |
430 | * we can see that the bit_shift for case 0 is 4. These are the hash | |
431 | * values resulting from each mc_filter_type... | |
432 | * [0] [1] [2] [3] [4] [5] | |
433 | * 01 AA 00 12 34 56 | |
434 | * LSB MSB | |
435 | * | |
436 | * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 | |
437 | * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 | |
438 | * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 | |
439 | * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 | |
440 | */ | |
441 | switch (hw->mac.mc_filter_type) { | |
442 | default: | |
443 | case 0: | |
444 | break; | |
445 | case 1: | |
446 | bit_shift += 1; | |
447 | break; | |
448 | case 2: | |
449 | bit_shift += 2; | |
450 | break; | |
451 | case 3: | |
452 | bit_shift += 4; | |
453 | break; | |
454 | } | |
455 | ||
456 | hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | | |
457 | (((u16) mc_addr[5]) << bit_shift))); | |
458 | ||
459 | return hash_value; | |
460 | } | |
461 | ||
462 | /** | |
463 | * e1000_update_mc_addr_list_generic - Update Multicast addresses | |
464 | * @hw: pointer to the HW structure | |
465 | * @mc_addr_list: array of multicast addresses to program | |
466 | * @mc_addr_count: number of multicast addresses to program | |
467 | * | |
468 | * Updates entire Multicast Table Array. | |
469 | * The caller must have a packed mc_addr_list of multicast addresses. | |
470 | **/ | |
471 | void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, | |
472 | u8 *mc_addr_list, u32 mc_addr_count) | |
473 | { | |
474 | u32 hash_value, hash_bit, hash_reg; | |
475 | int i; | |
476 | ||
477 | DEBUGFUNC("e1000_update_mc_addr_list_generic"); | |
478 | ||
479 | /* clear mta_shadow */ | |
480 | memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); | |
481 | ||
482 | /* update mta_shadow from mc_addr_list */ | |
483 | for (i = 0; (u32) i < mc_addr_count; i++) { | |
484 | hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); | |
485 | ||
486 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); | |
487 | hash_bit = hash_value & 0x1F; | |
488 | ||
489 | hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); | |
490 | mc_addr_list += (ETH_ADDR_LEN); | |
491 | } | |
492 | ||
493 | /* replace the entire MTA table */ | |
494 | for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) | |
495 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); | |
496 | E1000_WRITE_FLUSH(hw); | |
497 | } | |
498 | ||
499 | /** | |
500 | * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters | |
501 | * @hw: pointer to the HW structure | |
502 | * | |
503 | * Clears the base hardware counters by reading the counter registers. | |
504 | **/ | |
505 | void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) | |
506 | { | |
507 | DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); | |
508 | ||
509 | E1000_READ_REG(hw, E1000_CRCERRS); | |
510 | E1000_READ_REG(hw, E1000_SYMERRS); | |
511 | E1000_READ_REG(hw, E1000_MPC); | |
512 | E1000_READ_REG(hw, E1000_SCC); | |
513 | E1000_READ_REG(hw, E1000_ECOL); | |
514 | E1000_READ_REG(hw, E1000_MCC); | |
515 | E1000_READ_REG(hw, E1000_LATECOL); | |
516 | E1000_READ_REG(hw, E1000_COLC); | |
517 | E1000_READ_REG(hw, E1000_DC); | |
518 | E1000_READ_REG(hw, E1000_SEC); | |
519 | E1000_READ_REG(hw, E1000_RLEC); | |
520 | E1000_READ_REG(hw, E1000_XONRXC); | |
521 | E1000_READ_REG(hw, E1000_XONTXC); | |
522 | E1000_READ_REG(hw, E1000_XOFFRXC); | |
523 | E1000_READ_REG(hw, E1000_XOFFTXC); | |
524 | E1000_READ_REG(hw, E1000_FCRUC); | |
525 | E1000_READ_REG(hw, E1000_GPRC); | |
526 | E1000_READ_REG(hw, E1000_BPRC); | |
527 | E1000_READ_REG(hw, E1000_MPRC); | |
528 | E1000_READ_REG(hw, E1000_GPTC); | |
529 | E1000_READ_REG(hw, E1000_GORCL); | |
530 | E1000_READ_REG(hw, E1000_GORCH); | |
531 | E1000_READ_REG(hw, E1000_GOTCL); | |
532 | E1000_READ_REG(hw, E1000_GOTCH); | |
533 | E1000_READ_REG(hw, E1000_RNBC); | |
534 | E1000_READ_REG(hw, E1000_RUC); | |
535 | E1000_READ_REG(hw, E1000_RFC); | |
536 | E1000_READ_REG(hw, E1000_ROC); | |
537 | E1000_READ_REG(hw, E1000_RJC); | |
538 | E1000_READ_REG(hw, E1000_TORL); | |
539 | E1000_READ_REG(hw, E1000_TORH); | |
540 | E1000_READ_REG(hw, E1000_TOTL); | |
541 | E1000_READ_REG(hw, E1000_TOTH); | |
542 | E1000_READ_REG(hw, E1000_TPR); | |
543 | E1000_READ_REG(hw, E1000_TPT); | |
544 | E1000_READ_REG(hw, E1000_MPTC); | |
545 | E1000_READ_REG(hw, E1000_BPTC); | |
546 | } | |
547 | ||
548 | /** | |
549 | * e1000_check_for_copper_link_generic - Check for link (Copper) | |
550 | * @hw: pointer to the HW structure | |
551 | * | |
552 | * Checks to see of the link status of the hardware has changed. If a | |
553 | * change in link status has been detected, then we read the PHY registers | |
554 | * to get the current speed/duplex if link exists. | |
555 | **/ | |
556 | s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) | |
557 | { | |
558 | struct e1000_mac_info *mac = &hw->mac; | |
559 | s32 ret_val; | |
560 | bool link; | |
561 | ||
562 | DEBUGFUNC("e1000_check_for_copper_link"); | |
563 | ||
564 | /* We only want to go out to the PHY registers to see if Auto-Neg | |
565 | * has completed and/or if our link status has changed. The | |
566 | * get_link_status flag is set upon receiving a Link Status | |
567 | * Change or Rx Sequence Error interrupt. | |
568 | */ | |
569 | if (!mac->get_link_status) | |
570 | return E1000_SUCCESS; | |
571 | ||
572 | /* First we want to see if the MII Status Register reports | |
573 | * link. If so, then we want to get the current speed/duplex | |
574 | * of the PHY. | |
575 | */ | |
576 | ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); | |
577 | if (ret_val) | |
578 | return ret_val; | |
579 | ||
580 | if (!link) | |
581 | return E1000_SUCCESS; /* No link detected */ | |
582 | ||
583 | mac->get_link_status = false; | |
584 | ||
585 | /* Check if there was DownShift, must be checked | |
586 | * immediately after link-up | |
587 | */ | |
588 | e1000_check_downshift_generic(hw); | |
589 | ||
590 | /* If we are forcing speed/duplex, then we simply return since | |
591 | * we have already determined whether we have link or not. | |
592 | */ | |
593 | if (!mac->autoneg) | |
594 | return -E1000_ERR_CONFIG; | |
595 | ||
596 | /* Auto-Neg is enabled. Auto Speed Detection takes care | |
597 | * of MAC speed/duplex configuration. So we only need to | |
598 | * configure Collision Distance in the MAC. | |
599 | */ | |
600 | mac->ops.config_collision_dist(hw); | |
601 | ||
602 | /* Configure Flow Control now that Auto-Neg has completed. | |
603 | * First, we need to restore the desired flow control | |
604 | * settings because we may have had to re-autoneg with a | |
605 | * different link partner. | |
606 | */ | |
607 | ret_val = e1000_config_fc_after_link_up_generic(hw); | |
608 | if (ret_val) | |
609 | DEBUGOUT("Error configuring flow control\n"); | |
610 | ||
611 | return ret_val; | |
612 | } | |
613 | ||
614 | /** | |
615 | * e1000_check_for_fiber_link_generic - Check for link (Fiber) | |
616 | * @hw: pointer to the HW structure | |
617 | * | |
618 | * Checks for link up on the hardware. If link is not up and we have | |
619 | * a signal, then we need to force link up. | |
620 | **/ | |
621 | s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) | |
622 | { | |
623 | struct e1000_mac_info *mac = &hw->mac; | |
624 | u32 rxcw; | |
625 | u32 ctrl; | |
626 | u32 status; | |
627 | s32 ret_val; | |
628 | ||
629 | DEBUGFUNC("e1000_check_for_fiber_link_generic"); | |
630 | ||
631 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
632 | status = E1000_READ_REG(hw, E1000_STATUS); | |
633 | rxcw = E1000_READ_REG(hw, E1000_RXCW); | |
634 | ||
635 | /* If we don't have link (auto-negotiation failed or link partner | |
636 | * cannot auto-negotiate), the cable is plugged in (we have signal), | |
637 | * and our link partner is not trying to auto-negotiate with us (we | |
638 | * are receiving idles or data), we need to force link up. We also | |
639 | * need to give auto-negotiation time to complete, in case the cable | |
640 | * was just plugged in. The autoneg_failed flag does this. | |
641 | */ | |
642 | /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ | |
643 | if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && | |
644 | !(rxcw & E1000_RXCW_C)) { | |
645 | if (!mac->autoneg_failed) { | |
646 | mac->autoneg_failed = true; | |
647 | return E1000_SUCCESS; | |
648 | } | |
649 | DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); | |
650 | ||
651 | /* Disable auto-negotiation in the TXCW register */ | |
652 | E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); | |
653 | ||
654 | /* Force link-up and also force full-duplex. */ | |
655 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
656 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
657 | E1000_WRITE_REG(hw, E1000_CTRL, ctrl); | |
658 | ||
659 | /* Configure Flow Control after forcing link up. */ | |
660 | ret_val = e1000_config_fc_after_link_up_generic(hw); | |
661 | if (ret_val) { | |
662 | DEBUGOUT("Error configuring flow control\n"); | |
663 | return ret_val; | |
664 | } | |
665 | } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
666 | /* If we are forcing link and we are receiving /C/ ordered | |
667 | * sets, re-enable auto-negotiation in the TXCW register | |
668 | * and disable forced link in the Device Control register | |
669 | * in an attempt to auto-negotiate with our link partner. | |
670 | */ | |
671 | DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); | |
672 | E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); | |
673 | E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
674 | ||
675 | mac->serdes_has_link = true; | |
676 | } | |
677 | ||
678 | return E1000_SUCCESS; | |
679 | } | |
680 | ||
681 | /** | |
682 | * e1000_check_for_serdes_link_generic - Check for link (Serdes) | |
683 | * @hw: pointer to the HW structure | |
684 | * | |
685 | * Checks for link up on the hardware. If link is not up and we have | |
686 | * a signal, then we need to force link up. | |
687 | **/ | |
688 | s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) | |
689 | { | |
690 | struct e1000_mac_info *mac = &hw->mac; | |
691 | u32 rxcw; | |
692 | u32 ctrl; | |
693 | u32 status; | |
694 | s32 ret_val; | |
695 | ||
696 | DEBUGFUNC("e1000_check_for_serdes_link_generic"); | |
697 | ||
698 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
699 | status = E1000_READ_REG(hw, E1000_STATUS); | |
700 | rxcw = E1000_READ_REG(hw, E1000_RXCW); | |
701 | ||
702 | /* If we don't have link (auto-negotiation failed or link partner | |
703 | * cannot auto-negotiate), and our link partner is not trying to | |
704 | * auto-negotiate with us (we are receiving idles or data), | |
705 | * we need to force link up. We also need to give auto-negotiation | |
706 | * time to complete. | |
707 | */ | |
708 | /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ | |
709 | if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { | |
710 | if (!mac->autoneg_failed) { | |
711 | mac->autoneg_failed = true; | |
712 | return E1000_SUCCESS; | |
713 | } | |
714 | DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); | |
715 | ||
716 | /* Disable auto-negotiation in the TXCW register */ | |
717 | E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); | |
718 | ||
719 | /* Force link-up and also force full-duplex. */ | |
720 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
721 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
722 | E1000_WRITE_REG(hw, E1000_CTRL, ctrl); | |
723 | ||
724 | /* Configure Flow Control after forcing link up. */ | |
725 | ret_val = e1000_config_fc_after_link_up_generic(hw); | |
726 | if (ret_val) { | |
727 | DEBUGOUT("Error configuring flow control\n"); | |
728 | return ret_val; | |
729 | } | |
730 | } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
731 | /* If we are forcing link and we are receiving /C/ ordered | |
732 | * sets, re-enable auto-negotiation in the TXCW register | |
733 | * and disable forced link in the Device Control register | |
734 | * in an attempt to auto-negotiate with our link partner. | |
735 | */ | |
736 | DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); | |
737 | E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); | |
738 | E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
739 | ||
740 | mac->serdes_has_link = true; | |
741 | } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { | |
742 | /* If we force link for non-auto-negotiation switch, check | |
743 | * link status based on MAC synchronization for internal | |
744 | * serdes media type. | |
745 | */ | |
746 | /* SYNCH bit and IV bit are sticky. */ | |
747 | usec_delay(10); | |
748 | rxcw = E1000_READ_REG(hw, E1000_RXCW); | |
749 | if (rxcw & E1000_RXCW_SYNCH) { | |
750 | if (!(rxcw & E1000_RXCW_IV)) { | |
751 | mac->serdes_has_link = true; | |
752 | DEBUGOUT("SERDES: Link up - forced.\n"); | |
753 | } | |
754 | } else { | |
755 | mac->serdes_has_link = false; | |
756 | DEBUGOUT("SERDES: Link down - force failed.\n"); | |
757 | } | |
758 | } | |
759 | ||
760 | if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { | |
761 | status = E1000_READ_REG(hw, E1000_STATUS); | |
762 | if (status & E1000_STATUS_LU) { | |
763 | /* SYNCH bit and IV bit are sticky, so reread rxcw. */ | |
764 | usec_delay(10); | |
765 | rxcw = E1000_READ_REG(hw, E1000_RXCW); | |
766 | if (rxcw & E1000_RXCW_SYNCH) { | |
767 | if (!(rxcw & E1000_RXCW_IV)) { | |
768 | mac->serdes_has_link = true; | |
769 | DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); | |
770 | } else { | |
771 | mac->serdes_has_link = false; | |
772 | DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); | |
773 | } | |
774 | } else { | |
775 | mac->serdes_has_link = false; | |
776 | DEBUGOUT("SERDES: Link down - no sync.\n"); | |
777 | } | |
778 | } else { | |
779 | mac->serdes_has_link = false; | |
780 | DEBUGOUT("SERDES: Link down - autoneg failed\n"); | |
781 | } | |
782 | } | |
783 | ||
784 | return E1000_SUCCESS; | |
785 | } | |
786 | ||
787 | /** | |
788 | * e1000_set_default_fc_generic - Set flow control default values | |
789 | * @hw: pointer to the HW structure | |
790 | * | |
791 | * Read the EEPROM for the default values for flow control and store the | |
792 | * values. | |
793 | **/ | |
794 | static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) | |
795 | { | |
796 | s32 ret_val; | |
797 | u16 nvm_data; | |
798 | ||
799 | DEBUGFUNC("e1000_set_default_fc_generic"); | |
800 | ||
801 | /* Read and store word 0x0F of the EEPROM. This word contains bits | |
802 | * that determine the hardware's default PAUSE (flow control) mode, | |
803 | * a bit that determines whether the HW defaults to enabling or | |
804 | * disabling auto-negotiation, and the direction of the | |
805 | * SW defined pins. If there is no SW over-ride of the flow | |
806 | * control setting, then the variable hw->fc will | |
807 | * be initialized based on a value in the EEPROM. | |
808 | */ | |
809 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); | |
810 | ||
811 | if (ret_val) { | |
812 | DEBUGOUT("NVM Read Error\n"); | |
813 | return ret_val; | |
814 | } | |
815 | ||
816 | if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) | |
817 | hw->fc.requested_mode = e1000_fc_none; | |
818 | else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == | |
819 | NVM_WORD0F_ASM_DIR) | |
820 | hw->fc.requested_mode = e1000_fc_tx_pause; | |
821 | else | |
822 | hw->fc.requested_mode = e1000_fc_full; | |
823 | ||
824 | return E1000_SUCCESS; | |
825 | } | |
826 | ||
827 | /** | |
828 | * e1000_setup_link_generic - Setup flow control and link settings | |
829 | * @hw: pointer to the HW structure | |
830 | * | |
831 | * Determines which flow control settings to use, then configures flow | |
832 | * control. Calls the appropriate media-specific link configuration | |
833 | * function. Assuming the adapter has a valid link partner, a valid link | |
834 | * should be established. Assumes the hardware has previously been reset | |
835 | * and the transmitter and receiver are not enabled. | |
836 | **/ | |
837 | s32 e1000_setup_link_generic(struct e1000_hw *hw) | |
838 | { | |
839 | s32 ret_val; | |
840 | ||
841 | DEBUGFUNC("e1000_setup_link_generic"); | |
842 | ||
843 | /* In the case of the phy reset being blocked, we already have a link. | |
844 | * We do not need to set it up again. | |
845 | */ | |
846 | if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) | |
847 | return E1000_SUCCESS; | |
848 | ||
849 | /* If requested flow control is set to default, set flow control | |
850 | * based on the EEPROM flow control settings. | |
851 | */ | |
852 | if (hw->fc.requested_mode == e1000_fc_default) { | |
853 | ret_val = e1000_set_default_fc_generic(hw); | |
854 | if (ret_val) | |
855 | return ret_val; | |
856 | } | |
857 | ||
858 | /* Save off the requested flow control mode for use later. Depending | |
859 | * on the link partner's capabilities, we may or may not use this mode. | |
860 | */ | |
861 | hw->fc.current_mode = hw->fc.requested_mode; | |
862 | ||
863 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", | |
864 | hw->fc.current_mode); | |
865 | ||
866 | /* Call the necessary media_type subroutine to configure the link. */ | |
867 | ret_val = hw->mac.ops.setup_physical_interface(hw); | |
868 | if (ret_val) | |
869 | return ret_val; | |
870 | ||
871 | /* Initialize the flow control address, type, and PAUSE timer | |
872 | * registers to their default values. This is done even if flow | |
873 | * control is disabled, because it does not hurt anything to | |
874 | * initialize these registers. | |
875 | */ | |
876 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); | |
877 | E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); | |
878 | E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
879 | E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
880 | ||
881 | E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); | |
882 | ||
883 | return e1000_set_fc_watermarks_generic(hw); | |
884 | } | |
885 | ||
886 | /** | |
887 | * e1000_commit_fc_settings_generic - Configure flow control | |
888 | * @hw: pointer to the HW structure | |
889 | * | |
890 | * Write the flow control settings to the Transmit Config Word Register (TXCW) | |
891 | * base on the flow control settings in e1000_mac_info. | |
892 | **/ | |
893 | static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) | |
894 | { | |
895 | struct e1000_mac_info *mac = &hw->mac; | |
896 | u32 txcw; | |
897 | ||
898 | DEBUGFUNC("e1000_commit_fc_settings_generic"); | |
899 | ||
900 | /* Check for a software override of the flow control settings, and | |
901 | * setup the device accordingly. If auto-negotiation is enabled, then | |
902 | * software will have to set the "PAUSE" bits to the correct value in | |
903 | * the Transmit Config Word Register (TXCW) and re-start auto- | |
904 | * negotiation. However, if auto-negotiation is disabled, then | |
905 | * software will have to manually configure the two flow control enable | |
906 | * bits in the CTRL register. | |
907 | * | |
908 | * The possible values of the "fc" parameter are: | |
909 | * 0: Flow control is completely disabled | |
910 | * 1: Rx flow control is enabled (we can receive pause frames, | |
911 | * but not send pause frames). | |
912 | * 2: Tx flow control is enabled (we can send pause frames but we | |
913 | * do not support receiving pause frames). | |
914 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | |
915 | */ | |
916 | switch (hw->fc.current_mode) { | |
917 | case e1000_fc_none: | |
918 | /* Flow control completely disabled by a software over-ride. */ | |
919 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | |
920 | break; | |
921 | case e1000_fc_rx_pause: | |
922 | /* Rx Flow control is enabled and Tx Flow control is disabled | |
923 | * by a software over-ride. Since there really isn't a way to | |
924 | * advertise that we are capable of Rx Pause ONLY, we will | |
925 | * advertise that we support both symmetric and asymmetric Rx | |
926 | * PAUSE. Later, we will disable the adapter's ability to send | |
927 | * PAUSE frames. | |
928 | */ | |
929 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
930 | break; | |
931 | case e1000_fc_tx_pause: | |
932 | /* Tx Flow control is enabled, and Rx Flow control is disabled, | |
933 | * by a software over-ride. | |
934 | */ | |
935 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | |
936 | break; | |
937 | case e1000_fc_full: | |
938 | /* Flow control (both Rx and Tx) is enabled by a software | |
939 | * over-ride. | |
940 | */ | |
941 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
942 | break; | |
943 | default: | |
944 | DEBUGOUT("Flow control param set incorrectly\n"); | |
945 | return -E1000_ERR_CONFIG; | |
946 | break; | |
947 | } | |
948 | ||
949 | E1000_WRITE_REG(hw, E1000_TXCW, txcw); | |
950 | mac->txcw = txcw; | |
951 | ||
952 | return E1000_SUCCESS; | |
953 | } | |
954 | ||
955 | /** | |
956 | * e1000_poll_fiber_serdes_link_generic - Poll for link up | |
957 | * @hw: pointer to the HW structure | |
958 | * | |
959 | * Polls for link up by reading the status register, if link fails to come | |
960 | * up with auto-negotiation, then the link is forced if a signal is detected. | |
961 | **/ | |
962 | static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) | |
963 | { | |
964 | struct e1000_mac_info *mac = &hw->mac; | |
965 | u32 i, status; | |
966 | s32 ret_val; | |
967 | ||
968 | DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); | |
969 | ||
970 | /* If we have a signal (the cable is plugged in, or assumed true for | |
971 | * serdes media) then poll for a "Link-Up" indication in the Device | |
972 | * Status Register. Time-out if a link isn't seen in 500 milliseconds | |
973 | * seconds (Auto-negotiation should complete in less than 500 | |
974 | * milliseconds even if the other end is doing it in SW). | |
975 | */ | |
976 | for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { | |
977 | msec_delay(10); | |
978 | status = E1000_READ_REG(hw, E1000_STATUS); | |
979 | if (status & E1000_STATUS_LU) | |
980 | break; | |
981 | } | |
982 | if (i == FIBER_LINK_UP_LIMIT) { | |
983 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); | |
984 | mac->autoneg_failed = true; | |
985 | /* AutoNeg failed to achieve a link, so we'll call | |
986 | * mac->check_for_link. This routine will force the | |
987 | * link up if we detect a signal. This will allow us to | |
988 | * communicate with non-autonegotiating link partners. | |
989 | */ | |
990 | ret_val = mac->ops.check_for_link(hw); | |
991 | if (ret_val) { | |
992 | DEBUGOUT("Error while checking for link\n"); | |
993 | return ret_val; | |
994 | } | |
995 | mac->autoneg_failed = false; | |
996 | } else { | |
997 | mac->autoneg_failed = false; | |
998 | DEBUGOUT("Valid Link Found\n"); | |
999 | } | |
1000 | ||
1001 | return E1000_SUCCESS; | |
1002 | } | |
1003 | ||
1004 | /** | |
1005 | * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes | |
1006 | * @hw: pointer to the HW structure | |
1007 | * | |
1008 | * Configures collision distance and flow control for fiber and serdes | |
1009 | * links. Upon successful setup, poll for link. | |
1010 | **/ | |
1011 | s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) | |
1012 | { | |
1013 | u32 ctrl; | |
1014 | s32 ret_val; | |
1015 | ||
1016 | DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); | |
1017 | ||
1018 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
1019 | ||
1020 | /* Take the link out of reset */ | |
1021 | ctrl &= ~E1000_CTRL_LRST; | |
1022 | ||
1023 | hw->mac.ops.config_collision_dist(hw); | |
1024 | ||
1025 | ret_val = e1000_commit_fc_settings_generic(hw); | |
1026 | if (ret_val) | |
1027 | return ret_val; | |
1028 | ||
1029 | /* Since auto-negotiation is enabled, take the link out of reset (the | |
1030 | * link will be in reset, because we previously reset the chip). This | |
1031 | * will restart auto-negotiation. If auto-negotiation is successful | |
1032 | * then the link-up status bit will be set and the flow control enable | |
1033 | * bits (RFCE and TFCE) will be set according to their negotiated value. | |
1034 | */ | |
1035 | DEBUGOUT("Auto-negotiation enabled\n"); | |
1036 | ||
1037 | E1000_WRITE_REG(hw, E1000_CTRL, ctrl); | |
1038 | E1000_WRITE_FLUSH(hw); | |
1039 | msec_delay(1); | |
1040 | ||
1041 | /* For these adapters, the SW definable pin 1 is set when the optics | |
1042 | * detect a signal. If we have a signal, then poll for a "Link-Up" | |
1043 | * indication. | |
1044 | */ | |
1045 | if (hw->phy.media_type == e1000_media_type_internal_serdes || | |
1046 | (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { | |
1047 | ret_val = e1000_poll_fiber_serdes_link_generic(hw); | |
1048 | } else { | |
1049 | DEBUGOUT("No signal detected\n"); | |
1050 | } | |
1051 | ||
1052 | return ret_val; | |
1053 | } | |
1054 | ||
1055 | /** | |
1056 | * e1000_config_collision_dist_generic - Configure collision distance | |
1057 | * @hw: pointer to the HW structure | |
1058 | * | |
1059 | * Configures the collision distance to the default value and is used | |
1060 | * during link setup. | |
1061 | **/ | |
1062 | static void e1000_config_collision_dist_generic(struct e1000_hw *hw) | |
1063 | { | |
1064 | u32 tctl; | |
1065 | ||
1066 | DEBUGFUNC("e1000_config_collision_dist_generic"); | |
1067 | ||
1068 | tctl = E1000_READ_REG(hw, E1000_TCTL); | |
1069 | ||
1070 | tctl &= ~E1000_TCTL_COLD; | |
1071 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; | |
1072 | ||
1073 | E1000_WRITE_REG(hw, E1000_TCTL, tctl); | |
1074 | E1000_WRITE_FLUSH(hw); | |
1075 | } | |
1076 | ||
1077 | /** | |
1078 | * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks | |
1079 | * @hw: pointer to the HW structure | |
1080 | * | |
1081 | * Sets the flow control high/low threshold (watermark) registers. If | |
1082 | * flow control XON frame transmission is enabled, then set XON frame | |
1083 | * transmission as well. | |
1084 | **/ | |
1085 | s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) | |
1086 | { | |
1087 | u32 fcrtl = 0, fcrth = 0; | |
1088 | ||
1089 | DEBUGFUNC("e1000_set_fc_watermarks_generic"); | |
1090 | ||
1091 | /* Set the flow control receive threshold registers. Normally, | |
1092 | * these registers will be set to a default threshold that may be | |
1093 | * adjusted later by the driver's runtime code. However, if the | |
1094 | * ability to transmit pause frames is not enabled, then these | |
1095 | * registers will be set to 0. | |
1096 | */ | |
1097 | if (hw->fc.current_mode & e1000_fc_tx_pause) { | |
1098 | /* We need to set up the Receive Threshold high and low water | |
1099 | * marks as well as (optionally) enabling the transmission of | |
1100 | * XON frames. | |
1101 | */ | |
1102 | fcrtl = hw->fc.low_water; | |
1103 | if (hw->fc.send_xon) | |
1104 | fcrtl |= E1000_FCRTL_XONE; | |
1105 | ||
1106 | fcrth = hw->fc.high_water; | |
1107 | } | |
1108 | E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); | |
1109 | E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); | |
1110 | ||
1111 | return E1000_SUCCESS; | |
1112 | } | |
1113 | ||
1114 | /** | |
1115 | * e1000_force_mac_fc_generic - Force the MAC's flow control settings | |
1116 | * @hw: pointer to the HW structure | |
1117 | * | |
1118 | * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the | |
1119 | * device control register to reflect the adapter settings. TFCE and RFCE | |
1120 | * need to be explicitly set by software when a copper PHY is used because | |
1121 | * autonegotiation is managed by the PHY rather than the MAC. Software must | |
1122 | * also configure these bits when link is forced on a fiber connection. | |
1123 | **/ | |
1124 | s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) | |
1125 | { | |
1126 | u32 ctrl; | |
1127 | ||
1128 | DEBUGFUNC("e1000_force_mac_fc_generic"); | |
1129 | ||
1130 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
1131 | ||
1132 | /* Because we didn't get link via the internal auto-negotiation | |
1133 | * mechanism (we either forced link or we got link via PHY | |
1134 | * auto-neg), we have to manually enable/disable transmit an | |
1135 | * receive flow control. | |
1136 | * | |
1137 | * The "Case" statement below enables/disable flow control | |
1138 | * according to the "hw->fc.current_mode" parameter. | |
1139 | * | |
1140 | * The possible values of the "fc" parameter are: | |
1141 | * 0: Flow control is completely disabled | |
1142 | * 1: Rx flow control is enabled (we can receive pause | |
1143 | * frames but not send pause frames). | |
1144 | * 2: Tx flow control is enabled (we can send pause frames | |
1145 | * frames but we do not receive pause frames). | |
1146 | * 3: Both Rx and Tx flow control (symmetric) is enabled. | |
1147 | * other: No other values should be possible at this point. | |
1148 | */ | |
1149 | DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); | |
1150 | ||
1151 | switch (hw->fc.current_mode) { | |
1152 | case e1000_fc_none: | |
1153 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); | |
1154 | break; | |
1155 | case e1000_fc_rx_pause: | |
1156 | ctrl &= (~E1000_CTRL_TFCE); | |
1157 | ctrl |= E1000_CTRL_RFCE; | |
1158 | break; | |
1159 | case e1000_fc_tx_pause: | |
1160 | ctrl &= (~E1000_CTRL_RFCE); | |
1161 | ctrl |= E1000_CTRL_TFCE; | |
1162 | break; | |
1163 | case e1000_fc_full: | |
1164 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); | |
1165 | break; | |
1166 | default: | |
1167 | DEBUGOUT("Flow control param set incorrectly\n"); | |
1168 | return -E1000_ERR_CONFIG; | |
1169 | } | |
1170 | ||
1171 | E1000_WRITE_REG(hw, E1000_CTRL, ctrl); | |
1172 | ||
1173 | return E1000_SUCCESS; | |
1174 | } | |
1175 | ||
1176 | /** | |
1177 | * e1000_config_fc_after_link_up_generic - Configures flow control after link | |
1178 | * @hw: pointer to the HW structure | |
1179 | * | |
1180 | * Checks the status of auto-negotiation after link up to ensure that the | |
1181 | * speed and duplex were not forced. If the link needed to be forced, then | |
1182 | * flow control needs to be forced also. If auto-negotiation is enabled | |
1183 | * and did not fail, then we configure flow control based on our link | |
1184 | * partner. | |
1185 | **/ | |
1186 | s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) | |
1187 | { | |
1188 | struct e1000_mac_info *mac = &hw->mac; | |
1189 | s32 ret_val = E1000_SUCCESS; | |
1190 | u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; | |
1191 | u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; | |
1192 | u16 speed, duplex; | |
1193 | ||
1194 | DEBUGFUNC("e1000_config_fc_after_link_up_generic"); | |
1195 | ||
1196 | /* Check for the case where we have fiber media and auto-neg failed | |
1197 | * so we had to force link. In this case, we need to force the | |
1198 | * configuration of the MAC to match the "fc" parameter. | |
1199 | */ | |
1200 | if (mac->autoneg_failed) { | |
1201 | if (hw->phy.media_type == e1000_media_type_fiber || | |
1202 | hw->phy.media_type == e1000_media_type_internal_serdes) | |
1203 | ret_val = e1000_force_mac_fc_generic(hw); | |
1204 | } else { | |
1205 | if (hw->phy.media_type == e1000_media_type_copper) | |
1206 | ret_val = e1000_force_mac_fc_generic(hw); | |
1207 | } | |
1208 | ||
1209 | if (ret_val) { | |
1210 | DEBUGOUT("Error forcing flow control settings\n"); | |
1211 | return ret_val; | |
1212 | } | |
1213 | ||
1214 | /* Check for the case where we have copper media and auto-neg is | |
1215 | * enabled. In this case, we need to check and see if Auto-Neg | |
1216 | * has completed, and if so, how the PHY and link partner has | |
1217 | * flow control configured. | |
1218 | */ | |
1219 | if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { | |
1220 | /* Read the MII Status Register and check to see if AutoNeg | |
1221 | * has completed. We read this twice because this reg has | |
1222 | * some "sticky" (latched) bits. | |
1223 | */ | |
1224 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); | |
1225 | if (ret_val) | |
1226 | return ret_val; | |
1227 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); | |
1228 | if (ret_val) | |
1229 | return ret_val; | |
1230 | ||
1231 | if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { | |
1232 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); | |
1233 | return ret_val; | |
1234 | } | |
1235 | ||
1236 | /* The AutoNeg process has completed, so we now need to | |
1237 | * read both the Auto Negotiation Advertisement | |
1238 | * Register (Address 4) and the Auto_Negotiation Base | |
1239 | * Page Ability Register (Address 5) to determine how | |
1240 | * flow control was negotiated. | |
1241 | */ | |
1242 | ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, | |
1243 | &mii_nway_adv_reg); | |
1244 | if (ret_val) | |
1245 | return ret_val; | |
1246 | ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, | |
1247 | &mii_nway_lp_ability_reg); | |
1248 | if (ret_val) | |
1249 | return ret_val; | |
1250 | ||
1251 | /* Two bits in the Auto Negotiation Advertisement Register | |
1252 | * (Address 4) and two bits in the Auto Negotiation Base | |
1253 | * Page Ability Register (Address 5) determine flow control | |
1254 | * for both the PHY and the link partner. The following | |
1255 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
1256 | * 1999, describes these PAUSE resolution bits and how flow | |
1257 | * control is determined based upon these settings. | |
1258 | * NOTE: DC = Don't Care | |
1259 | * | |
1260 | * LOCAL DEVICE | LINK PARTNER | |
1261 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
1262 | *-------|---------|-------|---------|-------------------- | |
1263 | * 0 | 0 | DC | DC | e1000_fc_none | |
1264 | * 0 | 1 | 0 | DC | e1000_fc_none | |
1265 | * 0 | 1 | 1 | 0 | e1000_fc_none | |
1266 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
1267 | * 1 | 0 | 0 | DC | e1000_fc_none | |
1268 | * 1 | DC | 1 | DC | e1000_fc_full | |
1269 | * 1 | 1 | 0 | 0 | e1000_fc_none | |
1270 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
1271 | * | |
1272 | * Are both PAUSE bits set to 1? If so, this implies | |
1273 | * Symmetric Flow Control is enabled at both ends. The | |
1274 | * ASM_DIR bits are irrelevant per the spec. | |
1275 | * | |
1276 | * For Symmetric Flow Control: | |
1277 | * | |
1278 | * LOCAL DEVICE | LINK PARTNER | |
1279 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
1280 | *-------|---------|-------|---------|-------------------- | |
1281 | * 1 | DC | 1 | DC | E1000_fc_full | |
1282 | * | |
1283 | */ | |
1284 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
1285 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
1286 | /* Now we need to check if the user selected Rx ONLY | |
1287 | * of pause frames. In this case, we had to advertise | |
1288 | * FULL flow control because we could not advertise Rx | |
1289 | * ONLY. Hence, we must now check to see if we need to | |
1290 | * turn OFF the TRANSMISSION of PAUSE frames. | |
1291 | */ | |
1292 | if (hw->fc.requested_mode == e1000_fc_full) { | |
1293 | hw->fc.current_mode = e1000_fc_full; | |
1294 | DEBUGOUT("Flow Control = FULL.\n"); | |
1295 | } else { | |
1296 | hw->fc.current_mode = e1000_fc_rx_pause; | |
1297 | DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); | |
1298 | } | |
1299 | } | |
1300 | /* For receiving PAUSE frames ONLY. | |
1301 | * | |
1302 | * LOCAL DEVICE | LINK PARTNER | |
1303 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
1304 | *-------|---------|-------|---------|-------------------- | |
1305 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
1306 | */ | |
1307 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
1308 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
1309 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
1310 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
1311 | hw->fc.current_mode = e1000_fc_tx_pause; | |
1312 | DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); | |
1313 | } | |
1314 | /* For transmitting PAUSE frames ONLY. | |
1315 | * | |
1316 | * LOCAL DEVICE | LINK PARTNER | |
1317 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
1318 | *-------|---------|-------|---------|-------------------- | |
1319 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
1320 | */ | |
1321 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
1322 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
1323 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
1324 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
1325 | hw->fc.current_mode = e1000_fc_rx_pause; | |
1326 | DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); | |
1327 | } else { | |
1328 | /* Per the IEEE spec, at this point flow control | |
1329 | * should be disabled. | |
1330 | */ | |
1331 | hw->fc.current_mode = e1000_fc_none; | |
1332 | DEBUGOUT("Flow Control = NONE.\n"); | |
1333 | } | |
1334 | ||
1335 | /* Now we need to do one last check... If we auto- | |
1336 | * negotiated to HALF DUPLEX, flow control should not be | |
1337 | * enabled per IEEE 802.3 spec. | |
1338 | */ | |
1339 | ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); | |
1340 | if (ret_val) { | |
1341 | DEBUGOUT("Error getting link speed and duplex\n"); | |
1342 | return ret_val; | |
1343 | } | |
1344 | ||
1345 | if (duplex == HALF_DUPLEX) | |
1346 | hw->fc.current_mode = e1000_fc_none; | |
1347 | ||
1348 | /* Now we call a subroutine to actually force the MAC | |
1349 | * controller to use the correct flow control settings. | |
1350 | */ | |
1351 | ret_val = e1000_force_mac_fc_generic(hw); | |
1352 | if (ret_val) { | |
1353 | DEBUGOUT("Error forcing flow control settings\n"); | |
1354 | return ret_val; | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | /* Check for the case where we have SerDes media and auto-neg is | |
1359 | * enabled. In this case, we need to check and see if Auto-Neg | |
1360 | * has completed, and if so, how the PHY and link partner has | |
1361 | * flow control configured. | |
1362 | */ | |
1363 | if ((hw->phy.media_type == e1000_media_type_internal_serdes) && | |
1364 | mac->autoneg) { | |
1365 | /* Read the PCS_LSTS and check to see if AutoNeg | |
1366 | * has completed. | |
1367 | */ | |
1368 | pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); | |
1369 | ||
1370 | if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { | |
1371 | DEBUGOUT("PCS Auto Neg has not completed.\n"); | |
1372 | return ret_val; | |
1373 | } | |
1374 | ||
1375 | /* The AutoNeg process has completed, so we now need to | |
1376 | * read both the Auto Negotiation Advertisement | |
1377 | * Register (PCS_ANADV) and the Auto_Negotiation Base | |
1378 | * Page Ability Register (PCS_LPAB) to determine how | |
1379 | * flow control was negotiated. | |
1380 | */ | |
1381 | pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); | |
1382 | pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); | |
1383 | ||
1384 | /* Two bits in the Auto Negotiation Advertisement Register | |
1385 | * (PCS_ANADV) and two bits in the Auto Negotiation Base | |
1386 | * Page Ability Register (PCS_LPAB) determine flow control | |
1387 | * for both the PHY and the link partner. The following | |
1388 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
1389 | * 1999, describes these PAUSE resolution bits and how flow | |
1390 | * control is determined based upon these settings. | |
1391 | * NOTE: DC = Don't Care | |
1392 | * | |
1393 | * LOCAL DEVICE | LINK PARTNER | |
1394 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
1395 | *-------|---------|-------|---------|-------------------- | |
1396 | * 0 | 0 | DC | DC | e1000_fc_none | |
1397 | * 0 | 1 | 0 | DC | e1000_fc_none | |
1398 | * 0 | 1 | 1 | 0 | e1000_fc_none | |
1399 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
1400 | * 1 | 0 | 0 | DC | e1000_fc_none | |
1401 | * 1 | DC | 1 | DC | e1000_fc_full | |
1402 | * 1 | 1 | 0 | 0 | e1000_fc_none | |
1403 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
1404 | * | |
1405 | * Are both PAUSE bits set to 1? If so, this implies | |
1406 | * Symmetric Flow Control is enabled at both ends. The | |
1407 | * ASM_DIR bits are irrelevant per the spec. | |
1408 | * | |
1409 | * For Symmetric Flow Control: | |
1410 | * | |
1411 | * LOCAL DEVICE | LINK PARTNER | |
1412 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
1413 | *-------|---------|-------|---------|-------------------- | |
1414 | * 1 | DC | 1 | DC | e1000_fc_full | |
1415 | * | |
1416 | */ | |
1417 | if ((pcs_adv_reg & E1000_TXCW_PAUSE) && | |
1418 | (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { | |
1419 | /* Now we need to check if the user selected Rx ONLY | |
1420 | * of pause frames. In this case, we had to advertise | |
1421 | * FULL flow control because we could not advertise Rx | |
1422 | * ONLY. Hence, we must now check to see if we need to | |
1423 | * turn OFF the TRANSMISSION of PAUSE frames. | |
1424 | */ | |
1425 | if (hw->fc.requested_mode == e1000_fc_full) { | |
1426 | hw->fc.current_mode = e1000_fc_full; | |
1427 | DEBUGOUT("Flow Control = FULL.\n"); | |
1428 | } else { | |
1429 | hw->fc.current_mode = e1000_fc_rx_pause; | |
1430 | DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); | |
1431 | } | |
1432 | } | |
1433 | /* For receiving PAUSE frames ONLY. | |
1434 | * | |
1435 | * LOCAL DEVICE | LINK PARTNER | |
1436 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
1437 | *-------|---------|-------|---------|-------------------- | |
1438 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
1439 | */ | |
1440 | else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && | |
1441 | (pcs_adv_reg & E1000_TXCW_ASM_DIR) && | |
1442 | (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && | |
1443 | (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { | |
1444 | hw->fc.current_mode = e1000_fc_tx_pause; | |
1445 | DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); | |
1446 | } | |
1447 | /* For transmitting PAUSE frames ONLY. | |
1448 | * | |
1449 | * LOCAL DEVICE | LINK PARTNER | |
1450 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
1451 | *-------|---------|-------|---------|-------------------- | |
1452 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
1453 | */ | |
1454 | else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && | |
1455 | (pcs_adv_reg & E1000_TXCW_ASM_DIR) && | |
1456 | !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && | |
1457 | (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { | |
1458 | hw->fc.current_mode = e1000_fc_rx_pause; | |
1459 | DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); | |
1460 | } else { | |
1461 | /* Per the IEEE spec, at this point flow control | |
1462 | * should be disabled. | |
1463 | */ | |
1464 | hw->fc.current_mode = e1000_fc_none; | |
1465 | DEBUGOUT("Flow Control = NONE.\n"); | |
1466 | } | |
1467 | ||
1468 | /* Now we call a subroutine to actually force the MAC | |
1469 | * controller to use the correct flow control settings. | |
1470 | */ | |
1471 | pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); | |
1472 | pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1473 | E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); | |
1474 | ||
1475 | ret_val = e1000_force_mac_fc_generic(hw); | |
1476 | if (ret_val) { | |
1477 | DEBUGOUT("Error forcing flow control settings\n"); | |
1478 | return ret_val; | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | return E1000_SUCCESS; | |
1483 | } | |
1484 | ||
1485 | /** | |
1486 | * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex | |
1487 | * @hw: pointer to the HW structure | |
1488 | * @speed: stores the current speed | |
1489 | * @duplex: stores the current duplex | |
1490 | * | |
1491 | * Read the status register for the current speed/duplex and store the current | |
1492 | * speed and duplex for copper connections. | |
1493 | **/ | |
1494 | s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, | |
1495 | u16 *duplex) | |
1496 | { | |
1497 | u32 status; | |
1498 | ||
1499 | DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); | |
1500 | ||
1501 | status = E1000_READ_REG(hw, E1000_STATUS); | |
1502 | if (status & E1000_STATUS_SPEED_1000) { | |
1503 | *speed = SPEED_1000; | |
1504 | DEBUGOUT("1000 Mbs, "); | |
1505 | } else if (status & E1000_STATUS_SPEED_100) { | |
1506 | *speed = SPEED_100; | |
1507 | DEBUGOUT("100 Mbs, "); | |
1508 | } else { | |
1509 | *speed = SPEED_10; | |
1510 | DEBUGOUT("10 Mbs, "); | |
1511 | } | |
1512 | ||
1513 | if (status & E1000_STATUS_FD) { | |
1514 | *duplex = FULL_DUPLEX; | |
1515 | DEBUGOUT("Full Duplex\n"); | |
1516 | } else { | |
1517 | *duplex = HALF_DUPLEX; | |
1518 | DEBUGOUT("Half Duplex\n"); | |
1519 | } | |
1520 | ||
1521 | return E1000_SUCCESS; | |
1522 | } | |
1523 | ||
1524 | /** | |
1525 | * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex | |
1526 | * @hw: pointer to the HW structure | |
1527 | * @speed: stores the current speed | |
1528 | * @duplex: stores the current duplex | |
1529 | * | |
1530 | * Sets the speed and duplex to gigabit full duplex (the only possible option) | |
1531 | * for fiber/serdes links. | |
1532 | **/ | |
1533 | s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, | |
1534 | u16 *speed, u16 *duplex) | |
1535 | { | |
1536 | DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); | |
1537 | ||
1538 | *speed = SPEED_1000; | |
1539 | *duplex = FULL_DUPLEX; | |
1540 | ||
1541 | return E1000_SUCCESS; | |
1542 | } | |
1543 | ||
1544 | /** | |
1545 | * e1000_get_hw_semaphore_generic - Acquire hardware semaphore | |
1546 | * @hw: pointer to the HW structure | |
1547 | * | |
1548 | * Acquire the HW semaphore to access the PHY or NVM | |
1549 | **/ | |
1550 | s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) | |
1551 | { | |
1552 | u32 swsm; | |
1553 | s32 timeout = hw->nvm.word_size + 1; | |
1554 | s32 i = 0; | |
1555 | ||
1556 | DEBUGFUNC("e1000_get_hw_semaphore_generic"); | |
1557 | ||
1558 | /* Get the SW semaphore */ | |
1559 | while (i < timeout) { | |
1560 | swsm = E1000_READ_REG(hw, E1000_SWSM); | |
1561 | if (!(swsm & E1000_SWSM_SMBI)) | |
1562 | break; | |
1563 | ||
1564 | usec_delay(50); | |
1565 | i++; | |
1566 | } | |
1567 | ||
1568 | if (i == timeout) { | |
1569 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); | |
1570 | return -E1000_ERR_NVM; | |
1571 | } | |
1572 | ||
1573 | /* Get the FW semaphore. */ | |
1574 | for (i = 0; i < timeout; i++) { | |
1575 | swsm = E1000_READ_REG(hw, E1000_SWSM); | |
1576 | E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); | |
1577 | ||
1578 | /* Semaphore acquired if bit latched */ | |
1579 | if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) | |
1580 | break; | |
1581 | ||
1582 | usec_delay(50); | |
1583 | } | |
1584 | ||
1585 | if (i == timeout) { | |
1586 | /* Release semaphores */ | |
1587 | e1000_put_hw_semaphore_generic(hw); | |
1588 | DEBUGOUT("Driver can't access the NVM\n"); | |
1589 | return -E1000_ERR_NVM; | |
1590 | } | |
1591 | ||
1592 | return E1000_SUCCESS; | |
1593 | } | |
1594 | ||
1595 | /** | |
1596 | * e1000_put_hw_semaphore_generic - Release hardware semaphore | |
1597 | * @hw: pointer to the HW structure | |
1598 | * | |
1599 | * Release hardware semaphore used to access the PHY or NVM | |
1600 | **/ | |
1601 | void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) | |
1602 | { | |
1603 | u32 swsm; | |
1604 | ||
1605 | DEBUGFUNC("e1000_put_hw_semaphore_generic"); | |
1606 | ||
1607 | swsm = E1000_READ_REG(hw, E1000_SWSM); | |
1608 | ||
1609 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | |
1610 | ||
1611 | E1000_WRITE_REG(hw, E1000_SWSM, swsm); | |
1612 | } | |
1613 | ||
1614 | /** | |
1615 | * e1000_get_auto_rd_done_generic - Check for auto read completion | |
1616 | * @hw: pointer to the HW structure | |
1617 | * | |
1618 | * Check EEPROM for Auto Read done bit. | |
1619 | **/ | |
1620 | s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) | |
1621 | { | |
1622 | s32 i = 0; | |
1623 | ||
1624 | DEBUGFUNC("e1000_get_auto_rd_done_generic"); | |
1625 | ||
1626 | while (i < AUTO_READ_DONE_TIMEOUT) { | |
1627 | if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) | |
1628 | break; | |
1629 | msec_delay(1); | |
1630 | i++; | |
1631 | } | |
1632 | ||
1633 | if (i == AUTO_READ_DONE_TIMEOUT) { | |
1634 | DEBUGOUT("Auto read by HW from NVM has not completed.\n"); | |
1635 | return -E1000_ERR_RESET; | |
1636 | } | |
1637 | ||
1638 | return E1000_SUCCESS; | |
1639 | } | |
1640 | ||
1641 | /** | |
1642 | * e1000_valid_led_default_generic - Verify a valid default LED config | |
1643 | * @hw: pointer to the HW structure | |
1644 | * @data: pointer to the NVM (EEPROM) | |
1645 | * | |
1646 | * Read the EEPROM for the current default LED configuration. If the | |
1647 | * LED configuration is not valid, set to a valid LED configuration. | |
1648 | **/ | |
1649 | s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) | |
1650 | { | |
1651 | s32 ret_val; | |
1652 | ||
1653 | DEBUGFUNC("e1000_valid_led_default_generic"); | |
1654 | ||
1655 | ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1656 | if (ret_val) { | |
1657 | DEBUGOUT("NVM Read Error\n"); | |
1658 | return ret_val; | |
1659 | } | |
1660 | ||
1661 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) | |
1662 | *data = ID_LED_DEFAULT; | |
1663 | ||
1664 | return E1000_SUCCESS; | |
1665 | } | |
1666 | ||
1667 | /** | |
1668 | * e1000_id_led_init_generic - | |
1669 | * @hw: pointer to the HW structure | |
1670 | * | |
1671 | **/ | |
1672 | s32 e1000_id_led_init_generic(struct e1000_hw *hw) | |
1673 | { | |
1674 | struct e1000_mac_info *mac = &hw->mac; | |
1675 | s32 ret_val; | |
1676 | const u32 ledctl_mask = 0x000000FF; | |
1677 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; | |
1678 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; | |
1679 | u16 data, i, temp; | |
1680 | const u16 led_mask = 0x0F; | |
1681 | ||
1682 | DEBUGFUNC("e1000_id_led_init_generic"); | |
1683 | ||
1684 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); | |
1685 | if (ret_val) | |
1686 | return ret_val; | |
1687 | ||
1688 | mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); | |
1689 | mac->ledctl_mode1 = mac->ledctl_default; | |
1690 | mac->ledctl_mode2 = mac->ledctl_default; | |
1691 | ||
1692 | for (i = 0; i < 4; i++) { | |
1693 | temp = (data >> (i << 2)) & led_mask; | |
1694 | switch (temp) { | |
1695 | case ID_LED_ON1_DEF2: | |
1696 | case ID_LED_ON1_ON2: | |
1697 | case ID_LED_ON1_OFF2: | |
1698 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
1699 | mac->ledctl_mode1 |= ledctl_on << (i << 3); | |
1700 | break; | |
1701 | case ID_LED_OFF1_DEF2: | |
1702 | case ID_LED_OFF1_ON2: | |
1703 | case ID_LED_OFF1_OFF2: | |
1704 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
1705 | mac->ledctl_mode1 |= ledctl_off << (i << 3); | |
1706 | break; | |
1707 | default: | |
1708 | /* Do nothing */ | |
1709 | break; | |
1710 | } | |
1711 | switch (temp) { | |
1712 | case ID_LED_DEF1_ON2: | |
1713 | case ID_LED_ON1_ON2: | |
1714 | case ID_LED_OFF1_ON2: | |
1715 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
1716 | mac->ledctl_mode2 |= ledctl_on << (i << 3); | |
1717 | break; | |
1718 | case ID_LED_DEF1_OFF2: | |
1719 | case ID_LED_ON1_OFF2: | |
1720 | case ID_LED_OFF1_OFF2: | |
1721 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
1722 | mac->ledctl_mode2 |= ledctl_off << (i << 3); | |
1723 | break; | |
1724 | default: | |
1725 | /* Do nothing */ | |
1726 | break; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | return E1000_SUCCESS; | |
1731 | } | |
1732 | ||
1733 | /** | |
1734 | * e1000_setup_led_generic - Configures SW controllable LED | |
1735 | * @hw: pointer to the HW structure | |
1736 | * | |
1737 | * This prepares the SW controllable LED for use and saves the current state | |
1738 | * of the LED so it can be later restored. | |
1739 | **/ | |
1740 | s32 e1000_setup_led_generic(struct e1000_hw *hw) | |
1741 | { | |
1742 | u32 ledctl; | |
1743 | ||
1744 | DEBUGFUNC("e1000_setup_led_generic"); | |
1745 | ||
1746 | if (hw->mac.ops.setup_led != e1000_setup_led_generic) | |
1747 | return -E1000_ERR_CONFIG; | |
1748 | ||
1749 | if (hw->phy.media_type == e1000_media_type_fiber) { | |
1750 | ledctl = E1000_READ_REG(hw, E1000_LEDCTL); | |
1751 | hw->mac.ledctl_default = ledctl; | |
1752 | /* Turn off LED0 */ | |
1753 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | | |
1754 | E1000_LEDCTL_LED0_MODE_MASK); | |
1755 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << | |
1756 | E1000_LEDCTL_LED0_MODE_SHIFT); | |
1757 | E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); | |
1758 | } else if (hw->phy.media_type == e1000_media_type_copper) { | |
1759 | E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); | |
1760 | } | |
1761 | ||
1762 | return E1000_SUCCESS; | |
1763 | } | |
1764 | ||
1765 | /** | |
1766 | * e1000_cleanup_led_generic - Set LED config to default operation | |
1767 | * @hw: pointer to the HW structure | |
1768 | * | |
1769 | * Remove the current LED configuration and set the LED configuration | |
1770 | * to the default value, saved from the EEPROM. | |
1771 | **/ | |
1772 | s32 e1000_cleanup_led_generic(struct e1000_hw *hw) | |
1773 | { | |
1774 | DEBUGFUNC("e1000_cleanup_led_generic"); | |
1775 | ||
1776 | E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); | |
1777 | return E1000_SUCCESS; | |
1778 | } | |
1779 | ||
1780 | /** | |
1781 | * e1000_blink_led_generic - Blink LED | |
1782 | * @hw: pointer to the HW structure | |
1783 | * | |
1784 | * Blink the LEDs which are set to be on. | |
1785 | **/ | |
1786 | s32 e1000_blink_led_generic(struct e1000_hw *hw) | |
1787 | { | |
1788 | u32 ledctl_blink = 0; | |
1789 | u32 i; | |
1790 | ||
1791 | DEBUGFUNC("e1000_blink_led_generic"); | |
1792 | ||
1793 | if (hw->phy.media_type == e1000_media_type_fiber) { | |
1794 | /* always blink LED0 for PCI-E fiber */ | |
1795 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | | |
1796 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); | |
1797 | } else { | |
1798 | /* Set the blink bit for each LED that's "on" (0x0E) | |
1799 | * (or "off" if inverted) in ledctl_mode2. The blink | |
1800 | * logic in hardware only works when mode is set to "on" | |
1801 | * so it must be changed accordingly when the mode is | |
1802 | * "off" and inverted. | |
1803 | */ | |
1804 | ledctl_blink = hw->mac.ledctl_mode2; | |
1805 | for (i = 0; i < 32; i += 8) { | |
1806 | u32 mode = (hw->mac.ledctl_mode2 >> i) & | |
1807 | E1000_LEDCTL_LED0_MODE_MASK; | |
1808 | u32 led_default = hw->mac.ledctl_default >> i; | |
1809 | ||
1810 | if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && | |
1811 | (mode == E1000_LEDCTL_MODE_LED_ON)) || | |
1812 | ((led_default & E1000_LEDCTL_LED0_IVRT) && | |
1813 | (mode == E1000_LEDCTL_MODE_LED_OFF))) { | |
1814 | ledctl_blink &= | |
1815 | ~(E1000_LEDCTL_LED0_MODE_MASK << i); | |
1816 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | | |
1817 | E1000_LEDCTL_MODE_LED_ON) << i; | |
1818 | } | |
1819 | } | |
1820 | } | |
1821 | ||
1822 | E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); | |
1823 | ||
1824 | return E1000_SUCCESS; | |
1825 | } | |
1826 | ||
1827 | /** | |
1828 | * e1000_led_on_generic - Turn LED on | |
1829 | * @hw: pointer to the HW structure | |
1830 | * | |
1831 | * Turn LED on. | |
1832 | **/ | |
1833 | s32 e1000_led_on_generic(struct e1000_hw *hw) | |
1834 | { | |
1835 | u32 ctrl; | |
1836 | ||
1837 | DEBUGFUNC("e1000_led_on_generic"); | |
1838 | ||
1839 | switch (hw->phy.media_type) { | |
1840 | case e1000_media_type_fiber: | |
1841 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
1842 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
1843 | ctrl |= E1000_CTRL_SWDPIO0; | |
1844 | E1000_WRITE_REG(hw, E1000_CTRL, ctrl); | |
1845 | break; | |
1846 | case e1000_media_type_copper: | |
1847 | E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); | |
1848 | break; | |
1849 | default: | |
1850 | break; | |
1851 | } | |
1852 | ||
1853 | return E1000_SUCCESS; | |
1854 | } | |
1855 | ||
1856 | /** | |
1857 | * e1000_led_off_generic - Turn LED off | |
1858 | * @hw: pointer to the HW structure | |
1859 | * | |
1860 | * Turn LED off. | |
1861 | **/ | |
1862 | s32 e1000_led_off_generic(struct e1000_hw *hw) | |
1863 | { | |
1864 | u32 ctrl; | |
1865 | ||
1866 | DEBUGFUNC("e1000_led_off_generic"); | |
1867 | ||
1868 | switch (hw->phy.media_type) { | |
1869 | case e1000_media_type_fiber: | |
1870 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
1871 | ctrl |= E1000_CTRL_SWDPIN0; | |
1872 | ctrl |= E1000_CTRL_SWDPIO0; | |
1873 | E1000_WRITE_REG(hw, E1000_CTRL, ctrl); | |
1874 | break; | |
1875 | case e1000_media_type_copper: | |
1876 | E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); | |
1877 | break; | |
1878 | default: | |
1879 | break; | |
1880 | } | |
1881 | ||
1882 | return E1000_SUCCESS; | |
1883 | } | |
1884 | ||
1885 | /** | |
1886 | * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities | |
1887 | * @hw: pointer to the HW structure | |
1888 | * @no_snoop: bitmap of snoop events | |
1889 | * | |
1890 | * Set the PCI-express register to snoop for events enabled in 'no_snoop'. | |
1891 | **/ | |
1892 | void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) | |
1893 | { | |
1894 | u32 gcr; | |
1895 | ||
1896 | DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); | |
1897 | ||
1898 | if (no_snoop) { | |
1899 | gcr = E1000_READ_REG(hw, E1000_GCR); | |
1900 | gcr &= ~(PCIE_NO_SNOOP_ALL); | |
1901 | gcr |= no_snoop; | |
1902 | E1000_WRITE_REG(hw, E1000_GCR, gcr); | |
1903 | } | |
1904 | } | |
1905 | ||
1906 | /** | |
1907 | * e1000_disable_pcie_master_generic - Disables PCI-express master access | |
1908 | * @hw: pointer to the HW structure | |
1909 | * | |
1910 | * Returns E1000_SUCCESS if successful, else returns -10 | |
1911 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused | |
1912 | * the master requests to be disabled. | |
1913 | * | |
1914 | * Disables PCI-Express master access and verifies there are no pending | |
1915 | * requests. | |
1916 | **/ | |
1917 | s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) | |
1918 | { | |
1919 | u32 ctrl; | |
1920 | s32 timeout = MASTER_DISABLE_TIMEOUT; | |
1921 | ||
1922 | DEBUGFUNC("e1000_disable_pcie_master_generic"); | |
1923 | ||
1924 | ctrl = E1000_READ_REG(hw, E1000_CTRL); | |
1925 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; | |
1926 | E1000_WRITE_REG(hw, E1000_CTRL, ctrl); | |
1927 | ||
1928 | while (timeout) { | |
1929 | if (!(E1000_READ_REG(hw, E1000_STATUS) & | |
1930 | E1000_STATUS_GIO_MASTER_ENABLE)) | |
1931 | break; | |
1932 | usec_delay(100); | |
1933 | timeout--; | |
1934 | } | |
1935 | ||
1936 | if (!timeout) { | |
1937 | DEBUGOUT("Master requests are pending.\n"); | |
1938 | return -E1000_ERR_MASTER_REQUESTS_PENDING; | |
1939 | } | |
1940 | ||
1941 | return E1000_SUCCESS; | |
1942 | } | |
1943 | ||
1944 | /** | |
1945 | * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing | |
1946 | * @hw: pointer to the HW structure | |
1947 | * | |
1948 | * Reset the Adaptive Interframe Spacing throttle to default values. | |
1949 | **/ | |
1950 | void e1000_reset_adaptive_generic(struct e1000_hw *hw) | |
1951 | { | |
1952 | struct e1000_mac_info *mac = &hw->mac; | |
1953 | ||
1954 | DEBUGFUNC("e1000_reset_adaptive_generic"); | |
1955 | ||
1956 | if (!mac->adaptive_ifs) { | |
1957 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
1958 | return; | |
1959 | } | |
1960 | ||
1961 | mac->current_ifs_val = 0; | |
1962 | mac->ifs_min_val = IFS_MIN; | |
1963 | mac->ifs_max_val = IFS_MAX; | |
1964 | mac->ifs_step_size = IFS_STEP; | |
1965 | mac->ifs_ratio = IFS_RATIO; | |
1966 | ||
1967 | mac->in_ifs_mode = false; | |
1968 | E1000_WRITE_REG(hw, E1000_AIT, 0); | |
1969 | } | |
1970 | ||
1971 | /** | |
1972 | * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing | |
1973 | * @hw: pointer to the HW structure | |
1974 | * | |
1975 | * Update the Adaptive Interframe Spacing Throttle value based on the | |
1976 | * time between transmitted packets and time between collisions. | |
1977 | **/ | |
1978 | void e1000_update_adaptive_generic(struct e1000_hw *hw) | |
1979 | { | |
1980 | struct e1000_mac_info *mac = &hw->mac; | |
1981 | ||
1982 | DEBUGFUNC("e1000_update_adaptive_generic"); | |
1983 | ||
1984 | if (!mac->adaptive_ifs) { | |
1985 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
1986 | return; | |
1987 | } | |
1988 | ||
1989 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { | |
1990 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { | |
1991 | mac->in_ifs_mode = true; | |
1992 | if (mac->current_ifs_val < mac->ifs_max_val) { | |
1993 | if (!mac->current_ifs_val) | |
1994 | mac->current_ifs_val = mac->ifs_min_val; | |
1995 | else | |
1996 | mac->current_ifs_val += | |
1997 | mac->ifs_step_size; | |
1998 | E1000_WRITE_REG(hw, E1000_AIT, | |
1999 | mac->current_ifs_val); | |
2000 | } | |
2001 | } | |
2002 | } else { | |
2003 | if (mac->in_ifs_mode && | |
2004 | (mac->tx_packet_delta <= MIN_NUM_XMITS)) { | |
2005 | mac->current_ifs_val = 0; | |
2006 | mac->in_ifs_mode = false; | |
2007 | E1000_WRITE_REG(hw, E1000_AIT, 0); | |
2008 | } | |
2009 | } | |
2010 | } | |
2011 | ||
2012 | /** | |
2013 | * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings | |
2014 | * @hw: pointer to the HW structure | |
2015 | * | |
2016 | * Verify that when not using auto-negotiation that MDI/MDIx is correctly | |
2017 | * set, which is forced to MDI mode only. | |
2018 | **/ | |
2019 | static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) | |
2020 | { | |
2021 | DEBUGFUNC("e1000_validate_mdi_setting_generic"); | |
2022 | ||
2023 | if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { | |
2024 | DEBUGOUT("Invalid MDI setting detected\n"); | |
2025 | hw->phy.mdix = 1; | |
2026 | return -E1000_ERR_CONFIG; | |
2027 | } | |
2028 | ||
2029 | return E1000_SUCCESS; | |
2030 | } | |
2031 | ||
2032 | /** | |
2033 | * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings | |
2034 | * @hw: pointer to the HW structure | |
2035 | * | |
2036 | * Validate the MDI/MDIx setting, allowing for auto-crossover during forced | |
2037 | * operation. | |
2038 | **/ | |
2039 | s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) | |
2040 | { | |
2041 | DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); | |
2042 | ||
2043 | return E1000_SUCCESS; | |
2044 | } | |
2045 | ||
2046 | /** | |
2047 | * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register | |
2048 | * @hw: pointer to the HW structure | |
2049 | * @reg: 32bit register offset such as E1000_SCTL | |
2050 | * @offset: register offset to write to | |
2051 | * @data: data to write at register offset | |
2052 | * | |
2053 | * Writes an address/data control type register. There are several of these | |
2054 | * and they all have the format address << 8 | data and bit 31 is polled for | |
2055 | * completion. | |
2056 | **/ | |
2057 | s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, | |
2058 | u32 offset, u8 data) | |
2059 | { | |
2060 | u32 i, regvalue = 0; | |
2061 | ||
2062 | DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); | |
2063 | ||
2064 | /* Set up the address and data */ | |
2065 | regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); | |
2066 | E1000_WRITE_REG(hw, reg, regvalue); | |
2067 | ||
2068 | /* Poll the ready bit to see if the MDI read completed */ | |
2069 | for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { | |
2070 | usec_delay(5); | |
2071 | regvalue = E1000_READ_REG(hw, reg); | |
2072 | if (regvalue & E1000_GEN_CTL_READY) | |
2073 | break; | |
2074 | } | |
2075 | if (!(regvalue & E1000_GEN_CTL_READY)) { | |
2076 | DEBUGOUT1("Reg %08x did not indicate ready\n", reg); | |
2077 | return -E1000_ERR_PHY; | |
2078 | } | |
2079 | ||
2080 | return E1000_SUCCESS; | |
2081 | } |