]>
Commit | Line | Data |
---|---|---|
11fdf7f2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
7c673cae FG |
2 | /******************************************************************************* |
3 | ||
4 | Intel(R) Gigabit Ethernet Linux driver | |
5 | Copyright(c) 2007-2013 Intel Corporation. | |
6 | ||
7c673cae FG |
7 | Contact Information: |
8 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
9 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
10 | ||
11 | *******************************************************************************/ | |
12 | ||
13 | #include "e1000_api.h" | |
14 | ||
15 | static void e1000_reload_nvm_generic(struct e1000_hw *hw); | |
16 | ||
17 | /** | |
18 | * e1000_init_nvm_ops_generic - Initialize NVM function pointers | |
19 | * @hw: pointer to the HW structure | |
20 | * | |
21 | * Setups up the function pointers to no-op functions | |
22 | **/ | |
23 | void e1000_init_nvm_ops_generic(struct e1000_hw *hw) | |
24 | { | |
25 | struct e1000_nvm_info *nvm = &hw->nvm; | |
26 | DEBUGFUNC("e1000_init_nvm_ops_generic"); | |
27 | ||
28 | /* Initialize function pointers */ | |
29 | nvm->ops.init_params = e1000_null_ops_generic; | |
30 | nvm->ops.acquire = e1000_null_ops_generic; | |
31 | nvm->ops.read = e1000_null_read_nvm; | |
32 | nvm->ops.release = e1000_null_nvm_generic; | |
33 | nvm->ops.reload = e1000_reload_nvm_generic; | |
34 | nvm->ops.update = e1000_null_ops_generic; | |
35 | nvm->ops.valid_led_default = e1000_null_led_default; | |
36 | nvm->ops.validate = e1000_null_ops_generic; | |
37 | nvm->ops.write = e1000_null_write_nvm; | |
38 | } | |
39 | ||
40 | /** | |
41 | * e1000_null_nvm_read - No-op function, return 0 | |
42 | * @hw: pointer to the HW structure | |
43 | **/ | |
44 | s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw, | |
45 | u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, | |
46 | u16 E1000_UNUSEDARG *c) | |
47 | { | |
48 | DEBUGFUNC("e1000_null_read_nvm"); | |
49 | return E1000_SUCCESS; | |
50 | } | |
51 | ||
52 | /** | |
53 | * e1000_null_nvm_generic - No-op function, return void | |
54 | * @hw: pointer to the HW structure | |
55 | **/ | |
56 | void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw) | |
57 | { | |
58 | DEBUGFUNC("e1000_null_nvm_generic"); | |
59 | return; | |
60 | } | |
61 | ||
62 | /** | |
63 | * e1000_null_led_default - No-op function, return 0 | |
64 | * @hw: pointer to the HW structure | |
65 | **/ | |
66 | s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw, | |
67 | u16 E1000_UNUSEDARG *data) | |
68 | { | |
69 | DEBUGFUNC("e1000_null_led_default"); | |
70 | return E1000_SUCCESS; | |
71 | } | |
72 | ||
73 | /** | |
74 | * e1000_null_write_nvm - No-op function, return 0 | |
75 | * @hw: pointer to the HW structure | |
76 | **/ | |
77 | s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw, | |
78 | u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, | |
79 | u16 E1000_UNUSEDARG *c) | |
80 | { | |
81 | DEBUGFUNC("e1000_null_write_nvm"); | |
82 | return E1000_SUCCESS; | |
83 | } | |
84 | ||
85 | /** | |
86 | * e1000_raise_eec_clk - Raise EEPROM clock | |
87 | * @hw: pointer to the HW structure | |
88 | * @eecd: pointer to the EEPROM | |
89 | * | |
90 | * Enable/Raise the EEPROM clock bit. | |
91 | **/ | |
92 | static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) | |
93 | { | |
94 | *eecd = *eecd | E1000_EECD_SK; | |
95 | E1000_WRITE_REG(hw, E1000_EECD, *eecd); | |
96 | E1000_WRITE_FLUSH(hw); | |
97 | usec_delay(hw->nvm.delay_usec); | |
98 | } | |
99 | ||
100 | /** | |
101 | * e1000_lower_eec_clk - Lower EEPROM clock | |
102 | * @hw: pointer to the HW structure | |
103 | * @eecd: pointer to the EEPROM | |
104 | * | |
105 | * Clear/Lower the EEPROM clock bit. | |
106 | **/ | |
107 | static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) | |
108 | { | |
109 | *eecd = *eecd & ~E1000_EECD_SK; | |
110 | E1000_WRITE_REG(hw, E1000_EECD, *eecd); | |
111 | E1000_WRITE_FLUSH(hw); | |
112 | usec_delay(hw->nvm.delay_usec); | |
113 | } | |
114 | ||
115 | /** | |
116 | * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM | |
117 | * @hw: pointer to the HW structure | |
118 | * @data: data to send to the EEPROM | |
119 | * @count: number of bits to shift out | |
120 | * | |
121 | * We need to shift 'count' bits out to the EEPROM. So, the value in the | |
122 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
123 | * In order to do this, "data" must be broken down into bits. | |
124 | **/ | |
125 | static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) | |
126 | { | |
127 | struct e1000_nvm_info *nvm = &hw->nvm; | |
128 | u32 eecd = E1000_READ_REG(hw, E1000_EECD); | |
129 | u32 mask; | |
130 | ||
131 | DEBUGFUNC("e1000_shift_out_eec_bits"); | |
132 | ||
133 | mask = 0x01 << (count - 1); | |
134 | if (nvm->type == e1000_nvm_eeprom_spi) | |
135 | eecd |= E1000_EECD_DO; | |
136 | ||
137 | do { | |
138 | eecd &= ~E1000_EECD_DI; | |
139 | ||
140 | if (data & mask) | |
141 | eecd |= E1000_EECD_DI; | |
142 | ||
143 | E1000_WRITE_REG(hw, E1000_EECD, eecd); | |
144 | E1000_WRITE_FLUSH(hw); | |
145 | ||
146 | usec_delay(nvm->delay_usec); | |
147 | ||
148 | e1000_raise_eec_clk(hw, &eecd); | |
149 | e1000_lower_eec_clk(hw, &eecd); | |
150 | ||
151 | mask >>= 1; | |
152 | } while (mask); | |
153 | ||
154 | eecd &= ~E1000_EECD_DI; | |
155 | E1000_WRITE_REG(hw, E1000_EECD, eecd); | |
156 | } | |
157 | ||
158 | /** | |
159 | * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM | |
160 | * @hw: pointer to the HW structure | |
161 | * @count: number of bits to shift in | |
162 | * | |
163 | * In order to read a register from the EEPROM, we need to shift 'count' bits | |
164 | * in from the EEPROM. Bits are "shifted in" by raising the clock input to | |
165 | * the EEPROM (setting the SK bit), and then reading the value of the data out | |
166 | * "DO" bit. During this "shifting in" process the data in "DI" bit should | |
167 | * always be clear. | |
168 | **/ | |
169 | static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) | |
170 | { | |
171 | u32 eecd; | |
172 | u32 i; | |
173 | u16 data; | |
174 | ||
175 | DEBUGFUNC("e1000_shift_in_eec_bits"); | |
176 | ||
177 | eecd = E1000_READ_REG(hw, E1000_EECD); | |
178 | ||
179 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
180 | data = 0; | |
181 | ||
182 | for (i = 0; i < count; i++) { | |
183 | data <<= 1; | |
184 | e1000_raise_eec_clk(hw, &eecd); | |
185 | ||
186 | eecd = E1000_READ_REG(hw, E1000_EECD); | |
187 | ||
188 | eecd &= ~E1000_EECD_DI; | |
189 | if (eecd & E1000_EECD_DO) | |
190 | data |= 1; | |
191 | ||
192 | e1000_lower_eec_clk(hw, &eecd); | |
193 | } | |
194 | ||
195 | return data; | |
196 | } | |
197 | ||
198 | /** | |
199 | * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion | |
200 | * @hw: pointer to the HW structure | |
201 | * @ee_reg: EEPROM flag for polling | |
202 | * | |
203 | * Polls the EEPROM status bit for either read or write completion based | |
204 | * upon the value of 'ee_reg'. | |
205 | **/ | |
206 | s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) | |
207 | { | |
208 | u32 attempts = 100000; | |
209 | u32 i, reg = 0; | |
210 | ||
211 | DEBUGFUNC("e1000_poll_eerd_eewr_done"); | |
212 | ||
213 | for (i = 0; i < attempts; i++) { | |
214 | if (ee_reg == E1000_NVM_POLL_READ) | |
215 | reg = E1000_READ_REG(hw, E1000_EERD); | |
216 | else | |
217 | reg = E1000_READ_REG(hw, E1000_EEWR); | |
218 | ||
219 | if (reg & E1000_NVM_RW_REG_DONE) | |
220 | return E1000_SUCCESS; | |
221 | ||
222 | usec_delay(5); | |
223 | } | |
224 | ||
225 | return -E1000_ERR_NVM; | |
226 | } | |
227 | ||
228 | /** | |
229 | * e1000_acquire_nvm_generic - Generic request for access to EEPROM | |
230 | * @hw: pointer to the HW structure | |
231 | * | |
232 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. | |
233 | * Return successful if access grant bit set, else clear the request for | |
234 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
235 | **/ | |
236 | s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) | |
237 | { | |
238 | u32 eecd = E1000_READ_REG(hw, E1000_EECD); | |
239 | s32 timeout = E1000_NVM_GRANT_ATTEMPTS; | |
240 | ||
241 | DEBUGFUNC("e1000_acquire_nvm_generic"); | |
242 | ||
243 | E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); | |
244 | eecd = E1000_READ_REG(hw, E1000_EECD); | |
245 | ||
246 | while (timeout) { | |
247 | if (eecd & E1000_EECD_GNT) | |
248 | break; | |
249 | usec_delay(5); | |
250 | eecd = E1000_READ_REG(hw, E1000_EECD); | |
251 | timeout--; | |
252 | } | |
253 | ||
254 | if (!timeout) { | |
255 | eecd &= ~E1000_EECD_REQ; | |
256 | E1000_WRITE_REG(hw, E1000_EECD, eecd); | |
257 | DEBUGOUT("Could not acquire NVM grant\n"); | |
258 | return -E1000_ERR_NVM; | |
259 | } | |
260 | ||
261 | return E1000_SUCCESS; | |
262 | } | |
263 | ||
264 | /** | |
265 | * e1000_standby_nvm - Return EEPROM to standby state | |
266 | * @hw: pointer to the HW structure | |
267 | * | |
268 | * Return the EEPROM to a standby state. | |
269 | **/ | |
270 | static void e1000_standby_nvm(struct e1000_hw *hw) | |
271 | { | |
272 | struct e1000_nvm_info *nvm = &hw->nvm; | |
273 | u32 eecd = E1000_READ_REG(hw, E1000_EECD); | |
274 | ||
275 | DEBUGFUNC("e1000_standby_nvm"); | |
276 | ||
277 | if (nvm->type == e1000_nvm_eeprom_spi) { | |
278 | /* Toggle CS to flush commands */ | |
279 | eecd |= E1000_EECD_CS; | |
280 | E1000_WRITE_REG(hw, E1000_EECD, eecd); | |
281 | E1000_WRITE_FLUSH(hw); | |
282 | usec_delay(nvm->delay_usec); | |
283 | eecd &= ~E1000_EECD_CS; | |
284 | E1000_WRITE_REG(hw, E1000_EECD, eecd); | |
285 | E1000_WRITE_FLUSH(hw); | |
286 | usec_delay(nvm->delay_usec); | |
287 | } | |
288 | } | |
289 | ||
290 | /** | |
291 | * e1000_stop_nvm - Terminate EEPROM command | |
292 | * @hw: pointer to the HW structure | |
293 | * | |
294 | * Terminates the current command by inverting the EEPROM's chip select pin. | |
295 | **/ | |
296 | static void e1000_stop_nvm(struct e1000_hw *hw) | |
297 | { | |
298 | u32 eecd; | |
299 | ||
300 | DEBUGFUNC("e1000_stop_nvm"); | |
301 | ||
302 | eecd = E1000_READ_REG(hw, E1000_EECD); | |
303 | if (hw->nvm.type == e1000_nvm_eeprom_spi) { | |
304 | /* Pull CS high */ | |
305 | eecd |= E1000_EECD_CS; | |
306 | e1000_lower_eec_clk(hw, &eecd); | |
307 | } | |
308 | } | |
309 | ||
310 | /** | |
311 | * e1000_release_nvm_generic - Release exclusive access to EEPROM | |
312 | * @hw: pointer to the HW structure | |
313 | * | |
314 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
315 | **/ | |
316 | void e1000_release_nvm_generic(struct e1000_hw *hw) | |
317 | { | |
318 | u32 eecd; | |
319 | ||
320 | DEBUGFUNC("e1000_release_nvm_generic"); | |
321 | ||
322 | e1000_stop_nvm(hw); | |
323 | ||
324 | eecd = E1000_READ_REG(hw, E1000_EECD); | |
325 | eecd &= ~E1000_EECD_REQ; | |
326 | E1000_WRITE_REG(hw, E1000_EECD, eecd); | |
327 | } | |
328 | ||
329 | /** | |
330 | * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write | |
331 | * @hw: pointer to the HW structure | |
332 | * | |
333 | * Setups the EEPROM for reading and writing. | |
334 | **/ | |
335 | static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) | |
336 | { | |
337 | struct e1000_nvm_info *nvm = &hw->nvm; | |
338 | u32 eecd = E1000_READ_REG(hw, E1000_EECD); | |
339 | u8 spi_stat_reg; | |
340 | ||
341 | DEBUGFUNC("e1000_ready_nvm_eeprom"); | |
342 | ||
343 | if (nvm->type == e1000_nvm_eeprom_spi) { | |
344 | u16 timeout = NVM_MAX_RETRY_SPI; | |
345 | ||
346 | /* Clear SK and CS */ | |
347 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
348 | E1000_WRITE_REG(hw, E1000_EECD, eecd); | |
349 | E1000_WRITE_FLUSH(hw); | |
350 | usec_delay(1); | |
351 | ||
352 | /* Read "Status Register" repeatedly until the LSB is cleared. | |
353 | * The EEPROM will signal that the command has been completed | |
354 | * by clearing bit 0 of the internal status register. If it's | |
355 | * not cleared within 'timeout', then error out. | |
356 | */ | |
357 | while (timeout) { | |
358 | e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, | |
359 | hw->nvm.opcode_bits); | |
360 | spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); | |
361 | if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) | |
362 | break; | |
363 | ||
364 | usec_delay(5); | |
365 | e1000_standby_nvm(hw); | |
366 | timeout--; | |
367 | } | |
368 | ||
369 | if (!timeout) { | |
370 | DEBUGOUT("SPI NVM Status error\n"); | |
371 | return -E1000_ERR_NVM; | |
372 | } | |
373 | } | |
374 | ||
375 | return E1000_SUCCESS; | |
376 | } | |
377 | ||
378 | /** | |
379 | * e1000_read_nvm_spi - Read EEPROM's using SPI | |
380 | * @hw: pointer to the HW structure | |
381 | * @offset: offset of word in the EEPROM to read | |
382 | * @words: number of words to read | |
383 | * @data: word read from the EEPROM | |
384 | * | |
385 | * Reads a 16 bit word from the EEPROM. | |
386 | **/ | |
387 | s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
388 | { | |
389 | struct e1000_nvm_info *nvm = &hw->nvm; | |
390 | u32 i = 0; | |
391 | s32 ret_val; | |
392 | u16 word_in; | |
393 | u8 read_opcode = NVM_READ_OPCODE_SPI; | |
394 | ||
395 | DEBUGFUNC("e1000_read_nvm_spi"); | |
396 | ||
397 | /* A check for invalid values: offset too large, too many words, | |
398 | * and not enough words. | |
399 | */ | |
400 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
401 | (words == 0)) { | |
402 | DEBUGOUT("nvm parameter(s) out of bounds\n"); | |
403 | return -E1000_ERR_NVM; | |
404 | } | |
405 | ||
406 | ret_val = nvm->ops.acquire(hw); | |
407 | if (ret_val) | |
408 | return ret_val; | |
409 | ||
410 | ret_val = e1000_ready_nvm_eeprom(hw); | |
411 | if (ret_val) | |
412 | goto release; | |
413 | ||
414 | e1000_standby_nvm(hw); | |
415 | ||
416 | if ((nvm->address_bits == 8) && (offset >= 128)) | |
417 | read_opcode |= NVM_A8_OPCODE_SPI; | |
418 | ||
419 | /* Send the READ command (opcode + addr) */ | |
420 | e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); | |
421 | e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); | |
422 | ||
423 | /* Read the data. SPI NVMs increment the address with each byte | |
424 | * read and will roll over if reading beyond the end. This allows | |
425 | * us to read the whole NVM from any offset | |
426 | */ | |
427 | for (i = 0; i < words; i++) { | |
428 | word_in = e1000_shift_in_eec_bits(hw, 16); | |
429 | data[i] = (word_in >> 8) | (word_in << 8); | |
430 | } | |
431 | ||
432 | release: | |
433 | nvm->ops.release(hw); | |
434 | ||
435 | return ret_val; | |
436 | } | |
437 | ||
438 | /** | |
439 | * e1000_read_nvm_eerd - Reads EEPROM using EERD register | |
440 | * @hw: pointer to the HW structure | |
441 | * @offset: offset of word in the EEPROM to read | |
442 | * @words: number of words to read | |
443 | * @data: word read from the EEPROM | |
444 | * | |
445 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
446 | **/ | |
447 | s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
448 | { | |
449 | struct e1000_nvm_info *nvm = &hw->nvm; | |
450 | u32 i, eerd = 0; | |
451 | s32 ret_val = E1000_SUCCESS; | |
452 | ||
453 | DEBUGFUNC("e1000_read_nvm_eerd"); | |
454 | ||
455 | /* A check for invalid values: offset too large, too many words, | |
456 | * too many words for the offset, and not enough words. | |
457 | */ | |
458 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
459 | (words == 0)) { | |
460 | DEBUGOUT("nvm parameter(s) out of bounds\n"); | |
461 | return -E1000_ERR_NVM; | |
462 | } | |
463 | ||
464 | for (i = 0; i < words; i++) { | |
465 | eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + | |
466 | E1000_NVM_RW_REG_START; | |
467 | ||
468 | E1000_WRITE_REG(hw, E1000_EERD, eerd); | |
469 | ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); | |
470 | if (ret_val) | |
471 | break; | |
472 | ||
473 | data[i] = (E1000_READ_REG(hw, E1000_EERD) >> | |
474 | E1000_NVM_RW_REG_DATA); | |
475 | } | |
476 | ||
477 | return ret_val; | |
478 | } | |
479 | ||
480 | /** | |
481 | * e1000_write_nvm_spi - Write to EEPROM using SPI | |
482 | * @hw: pointer to the HW structure | |
483 | * @offset: offset within the EEPROM to be written to | |
484 | * @words: number of words to write | |
485 | * @data: 16 bit word(s) to be written to the EEPROM | |
486 | * | |
487 | * Writes data to EEPROM at offset using SPI interface. | |
488 | * | |
489 | * If e1000_update_nvm_checksum is not called after this function , the | |
490 | * EEPROM will most likely contain an invalid checksum. | |
491 | **/ | |
492 | s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
493 | { | |
494 | struct e1000_nvm_info *nvm = &hw->nvm; | |
495 | s32 ret_val = -E1000_ERR_NVM; | |
496 | u16 widx = 0; | |
497 | ||
498 | DEBUGFUNC("e1000_write_nvm_spi"); | |
499 | ||
500 | /* A check for invalid values: offset too large, too many words, | |
501 | * and not enough words. | |
502 | */ | |
503 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
504 | (words == 0)) { | |
505 | DEBUGOUT("nvm parameter(s) out of bounds\n"); | |
506 | return -E1000_ERR_NVM; | |
507 | } | |
508 | ||
509 | while (widx < words) { | |
510 | u8 write_opcode = NVM_WRITE_OPCODE_SPI; | |
511 | ||
512 | ret_val = nvm->ops.acquire(hw); | |
513 | if (ret_val) | |
514 | return ret_val; | |
515 | ||
516 | ret_val = e1000_ready_nvm_eeprom(hw); | |
517 | if (ret_val) { | |
518 | nvm->ops.release(hw); | |
519 | return ret_val; | |
520 | } | |
521 | ||
522 | e1000_standby_nvm(hw); | |
523 | ||
524 | /* Send the WRITE ENABLE command (8 bit opcode) */ | |
525 | e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, | |
526 | nvm->opcode_bits); | |
527 | ||
528 | e1000_standby_nvm(hw); | |
529 | ||
530 | /* Some SPI eeproms use the 8th address bit embedded in the | |
531 | * opcode | |
532 | */ | |
533 | if ((nvm->address_bits == 8) && (offset >= 128)) | |
534 | write_opcode |= NVM_A8_OPCODE_SPI; | |
535 | ||
536 | /* Send the Write command (8-bit opcode + addr) */ | |
537 | e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); | |
538 | e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), | |
539 | nvm->address_bits); | |
540 | ||
541 | /* Loop to allow for up to whole page write of eeprom */ | |
542 | while (widx < words) { | |
543 | u16 word_out = data[widx]; | |
544 | word_out = (word_out >> 8) | (word_out << 8); | |
545 | e1000_shift_out_eec_bits(hw, word_out, 16); | |
546 | widx++; | |
547 | ||
548 | if ((((offset + widx) * 2) % nvm->page_size) == 0) { | |
549 | e1000_standby_nvm(hw); | |
550 | break; | |
551 | } | |
552 | } | |
553 | msec_delay(10); | |
554 | nvm->ops.release(hw); | |
555 | } | |
556 | ||
557 | return ret_val; | |
558 | } | |
559 | ||
560 | /** | |
561 | * e1000_read_pba_string_generic - Read device part number | |
562 | * @hw: pointer to the HW structure | |
563 | * @pba_num: pointer to device part number | |
564 | * @pba_num_size: size of part number buffer | |
565 | * | |
566 | * Reads the product board assembly (PBA) number from the EEPROM and stores | |
567 | * the value in pba_num. | |
568 | **/ | |
569 | s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, | |
570 | u32 pba_num_size) | |
571 | { | |
572 | s32 ret_val; | |
573 | u16 nvm_data; | |
574 | u16 pba_ptr; | |
575 | u16 offset; | |
576 | u16 length; | |
577 | ||
578 | DEBUGFUNC("e1000_read_pba_string_generic"); | |
579 | ||
580 | if (pba_num == NULL) { | |
581 | DEBUGOUT("PBA string buffer was null\n"); | |
582 | return -E1000_ERR_INVALID_ARGUMENT; | |
583 | } | |
584 | ||
585 | ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); | |
586 | if (ret_val) { | |
587 | DEBUGOUT("NVM Read Error\n"); | |
588 | return ret_val; | |
589 | } | |
590 | ||
591 | ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); | |
592 | if (ret_val) { | |
593 | DEBUGOUT("NVM Read Error\n"); | |
594 | return ret_val; | |
595 | } | |
596 | ||
597 | /* if nvm_data is not ptr guard the PBA must be in legacy format which | |
598 | * means pba_ptr is actually our second data word for the PBA number | |
599 | * and we can decode it into an ascii string | |
600 | */ | |
601 | if (nvm_data != NVM_PBA_PTR_GUARD) { | |
602 | DEBUGOUT("NVM PBA number is not stored as string\n"); | |
603 | ||
604 | /* make sure callers buffer is big enough to store the PBA */ | |
605 | if (pba_num_size < E1000_PBANUM_LENGTH) { | |
606 | DEBUGOUT("PBA string buffer too small\n"); | |
607 | return E1000_ERR_NO_SPACE; | |
608 | } | |
609 | ||
610 | /* extract hex string from data and pba_ptr */ | |
611 | pba_num[0] = (nvm_data >> 12) & 0xF; | |
612 | pba_num[1] = (nvm_data >> 8) & 0xF; | |
613 | pba_num[2] = (nvm_data >> 4) & 0xF; | |
614 | pba_num[3] = nvm_data & 0xF; | |
615 | pba_num[4] = (pba_ptr >> 12) & 0xF; | |
616 | pba_num[5] = (pba_ptr >> 8) & 0xF; | |
617 | pba_num[6] = '-'; | |
618 | pba_num[7] = 0; | |
619 | pba_num[8] = (pba_ptr >> 4) & 0xF; | |
620 | pba_num[9] = pba_ptr & 0xF; | |
621 | ||
622 | /* put a null character on the end of our string */ | |
623 | pba_num[10] = '\0'; | |
624 | ||
625 | /* switch all the data but the '-' to hex char */ | |
626 | for (offset = 0; offset < 10; offset++) { | |
627 | if (pba_num[offset] < 0xA) | |
628 | pba_num[offset] += '0'; | |
629 | else if (pba_num[offset] < 0x10) | |
630 | pba_num[offset] += 'A' - 0xA; | |
631 | } | |
632 | ||
633 | return E1000_SUCCESS; | |
634 | } | |
635 | ||
636 | ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); | |
637 | if (ret_val) { | |
638 | DEBUGOUT("NVM Read Error\n"); | |
639 | return ret_val; | |
640 | } | |
641 | ||
642 | if (length == 0xFFFF || length == 0) { | |
643 | DEBUGOUT("NVM PBA number section invalid length\n"); | |
644 | return -E1000_ERR_NVM_PBA_SECTION; | |
645 | } | |
646 | /* check if pba_num buffer is big enough */ | |
647 | if (pba_num_size < (((u32)length * 2) - 1)) { | |
648 | DEBUGOUT("PBA string buffer too small\n"); | |
649 | return -E1000_ERR_NO_SPACE; | |
650 | } | |
651 | ||
652 | /* trim pba length from start of string */ | |
653 | pba_ptr++; | |
654 | length--; | |
655 | ||
656 | for (offset = 0; offset < length; offset++) { | |
657 | ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); | |
658 | if (ret_val) { | |
659 | DEBUGOUT("NVM Read Error\n"); | |
660 | return ret_val; | |
661 | } | |
662 | pba_num[offset * 2] = (u8)(nvm_data >> 8); | |
663 | pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); | |
664 | } | |
665 | pba_num[offset * 2] = '\0'; | |
666 | ||
667 | return E1000_SUCCESS; | |
668 | } | |
669 | ||
670 | /** | |
671 | * e1000_read_pba_length_generic - Read device part number length | |
672 | * @hw: pointer to the HW structure | |
673 | * @pba_num_size: size of part number buffer | |
674 | * | |
675 | * Reads the product board assembly (PBA) number length from the EEPROM and | |
676 | * stores the value in pba_num_size. | |
677 | **/ | |
678 | s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) | |
679 | { | |
680 | s32 ret_val; | |
681 | u16 nvm_data; | |
682 | u16 pba_ptr; | |
683 | u16 length; | |
684 | ||
685 | DEBUGFUNC("e1000_read_pba_length_generic"); | |
686 | ||
687 | if (pba_num_size == NULL) { | |
688 | DEBUGOUT("PBA buffer size was null\n"); | |
689 | return -E1000_ERR_INVALID_ARGUMENT; | |
690 | } | |
691 | ||
692 | ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); | |
693 | if (ret_val) { | |
694 | DEBUGOUT("NVM Read Error\n"); | |
695 | return ret_val; | |
696 | } | |
697 | ||
698 | ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); | |
699 | if (ret_val) { | |
700 | DEBUGOUT("NVM Read Error\n"); | |
701 | return ret_val; | |
702 | } | |
703 | ||
704 | /* if data is not ptr guard the PBA must be in legacy format */ | |
705 | if (nvm_data != NVM_PBA_PTR_GUARD) { | |
706 | *pba_num_size = E1000_PBANUM_LENGTH; | |
707 | return E1000_SUCCESS; | |
708 | } | |
709 | ||
710 | ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); | |
711 | if (ret_val) { | |
712 | DEBUGOUT("NVM Read Error\n"); | |
713 | return ret_val; | |
714 | } | |
715 | ||
716 | if (length == 0xFFFF || length == 0) { | |
717 | DEBUGOUT("NVM PBA number section invalid length\n"); | |
718 | return -E1000_ERR_NVM_PBA_SECTION; | |
719 | } | |
720 | ||
721 | /* Convert from length in u16 values to u8 chars, add 1 for NULL, | |
722 | * and subtract 2 because length field is included in length. | |
723 | */ | |
724 | *pba_num_size = ((u32)length * 2) - 1; | |
725 | ||
726 | return E1000_SUCCESS; | |
727 | } | |
728 | ||
729 | ||
730 | ||
731 | ||
732 | ||
733 | /** | |
734 | * e1000_read_mac_addr_generic - Read device MAC address | |
735 | * @hw: pointer to the HW structure | |
736 | * | |
737 | * Reads the device MAC address from the EEPROM and stores the value. | |
738 | * Since devices with two ports use the same EEPROM, we increment the | |
739 | * last bit in the MAC address for the second port. | |
740 | **/ | |
741 | s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) | |
742 | { | |
743 | u32 rar_high; | |
744 | u32 rar_low; | |
745 | u16 i; | |
746 | ||
747 | rar_high = E1000_READ_REG(hw, E1000_RAH(0)); | |
748 | rar_low = E1000_READ_REG(hw, E1000_RAL(0)); | |
749 | ||
750 | for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) | |
751 | hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); | |
752 | ||
753 | for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) | |
754 | hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); | |
755 | ||
756 | for (i = 0; i < ETH_ADDR_LEN; i++) | |
757 | hw->mac.addr[i] = hw->mac.perm_addr[i]; | |
758 | ||
759 | return E1000_SUCCESS; | |
760 | } | |
761 | ||
762 | /** | |
763 | * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum | |
764 | * @hw: pointer to the HW structure | |
765 | * | |
766 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
767 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
768 | **/ | |
769 | s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) | |
770 | { | |
771 | s32 ret_val; | |
772 | u16 checksum = 0; | |
773 | u16 i, nvm_data; | |
774 | ||
775 | DEBUGFUNC("e1000_validate_nvm_checksum_generic"); | |
776 | ||
777 | for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { | |
778 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); | |
779 | if (ret_val) { | |
780 | DEBUGOUT("NVM Read Error\n"); | |
781 | return ret_val; | |
782 | } | |
783 | checksum += nvm_data; | |
784 | } | |
785 | ||
786 | if (checksum != (u16) NVM_SUM) { | |
787 | DEBUGOUT("NVM Checksum Invalid\n"); | |
788 | return -E1000_ERR_NVM; | |
789 | } | |
790 | ||
791 | return E1000_SUCCESS; | |
792 | } | |
793 | ||
794 | /** | |
795 | * e1000_update_nvm_checksum_generic - Update EEPROM checksum | |
796 | * @hw: pointer to the HW structure | |
797 | * | |
798 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
799 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
800 | * value to the EEPROM. | |
801 | **/ | |
802 | s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) | |
803 | { | |
804 | s32 ret_val; | |
805 | u16 checksum = 0; | |
806 | u16 i, nvm_data; | |
807 | ||
808 | DEBUGFUNC("e1000_update_nvm_checksum"); | |
809 | ||
810 | for (i = 0; i < NVM_CHECKSUM_REG; i++) { | |
811 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); | |
812 | if (ret_val) { | |
813 | DEBUGOUT("NVM Read Error while updating checksum.\n"); | |
814 | return ret_val; | |
815 | } | |
816 | checksum += nvm_data; | |
817 | } | |
818 | checksum = (u16) NVM_SUM - checksum; | |
819 | ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); | |
820 | if (ret_val) | |
821 | DEBUGOUT("NVM Write Error while updating checksum.\n"); | |
822 | ||
823 | return ret_val; | |
824 | } | |
825 | ||
826 | /** | |
827 | * e1000_reload_nvm_generic - Reloads EEPROM | |
828 | * @hw: pointer to the HW structure | |
829 | * | |
830 | * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the | |
831 | * extended control register. | |
832 | **/ | |
833 | static void e1000_reload_nvm_generic(struct e1000_hw *hw) | |
834 | { | |
835 | u32 ctrl_ext; | |
836 | ||
837 | DEBUGFUNC("e1000_reload_nvm_generic"); | |
838 | ||
839 | usec_delay(10); | |
840 | ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); | |
841 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
842 | E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); | |
843 | E1000_WRITE_FLUSH(hw); | |
844 | } | |
845 | ||
846 | /** | |
847 | * e1000_get_fw_version - Get firmware version information | |
848 | * @hw: pointer to the HW structure | |
849 | * @fw_vers: pointer to output version structure | |
850 | * | |
851 | * unsupported/not present features return 0 in version structure | |
852 | **/ | |
853 | void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) | |
854 | { | |
855 | u16 eeprom_verh, eeprom_verl, etrack_test, fw_version; | |
856 | u8 q, hval, rem, result; | |
857 | u16 comb_verh, comb_verl, comb_offset; | |
858 | ||
859 | memset(fw_vers, 0, sizeof(struct e1000_fw_version)); | |
860 | ||
861 | /* basic eeprom version numbers, bits used vary by part and by tool | |
862 | * used to create the nvm images */ | |
863 | /* Check which data format we have */ | |
864 | hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); | |
865 | switch (hw->mac.type) { | |
866 | case e1000_i211: | |
867 | e1000_read_invm_version(hw, fw_vers); | |
868 | return; | |
869 | case e1000_82575: | |
870 | case e1000_82576: | |
871 | case e1000_82580: | |
872 | /* Use this format, unless EETRACK ID exists, | |
873 | * then use alternate format | |
874 | */ | |
875 | if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) { | |
876 | hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); | |
877 | fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) | |
878 | >> NVM_MAJOR_SHIFT; | |
879 | fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK) | |
880 | >> NVM_MINOR_SHIFT; | |
881 | fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK); | |
882 | goto etrack_id; | |
883 | } | |
884 | break; | |
885 | case e1000_i210: | |
886 | if (!(e1000_get_flash_presence_i210(hw))) { | |
887 | e1000_read_invm_version(hw, fw_vers); | |
888 | return; | |
889 | } | |
890 | /* fall through */ | |
891 | case e1000_i350: | |
892 | case e1000_i354: | |
893 | /* find combo image version */ | |
894 | hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); | |
895 | if ((comb_offset != 0x0) && | |
896 | (comb_offset != NVM_VER_INVALID)) { | |
897 | ||
898 | hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset | |
899 | + 1), 1, &comb_verh); | |
900 | hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), | |
901 | 1, &comb_verl); | |
902 | ||
903 | /* get Option Rom version if it exists and is valid */ | |
904 | if ((comb_verh && comb_verl) && | |
905 | ((comb_verh != NVM_VER_INVALID) && | |
906 | (comb_verl != NVM_VER_INVALID))) { | |
907 | ||
908 | fw_vers->or_valid = true; | |
909 | fw_vers->or_major = | |
910 | comb_verl >> NVM_COMB_VER_SHFT; | |
911 | fw_vers->or_build = | |
912 | (comb_verl << NVM_COMB_VER_SHFT) | |
913 | | (comb_verh >> NVM_COMB_VER_SHFT); | |
914 | fw_vers->or_patch = | |
915 | comb_verh & NVM_COMB_VER_MASK; | |
916 | } | |
917 | } | |
918 | break; | |
919 | default: | |
920 | return; | |
921 | } | |
922 | hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); | |
923 | fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) | |
924 | >> NVM_MAJOR_SHIFT; | |
925 | ||
926 | /* check for old style version format in newer images*/ | |
927 | if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) { | |
928 | eeprom_verl = (fw_version & NVM_COMB_VER_MASK); | |
929 | } else { | |
930 | eeprom_verl = (fw_version & NVM_MINOR_MASK) | |
931 | >> NVM_MINOR_SHIFT; | |
932 | } | |
933 | /* Convert minor value to hex before assigning to output struct | |
934 | * Val to be converted will not be higher than 99, per tool output | |
935 | */ | |
936 | q = eeprom_verl / NVM_HEX_CONV; | |
937 | hval = q * NVM_HEX_TENS; | |
938 | rem = eeprom_verl % NVM_HEX_CONV; | |
939 | result = hval + rem; | |
940 | fw_vers->eep_minor = result; | |
941 | ||
942 | etrack_id: | |
943 | if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) { | |
944 | hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); | |
945 | hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); | |
946 | fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | |
947 | | eeprom_verl; | |
948 | } | |
949 | return; | |
950 | } |